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* fdt: add crypto node handling for MPC8{3, 5}xxE processorsKim Phillips2008-07-14-0/+9
| | | | | | | | Delete the crypto node if not on an E-processor. If on 8360 or 834x family, check rev and up-rev crypto node (to SEC rev. 2.4 property values) if on an 'EA' processor, e.g. MPC8349EA. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Merge commit 'wd/master'Jon Loeliger2008-07-10-3/+62
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| * ppc4xx: Enable support for > 2GB SDRAM on AMCC KatmaiStefan Roese2008-07-10-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM. To support such configurations, we "only" map the first 2GB via the TLB's. We need some free virtual address space for the remaining peripherals like, SoC devices, FLASH etc. Note that ECC is currently not supported on configurations with more than 2GB SDRAM. This is because we only map the first 2GB on such systems, and therefore the ECC parity byte of the remaining area can't be written. Signed-off-by: Stefan Roese <sr@denx.de>
| * Merge branch 'master' of git://www.denx.de/git/u-boot-mpc83xxWolfgang Denk2008-07-07-0/+7
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| | * mpc83xx: move CPU_TYPE_ENTRY over to processor.hKim Phillips2008-06-25-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to avoid this: cpu.c:47:1: warning: "CPU_TYPE_ENTRY" redefined In file included from cpu.c:33: /home/kim/git/u-boot/include/asm/processor.h:982:1: warning: this is the location of the previous definition Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | PPC: Added fls, fls64, __ilog2_u64, and ffs64 to bitopsKumar Gala2008-07-01-0/+52
| |/ | | | | | | | | | | | | fls64, __ilog2_u64, ffs64 are variants that work on an u64, and fls is used to implement them. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * Fix 4xx build issueAnatolij Gustschin2008-06-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Building for 4xx doesn't work since commit 4dbdb768: In file included from 4xx_pcie.c:28: include/asm/processor.h:971: error: expected ')' before 'ver' make[1]: *** [4xx_pcie.o] Error 1 This patch fixes the problem. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* | Feed the watchdog in u-boot for 8610 board.Jason Jin2008-07-07-1/+15
|/ | | | | | | | | The watchdog on 8610 board is enabled by setting sw[6] to on. Once enabled, the watchdog can not be disabled by software. So feed the dog in u-boot is necessary for normal operation. Signed-off-by: Jason Jin <Jason.jin@freescale.com>
* Change bd/gd memsize/ram_size to be phys_size_t.Becky Bruce2008-06-12-2/+2
| | | | | | | | | | Currently, both are defined as an unsigned long, but should be phys_size_t. This should result in no real change, since phys_size_t is currently an unsigned long for all the default configs. Also add print_lnum to cmd_bdinfo to deal with the potentially wider memsize. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xxWolfgang Denk2008-06-11-2/+1160
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| * ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part2Stefan Roese2008-06-03-0/+1156
| | | | | | | | | | | | | | This patch now adds a new header file (asm-ppc/ppc4xx-sdram.h) for all ppc4xx related SDRAM/DDR/DDR2 controller defines. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Enable Primordial Stack for 40x and Unify ECC HandlingGrant Erickson2008-06-03-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch (Part 1 of 2): * Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). * Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code. * Enables MCSR visibility on the 405EX(r). * Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value. - Removed, per Stefan Roese's request, defunct memory.c file for Makalu and rolled sdram_init from it into makalu.c. With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | FSL LAW: Add new interface to use the last free LAWKumar Gala2008-06-11-0/+1
| | | | | | | | | | | | | | | | LAWs have the concept of priority so its useful to be able to allocate the lowest (highest number) priority. We will end up using this with the new DDR code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | FSL LAW: Keep track of LAW allocationsKumar Gala2008-06-11-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make it so we keep track of which LAWs have allocated and provide a function (set_next_law) which can allocate a LAW for us if one is free. In the future we will move to doing more "dynamic" LAW allocation since the majority of users dont really care about what LAW number they are at. Also, add CONFIG_MPC8540 or CONFIG_MPC8560 to those boards which needed them Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | Added the upmconfig() function for 85xx.Sergei Poselenov2008-06-11-0/+4
| | | | | | | | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | PPC: add accessor macros to clear and set bits in one shotWolfgang Grandegger2008-06-10-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | PPC: add accessor macros to clear and set bits in one shot This patch adds macros from linux/include/asm-powerpc/io.h to clear and set bits in one shot using the in_be32, out_be32, etc. accessor functions. They are very handy to manipulate bits it I/O registers. This patch is required for my forthcoming FSL NAND UPM driver re-write and the support for the TQM8548 module. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* | 83xx/85xx/86xx: add more MxMR local bus definitionsWolfgang Grandegger2008-06-10-5/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 83xx/85xx/86xx: add more MxMR local bus definitions This patch adds more macro definitions for the UPM Machine Mode Registers They are copied from "include/mpc82xx.h" to simplify the merge of all 8xxx common local bus definitions into include/asm-ppc/fsl_lbc.h. They are required for my forthcoming FSL NAND UPM driver re-write and the support for the TQM8548 module. This patch is based on the following two patches from Anton Vorontsov: http://www.mail-archive.com/u-boot-users@lists.sourceforge.net/msg06511.html http://www.mail-archive.com/u-boot-users@lists.sourceforge.net/msg06587.html I leave coding style violation fixes, code beautification and name corrections to somebody else ;-(. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* | 83xx/85xx: further localbus cleanupsAnton Vorontsov2008-06-10-2/+15
| | | | | | | | | | | | | | Merge mpc85xx.h's LBC defines to fsl_lbc.h. Also, adopt ACS names from mpc85xx.h, so ACS_0b10 renamed to ACS_DIV4, ACS_0b11 to ACS_DIV2. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* | 83xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.hAnton Vorontsov2008-06-10-0/+251
| | | | | | | | | | | | | | This patch moves Freescale Localbus defines out of mpc83xx.h, so we could use it on MPC85xx and MPC86xx processors. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* | 85xx: expose cpu identificationKumar Gala2008-06-10-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | The current cpu identification code is used just to return the name of the processor at boot. There are some other locations that the name is useful (device tree setup). Expose the functionality to other bits of code. Also, drop the 'E' suffix and add it on by looking at the SVR version when we print this out. This is mainly to allow the most flexible use of the name. The device tree code tends to not care about the 'E' suffix. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Fix warnings from gcc-4.3.0 build on a ppc hostKumar Gala2008-06-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | * The cfi_flash.c memset fix actual allows the board to boot so there is a bit more going on here than just resolving warnings associated with uninitialized variables. * include/asm/bitops.h:302: warning: '__swab32p' is static but used in inline function 'ext2_find_next_zero_bit' which is not static Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | PPC: Add print_bats() to lib_ppc/bat_rw.cBecky Bruce2008-06-03-0/+1
| | | | | | | | | | | | | | | | | | This function prints the values of all the BAT register pairs - I needed this for debug earlier this week; adding it to lib_ppc so others can use it (and add it to reginfo commands if so desired). Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* | PPC: Change lib_ppc/bat_rw.c to use high batsBecky Bruce2008-06-03-1/+5
|/ | | | | | | | Currently, this code only deals with BATs 0-3, which makes it useless on systems that support BATs 4-7. Add the support for these registers. Signed-off-by: Becky Bruce <Becky.bruce@freescale.com>
* Merge branch 'lwmon5' of /home/wd/git/u-boot/projectsWolfgang Denk2008-05-21-0/+2
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| * POST: replace the LOGBUFF_INITIALIZED flag in gd->post_log_word (1 << 31) ↵Yuri Tikhonov2008-05-20-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | with the GD_FLG_LOGINIT flag in gd->flags. This way we become able to utilize the full post_log_word for POST activities (overwise, POST ECC, which has 0x8000 ID, could be erroneously treated as started in post_output_backlog() even if there was actually no POST ECC run (because of OCM POST failure, for example). Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
| * POST: add POST_STOP flagYuri Tikhonov2008-05-20-0/+1
| | | | | | | | | | | | | | | | Don't run futher tests in case of a test fails that is marked as POST_STOP. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
* | Big white-space cleanup.Wolfgang Denk2008-05-21-126/+126
|/ | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Add 405EX(r) revision C PVR definitions and detection codeStefan Roese2008-05-13-4/+8
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* PPC: fix map_physmem build warningBecky Bruce2008-05-10-1/+1
| | | | | | | map_physmem currently generates a warning when CONFIG_PHYS_64BIT is enabled. This quiets the warning. Signed-off-by: Becky Bruce <Becky.Bruce@freescale.com>
* 85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docsKumar Gala2008-04-29-2/+2
| | | | | | | All the 85xx and 86xx UM describe the register as timing_cfg_3 not as ext_refrec. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx/86xx: Rename DDR init address and init extended address registerKumar Gala2008-04-29-3/+3
| | | | | | | Rename init_addr and init_ext_addr to match the docs between 85xx and 86xx. Both now use 'init_addr' and 'init_ext_addr'. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc4xx: Fix compile warning of hcu4 boardStefan Roese2008-04-28-0/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xxWolfgang Denk2008-04-26-1/+4
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| * ppc4xx: Pass PCIe root-complex/endpoint configuration to Linux via the fdtStefan Roese2008-04-25-1/+4
| | | | | | | | | | | | | | | | | | | | The PCIe root-complex/endpoint setup as configured via the "pcie_mode" environment variable will now get passed to the Linux kernel by setting the device_type property of the PCIe device tree node. For normal root- complex configuration it will keep its defaults value of "pci" and for endpoint configuration it will get changed to "pci-endpoint". Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of /home/wd/git/u-boot/lwmon5Wolfgang Denk2008-04-25-0/+3
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: common/cmd_bootm.c common/cmd_log.c include/common.h post/board/lwmon5/Makefile post/board/lwmon5/dsp.c post/board/lwmon5/dspic.c post/board/lwmon5/fpga.c post/board/lwmon5/gdc.c post/board/lwmon5/sysmon.c post/board/lwmon5/watchdog.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | lwmon5 watchdog: limit trigger rateYuri Tikhonov2008-04-22-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Limit the rate of h/w watch-dog triggering on the LWMON5 board by the CONFIG_WD_MAX_RATE value. Note that an earlier version of this patch which used microseconds instead of ticks dis not work. The problem was that we used usec2ticks() to convert microseconds into ticks. usec2ticks() uses get_tbclk(), which in turn calls get_sys_info(). It turns out that this function does a lot of prolonged operations (like divisions) which take too much time so we do not trigger the watchdog in time, and it resets the system. Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
| * | The patch introduces the CRITICAL feature of POST tests. If the testYuri Tikhonov2008-03-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | marked as POST_CRITICAL fails then the alternative, post_critical, boot-command is used. If this command is not defined then U-Boot enters into interactive mode. Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
* | | Fix calculation of I2C clock for some 85xx chipsTimur Tabi2008-04-18-1/+3
| |/ |/| | | | | | | | | | | | | | | | | | | Some 85xx chips use CCB as the base clock for the I2C. Some use CCB/2, and some use CCB/3. There is no pattern that can be used to determine which chips use which frequency, so the only way to determine is to look up the actual SOC designation and use the right value for that SOC. Update immap_85xx.h to include the GUTS PORDEVSR2 register. Signed-off-by: Timur Tabi <timur@freescale.com>
* | Introduce phys_size_t and move phys_addr_t into asm/types.hKumar Gala2008-04-13-2/+8
| | | | | | | | | | | | | | Also add CONFIG_PHYS_64BIT on powerpc to deal with 32-bit ppc's that have larger physical addresses like 44x, 85xx, and 86xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc: Get rid of unused machine type definitionsWolfgang Denk2008-04-13-49/+0
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Coding Style cleanup; update CHANGELOGWolfgang Denk2008-04-13-143/+136
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | mpc83xx: unreinvent mem_clkKim Phillips2008-03-28-2/+1
| | | | | | | | | | | | | | delete ddr_clk and use mem_clk instead. Rename other ddr_*_clk to mem_*_clk for consistency's sake. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | 85xx: Expand CCSR space with more DDR controller registers.James Yang2008-03-26-4/+21
| | | | | | | | | | | | Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | 85xx: Speed up get_ddr_freq() and get_bus_freq()James Yang2008-03-26-2/+0
| | | | | | | | | | | | | | | | | | | | get_ddr_freq() and get_bus_freq() used get_sys_info() each time they were called. However, get_sys_info() recalculates extraneous information when called each time. Have get_ddr_freq() and get_bus_freq() return memoized values from global_data instead. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Update SVR numbers to expand supportAndy Fleming2008-03-26-12/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | FSL has taken to using SVR[16:23] as an SOC sub-version field. This is used to distinguish certain variants within an SOC family. To account for this, we add the SVR_SOC_VER() macro, and update the SVR_* constants to reflect the larger value. We also add SVR numbers for all of the current variants. Finally, to make things neater, rather than use an enormous switch statement to print out the CPU type, we create and array of SVR/name pairs (using a macro), and print out the CPU name that matches the SVR SOC version. Signed-off-by: Andy Fleming <afleming@freescale.com>
* | 85xx: Added support for multicore boot mechanismKumar Gala2008-03-26-0/+4
| | | | | | | | | | | | | | | | | | Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | 83xx: serdes setup routinesAnton Vorontsov2008-03-25-0/+21
| | | | | | | | | | | | This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* | 8xx: Update OF support on 8xxBryan O'Donoghue2008-03-25-1/+4
| | | | | | | | | | | | This patch does some shifting around of OF support on 8xx. Signed-off-by: Bryan O'Donoghue <bodonoghue@codehermit.ie>
* | The patch introduces the CRITICAL feature of POST tests. If the test marked ↵Yuri Tikhonov2008-03-18-0/+1
|/ | | | | | | as POST_CRITICAL fails then the alternative, post_critical, boot-command is used. If this command is not defined then U-Boot enters into interactive mode. Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
* ppc4xx: Add AMCC Canyonlands support (460EX) (3/3)Stefan Roese2008-03-15-2/+3
| | | | | | | This patch adds support for the AMCC Canyonlands 460EX evaluation board. Signed-off-by: Stefan Roese <sr@denx.de>
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