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* MPC512X: Cleanup bus clock names.Grzegorz Bernacki2008-01-12-1/+1
| | | | Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* ads5121: Added support for FDT.Grzegorz Bernacki2008-01-12-0/+3
| | | | Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* mpc83xx: Fix the typo in global data structDave Liu2008-01-10-1/+1
| | | | | | | Fix the typo in global_data.h Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* 85xx: add ability to upload QE firmwareTimur Tabi2008-01-09-2/+31
| | | | | | | | | | | Define the layout of a binary blob that contains a QE firmware and instructions on how to upload it. Add function qe_upload_firmware() to parse the blob and perform the actual upload. Add command-line command "qe fw" to take a firmware blob in memory and upload it. Update ft_cpu_setup() on 85xx to create the 'firmware' device tree node if U-Boot has uploaded a firmware. Fully define 'struct rsp' in immap_qe.h to include the actual RISC Special Registers. Signed-off-by: Timur Tabi <timur@freescale.com>
* 85xx: Remove cache config from configs.hKumar Gala2008-01-09-6/+8
| | | | | | | | | Either use the standard defines in asm/cache.h or grab the information at runtime from the L1CFG SPR. Also, minor cleanup in cache.h to make the code a bit more readable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Reworked FSL Book-E TLB macros to be more readableKumar Gala2008-01-09-0/+13
| | | | | | | | | | | The old macros made it difficult to know what WIMGE and perm bits were set for a TLB entry. Actually use the bit masks for these items since they are only a single bit. Also moved the macros into mmu.h out of e500.h since they aren't specific to e500. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Use FSL Book-E MMU macros from Linux KernelKumar Gala2008-01-09-47/+53
| | | | | | | | Grab the FSL Book-E MAS register macros from Linux. Also added defines for page sizes up to 4TB and removed SHAREN since it doesnt really exist. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-mpc83xxWolfgang Denk2008-01-09-4/+156
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| * mpc83xx: Add the support of MPC8315E SoCDave Liu2008-01-08-1/+65
| | | | | | | | | | | | | | The MPC8315E SoC including e300c3 core and new IP blocks, such as TDM, PCI Express and SATA controller. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * mpc83xx: Add the support of MPC837x SoCDave Liu2008-01-08-3/+91
| | | | | | | | | | | | | | The MPC837x SoC including e300c4 core and new IP blocks, such as SDHC, PCI Express and SATA controller. Signed-off-by: Dave Liu <daveliu@freescale.com>
* | ppc4xx: Move cpu/ppc4xx/vecnum.h into include pathMatthias Fuchs2008-01-09-0/+403
|/ | | | | | | This patch allows the use of 4xx interrupt vector number defines in board specific code outside cpu/ppc4xx. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* ppc4xx: Add functionality to GPIO supportLawrence R. Johnson2008-01-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes two additions to GPIO support: First, it adds function gpio_read_in_bit() to read the a bit from the GPIO Input Register (GPIOx_IR) in the same way that function gpio_read_out_bit() reads a bit from the GPIO Output Register (GPIOx_OR). Second, it modifies function gpio_set_chip_configuration() to provide an additional option for configuring the GPIO from the "CFG_4xx_GPIO_TABLE". According to the 440EPx User's Manual, when an alternate output is used, the three-state control is configured in one of two ways, depending on the particular output. The first option is to select the corresponding alternate three-state control in the GPIOx_TRSH/L registers. The second option is to select the GPIO Three-State Control Register (GPIOx_TCR) in the GPIOx_TRSH/L registers, and set the corresponding bit in the GPIOx_TCR register to enable the output. For example, the Manual specifies configuring the GPIO00 Alternate 1 Signal (PreAddr07) to use the alternate three-state control (first option), and specifies configuring the GPIO32 Alternate 1 Signal (USB2OM0) with the output enabled in the GPIOx_TCR register (second option). Currently, gpio_set_chip_configuration() configures all alternate signal outputs to use the first option. This patch allow the second option to be selected by setting the "out_val" element in the table entry to "GPIO_OUT_1". The first option is used when the "out_val" element is set to "GPIO_OUT_0". Because "out_val" is not currently used when an alternate signal is selected, and because all current GPIO tables set "out_val" to "GPIO_OUT_0" for all alternate signals, this patch should not change any existing configurations. Signed-off-by: Larry Johnson <lrj@acm.org>
* Merge commit 'wd/master'Jon Loeliger2008-01-03-51/+558
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| * Merge branch 'master' of /home/stefan/git/u-boot/u-boot into for-1.3.2-ver2Stefan Roese2007-12-27-46/+105
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| | * Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxWolfgang Denk2007-12-27-45/+48
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| | | * Handle MPC85xx PCIe reset errata (PCI-Ex 38)Kumar Gala2007-12-11-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On the MPC85xx boards that have PCIe enable the PCIe errata fix. (MPC8544DS, MPC8548CDS, MPC8568MDS). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | | * Use standard LAWAR_TRGT_IF_* defines for LAW setup on 85xxKumar Gala2007-12-11-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We already had defines for LAWAR_TRGT_IF_* that we should use rather than creating new ones. Also, added some missing defines for PCIE targets. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | | * Stop using immap_t on 85xxKumar Gala2007-12-11-24/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_*_ADDR as the base of the registers instead of getting it via &immap. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | | * Stop using immap_t for cpm offset on 85xxKumar Gala2007-12-11-21/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers instead of getting it via &immap->im_cpm. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | | * Stop using immap_t for guts offset on 85xxKumar Gala2007-12-11-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers instead of getting it via &immap->im_gur. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | Introduce map_physmem() and unmap_physmem()Haavard Skinnemoen2007-12-13-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | map_physmem() returns a virtual address which can be used to access a given physical address without involving the cache. unmap_physmem() should be called when the virtual address returned by map_physmem() is no longer needed. This patch adds a stub implementation which simply returns the physical address cast to a uchar * for all architectures except AVR32, which converts the physical address to an uncached virtual mapping. unmap_physmem() is a no-op on all architectures, but if any architecture needs to do such mappings through the TLB, this is the hook where those TLB entries can be invalidated. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
| | * | Implement __raw_{read,write}[bwl] on all architecturesHaavard Skinnemoen2007-12-13-1/+31
| | |/ | | | | | | | | | | | | | | | | | | | | | This adds implementations of __raw_read[bwl] and __raw_write[bwl] to m68k, ppc, nios and nios2. The m68k and ppc implementations were taken from Linux. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
| * | ppc4xx: Enable 405EX PCIe UTL register configurationStefan Roese2007-11-16-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Till now the UTL registers on 405EX were not initialized but left with their default values. This patch new initializes some of the UTL registers on 405EX. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platformsStefan Roese2007-11-15-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | - Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE - Cleanup of the 4xx GPIO functions - Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Add change_tlb function to modify I attribute of TLB(s)Stefan Roese2007-10-31-0/+1
| | | | | | | | | | | | | | | | | | | | | This function is used to either turn cache on or off in a specific memory area. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Rework 4xx cache supportStefan Roese2007-10-31-5/+16
| | | | | | | | | | | | | | | | | | | | | New cache handling functions added and all existing functions moved from start.S into seperate cache.S. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Correct UART input clock calculation and passing to fdtStefan Roese2007-10-31-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | We now use a value in the gd (global data) structure for the UART input frequency, since the PPC4xx_SYS_INFO struct is always rewritten completely in get_sys_info(). Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Define CONFIG_BOOKE for all PPC440 based processorsEugene O'Brien2007-10-31-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_BOOKE must be defined for PPC440 processors so that the proper SPR number is used to access system registers. Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Add PCIe endpoint support on Kilauea (405EX)Stefan Roese2007-10-31-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds endpoint support for the AMCC Kilauea eval board. It can be tested by connecting a reworked PCIe cable (only 1x lane singles connected) to another root-complex. In this test setup, a 64MB inbound window is configured at BAR0 which maps to 0 on the PLB side. So accessing this BAR0 from the root-complex will access the first 64MB of the SDRAM on the PPC side. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint modeStefan Roese2007-10-31-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for dynamic configuration of PCIe ports for the AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe boards Yucca & Katmai and the 405EX board Kilauea. This dynamic configuration is done via the "pcie_mode" environement variable. This variable can be set to "EP" or "RP" for endpoint or rootpoint mode. Multiple values can be joined via the ":" delimiter. Here an example: pcie_mode=RP:EP:EP This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2 as endpoint. Per default Yucca will be configured as: pcie_mode=RP:EP:EP Per default Katmai will be configured as: pcie_mode=RP:RP:REP Per default Kilauea will be configured as: pcie_mode=RP:RP Signed-off-by: Tirumala R Marri <tmarri@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Add PPC405EX supportStefan Roese2007-10-31-0/+5
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: 4xx_pcie: More general cleanup and 405EX PCIe support addedStefan Roese2007-10-31-12/+19
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Rename 405gp_pci to 4xx_pci since its used on all 4xx platformsStefan Roese2007-10-31-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | These files were introduced with the IBM 405GP but are currently used on all 4xx PPC platforms. So the name doesn't match the content anymore. This patch renames the files to 4xx_pci.c/h. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (3)Stefan Roese2007-10-31-2/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (3) This patch introduces macros like SDRN_PESDR_DLPSET(port) to access the SDR registers of the PCIe ports. This makes the overall design clearer, since it removed a lot of switch statements which are not needed anymore. Also, the functions ppc4xx_init_pcie_rootport() and ppc4xx_init_pcie_entport() are merged into a single function ppc4xx_init_pcie_port(), since most of the code was duplicated. This makes maintainance and porting to other 4xx platforms easier. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (2)Stefan Roese2007-10-31-9/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (2) This patch renames the functions from 440spe_ to 4xx_ with a little additional cleanup Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (1)Stefan Roese2007-10-31-0/+174
| |/ | | | | | | | | | | | | | | | | | | This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (1) This patch renames the files from 440spe_pcie to 4xx_pcie Signed-off-by: Stefan Roese <sr@denx.de>
* | Initial mpc8610hpcd cpu/, README and include/ files.Jon Loeliger2007-10-17-0/+1
|/ | | | | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Mahesh Jade <mahesh.jade@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-08-29-1/+1
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| * Merge with /home/stefan/git/u-boot/u-boot-ppc4xxStefan Roese2007-08-21-14/+821
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| * | ppc4xx: Add matrix kbd support to lwmon5 board (440EPx based)Stefan Roese2007-08-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the matrix keyboard on the lwmon5 board. Since the implementation in the dsPCI is kind of compatible with the "old" lwmon board, most of the code is copied from the lwmon board directory. Signed-off-by: Stefan Roese <sr@denx.de>
* | | IDE: - make ide_inb () and ide_outb () "weak", so boards canHeiko Schocher2007-08-28-0/+3
| |/ |/| | | | | | | | | | | | | | | define there own I/O functions. (Needed for the pcs440ep board). - The default I/O Functions are again 8 Bit accesses. - Added CONFIG_CMD_IDE for the pcs440ep Board. Signed-off-by: Heiko Schocher <hs@denx.de>
* | Fix numerous bugs in the 8568 UEC supportAndy Fleming2007-08-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Actually, fixed a large bug in the UEC for *all* platforms. How did this ever work? uec_init() did not follow the spec for eth_init(), and returned 0 on success. Switch it to return the link like tsec_init() (and 0 on error) The immap for the 8568 was defined based on MPC8568, rather than CONFIG_MPC8568 CONFIG_QE was off CONFIG_ETHPRIME was set to "Freescale GETH". Now is "FSL UEC0" Fixed a comment about the ranges for CONFIG_ETHPRIME if TSEC_ENET is enabled Signed-off-by: Andy Fleming <afleming@freescale.com>
* | Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-08-14-14/+821
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| * Add support for UEC to 8568Andy Fleming2007-08-14-5/+23
| | | | | | | | | | Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Add PCI support for MPC8568MDS boardHaiying Wang2007-08-14-0/+17
| | | | | | | | | | | | | | This patch is against u-boot-mpc85xx.git of www.denx.com Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>
| * 8544ds PCIE supportEd Swarthout2007-08-14-1/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address. Enable LBC and ECM errors and clear error registers. Add tftpflash env var to get uboot from tftp server and flash it. Add pci/pcie convenience env vars to display register space: "run pcie3regs" to see all pcie3 ccsr registers "run pcie3cfg" to see all cfg registers Whitespace cleanup and MPC8544DS.h Enable CONFIG_INTERRUPTS. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
| * 85xx start.S cleanup and exception supportAndy Fleming2007-08-14-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From: Ed Swarthout <Ed.Swarthout@freescale.com> Support external interrupts from platform to eliminate system hangs. Define CONFIG_INTERRUPTS board configure option to enable. Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC. Remove extra cpu initialization redundant with hardware initialization. Whitespace cleanup. Define and use _START_OFFSET consistent with other processors using ppc_asm.tmpl Move additional code from .text to boot page to make room for exception vectors at start of image. Handle Machine Check, External and Critical exceptions. Fix e500 machine check error determination in traps.c TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
| * fsl_pci_init cleanup.Ed Swarthout2007-08-10-1/+1
| | | | | | | | | | | | | | | | | | | | Do not enable normal errors created during probe (master abort, perr, and pcie Invalid Configuration access). Add CONFIG_PCI_NOSCAN board option to prevent bus scan. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
| * cpu/86xx fixes.Jon Loeliger2007-08-10-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove rev 1 fixes. Always set PICGCR_MODE. Enable machine check and provide board config option to set and handle SoC error interrupts. Include MSSSR0 in error message. Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
| * Merge with /home/wd/git/u-boot/custodian/u-boot-testingWolfgang Denk2007-08-06-1/+153
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