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* ppc/85xx,86xx: Handling Unknown SOC versionPoonam Aggrwal2009-09-08-0/+2
| | | | | | | | | | | Incase the system is detected with Unknown SVR, let the system boot with a default value and a proper message. Now with dynamic detection of SOC properties from SVR, this is necessary to prevent a crash. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/8xxx: Refactor code to determine if PCI is enabled & agent/hostKumar Gala2009-09-08-0/+5
| | | | | | | | | | | Refactor the code into a simple bitmask lookup table that determines if a given PCI controller is enabled and if its in host/root-complex or agent/end-point mode. Each processor in the PQ3/MPC86xx family specified different encodings for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Add a simple function to search the TLBKumar Gala2009-09-08-2/+5
| | | | | | | | | | | Allow us to search the TLB array based on an address. This is useful if we want to change an entry but dont know where it happens to be located. For example, the boot page mapping we use on MP or the flash TLB that we change the WIMGE settings for after we've relocated. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add support for setting IVORs to fixed offset defaultsKumar Gala2009-09-08-0/+12
| | | | | | | | | | | | In future Book-E implementations IVORs will most likely go away and be replaced with fixed offsets. The IVPR will continue to exist to allow for relocation of the interrupt vectors. This code adds support to setup the IVORs as their fixed offset values per the ISA 2.06 spec when we transition from u-boot to another OS either via 'bootm' or a cpu release. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/8xxx: Remove ddr_pd_cntl register since it doesn't existKumar Gala2009-09-08-2/+1
| | | | | | | | The ddr_pd_cntl isn't defined in any reference manual and thus we wil remove especially since we set it to 0, which would most likely be its POR value. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* driver/fsl_pci: Add fsl_pci_init_port function to initialize a PCI controllerPoonam Aggrwal2009-08-28-0/+26
| | | | | | | | | fsl_pci_init_port can be called from board specific PCI initialization routines to setup the PCI (or PCIe) controller. This will reduce code redundancy in most of the 85xx/86xx FSL board ports that setup PCI. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Added single core members of FSL P1xx/P2xx processors seriesPoonam Aggrwal2009-08-28-2/+6
| | | | | | | | P1011 - Single core variant of P1020 P2010 - Single core variant of P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Added CONFIG_MAX_CPUS for P1020Poonam Aggrwal2009-08-28-2/+2
| | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add L2SRAM Register's macro definitionMingkai Hu2009-08-28-0/+5
| | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Added P1020 Processor Support.Poonam Aggrwal2009-08-28-0/+2
| | | | | | | | | | | | | | P1020 is another member of QorIQ series of processors which falls in ULE category. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities. Also the SOC is pin compatible with P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add support for P2020RDB boardPoonam Aggrwal2009-08-28-1/+1
| | | | | | | | | | | | | The code base adds P1 & P2 RDB platforms support. The folder and file names can cater to future SOCs of P1/P2 family. P1 & P2 processors are 85xx platforms, part of Freescale QorIQ series. Tested following on P2020RDB: 1. eTSECs 2. DDR, NAND, NOR, I2C. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xxPoonam Aggrwal2009-08-28-2/+11
| | | | | | | | | | | | | The number of CPUs are getting detected dynamically by checking the processor SVR value. Also removed CONFIG_NUM_CPUS references from all the platforms with 85xx/86xx processors. This can help to use the same u-boot image across the platforms. Also revamped and corrected few Freescale Copyright messages. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Fold fsl_pci_setup_inbound_windows into fsl_pci_initKumar Gala2009-08-28-1/+0
| | | | | | | | Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Fold pci_setup_indirect into fsl_pci_initKumar Gala2009-08-28-1/+1
| | | | | | | | Every platform that calls fsl_pci_init calls pci_setup_indirect before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc4xx: Add basic support for AMCC PPC460EX/460GT rev B chipsStefan Roese2009-07-30-0/+2
| | | | | | | This patch is based on a diff created by Phong Vo from AMCC. Signed-off-by: Phong Vo <pvo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add struct for 4xx GPIO controller registersMatthias Fuchs2009-07-24-0/+24
| | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Replace 4xx lowercase SPR referencesMatthias Fuchs2009-07-24-0/+46
| | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* Add "chip_config" command for PPC4xx bootstrap configurationStefan Roese2009-07-24-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a generic command for programming I2C bootstrap eeproms on PPC4xx. An implementation for Canyonlands board is included. The command name is intentionally chosen not to be PPC4xx specific. This way other CPU's/SoC's can implement a similar command under the same name, perhaps with a different syntax. Usage on Canyonlands: => chip_config Available configurations (I2C address 0x52): 600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100 600-nand - NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100 800-nor - NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100 800-nand - NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100 1000-nor - NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100 1000-nand - NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100 1066-nor - NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88 *** 1066-nand - NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88 => chip_config 600-nor Using configuration: 600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100 done (dump via 'i2c md 52 0.1 10') Reset the board for the changes to take effect Other 4xx boards will be migrated to use this command soon as well. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Dirk Eibach <eibach@gdsys.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* 86xx: Rename ccsr_ddr's sdram_mode_1, sdram_cfg_1 fieldsPeter Tyser2009-07-22-2/+2
| | | | | | | | Rename sdram_mode_1 to sdram_mode and sdram_cfg_1 to sdram_cfg to match the 86xx user's manual and other Freescale architectures Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc: Fix compile error for boards with CONFIG_DDR_ECCPeter Tyser2009-07-17-4/+5
| | | | | | | | | | | | | A bug was introduced by commit e94e460c6e8741f42dab6d8dd4b596ba5d9d79ae which affected non-MPC83xx/85xx/86xx ppc boards which had CONFIG_DDR_ECC defined and resulted in errors such as: Configuring for canyonlands board... fsl_dma.c:50:2: error: #error "Freescale DMA engine not supported on your processor" make[1]: *** No rule to make target `.depend', needed by `libdma.a'. Stop. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2009-07-16-1/+10
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| * usb: mpc834x: added support of the MPH USB controller in addition to the DR oneValeriy Glushkov2009-07-14-1/+10
| | | | | | | | | | Signed-off-by: Valeriy Glushkov <gvv@lstec.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Merge branch 'asm-generic' of git://git.denx.de/u-boot-microblazeWolfgang Denk2009-07-16-138/+1
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| * asm-generic: Consolidate errno.h to asm-generic/errno.hMichal Simek2009-07-09-138/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch use blackfin errno.h implementation which correspond Linux kernel one. MIPS implemetation is different that's why I keep it. I removed ppc_error_no.h from Marvell boards which was the same too. I have got ack from ppc40x, blackfin, arm, coldfire and avr custodians. Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Michal Simek <monstr@monstr.eu>
* | MPC512x: factor out common codeWolfgang Denk2009-07-14-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have 3 boards for the MPC512x it turns out that they all use the very same fixed_sdram() code. This patch factors out this common code into cpu/mpc512x/fixed_sdram.c and adds a new header file, include/asm-ppc/mpc512x.h, with some macros, inline functions and prototype definitions specific to MPC512x systems. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* | MPC512x: Add MSCAN1...4 Clock Control RegistersWolfgang Denk2009-07-14-4/+5
|/ | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* 83xx: Add support for fsl_dma driverPeter Tyser2009-07-02-47/+43
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Reviewed-by: Ira W. Snyder <iws@ovro.caltech.edu> Tested-by: Ira W. Snyder <iws@ovro.caltech.edu> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Adds GPIO registers to MPC85xx Memory Map.Poonam Aggrwal2009-07-02-0/+11
| | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_dma: Break out common memory initialization functionPeter Tyser2009-07-01-0/+3
| | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_dma: Move dma function prototypes to common header filePeter Tyser2009-07-01-0/+5
| | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_dma: Add bitfield definitions for common registersPeter Tyser2009-07-01-0/+46
| | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 8xxx: Break out DMA code to a common filePeter Tyser2009-07-01-0/+7
| | | | | | | | DMA support is now enabled via the CONFIG_FSL_DMA define instead of the previous CONFIG_DDR_ECC Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 86xx: Add CPU_TYPE_ENTRY supportKumar Gala2009-06-30-1/+1
| | | | | | | | Unify with 83xx and 85xx and use CPU_TYPE_ENTRY. We are going to use this to convey the # of cores and DDR width in the near future so its good to keep in sync. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add PORBMSR and PORDEVSR shift definesPeter Tyser2009-06-12-0/+2
| | | | | | | | | Add defines similar to those already used for the the 86xx architecture. This will ease sharing of PCI code between the 85xx and 86xx architectures. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl/85xx, 86xx: Sync up DMA codePeter Tyser2009-06-12-0/+2
| | | | | | | | | | | | | | | | | | | | | The following changes were made to sync up the DMA code between the 85xx and 86xx architectures which will make it easier to break out common 8xxx DMA code: 85xx: - Don't set STRANSINT and SPCIORDER fields in SATR register. These bits only have an affect when the SBPATMU bit is set. - Write 0xffffffff instead of 0xfffffff to clear errors in the DMA status register. We may as well clear all 32 bits of the register... 86xx: - Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers - Add clearing of errors in the DMA status register when initializing the controller - Clear the channel start bit in the DMA mode register after a transfer Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl: Create common fsl_dma.h for 85xx and 86xx cpusPeter Tyser2009-06-12-146/+57
| | | | | | | | Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to reduce a large amount of code duplication Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* drivers/qe: Add more SNUM number for QEHaiying Wang2009-06-12-1/+4
| | | | | | | | | Some QE chips like 8569 need more SNUM numbers for supporting 4 UECs in RGMII- 1000 mode. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* drivers/qe: Change QE RISC ALLOCATION to support 4 RISCsHaiying Wang2009-06-12-0/+8
| | | | | | | | | Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and define MAX_QE_RISC for QE based silicons. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add QE clk supportHaiying Wang2009-06-12-0/+2
| | | | | | Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: Timur Tabi <Timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Added MPC8535/E identifiersKumar Gala2009-06-12-0/+2
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mcp512x: Add macros for SCFR LPC divisor accessStefan Roese2009-06-12-0/+3
| | | | | | Thos macros will be used by the esd mecp5123 board. Signed-off-by: Stefan Roese <sr@denx.de>
* mpc85xx: USB: Add supportVivek Mahajan2009-06-12-1/+4
| | | | | | | | The following patch adds 85xx-specific USB support and also revamps Copyright in immap_85xx.h Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
* mpc83xx: USB: Reorganized its supportVivek Mahajan2009-06-12-1/+4
| | | | | | | | | | | | | | | | | The following patch reorganizes/reworks the USB support for mpc83xx as under:- * Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to cpu/mpx83xx/cpu_init.c * Board specific usb_phy_type is read from the environment * Adds USB EHCI specific structure in include/usb/ehci-fsl.h * Copyrights revamped in most of the following files Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
* 83xx: Replace CONFIG_MPC83[0-9]X with MPC83[0-9]xPeter Tyser2009-06-12-14/+14
| | | | | | | | Use the standard lowercase "x" capitalization that other Freescale architectures use for CPU defines to prevent confusion and errors Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* 83xx: Replace CONFIG_MPC83XX with CONFIG_MPC83xxPeter Tyser2009-06-12-6/+6
| | | | | | | | Use the standard lowercase "xx" capitalization that other Freescale architectures use for CPU defines to prevent confusion and errors Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* MPC512x: remove include/mpc512x.hWolfgang Denk2009-06-12-1/+323
| | | | | | | | | | | | | | | | | | | | Move needed definitions (register descriptions etc.) from include/mpc512x.h into include/asm-ppc/immap_512x.h. Instead of using a #define'd register offset, use a function that provides the PATA controller's base address. All the rest of include/mpc512x.h are register offset definitions which can be eliminated by proper use of C structures. There are only a few register offsets remaining that are needed in cpu/mpc512x/start.S; for these we provide cpu/mpc512x/asm-offsets.h which is intended as a temporary workaround only. In a later patch this file will be removed, too, and then auto-generated from the respective C structs. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: John Rigby <jcrigby@gmail.com>
* MPC512x: add more hardware description to immap_512x.hWolfgang Denk2009-06-12-5/+248
| | | | | | | | | | | | | - add GPIO module description - add Address Latch Timing Register description - add IO Control Memory Map - add FEC Memory Map Also change board/freescale/mpc5121ads/mpc5121ads.c and cpu/mpc512x/iopin.c as needed. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: John Rigby <jcrigby@gmail.com>
* 85xx: Fix MURAM size for MPC8569Haiying Wang2009-06-12-2/+7
| | | | | | | MPC8569 has 128K bytes MURAM. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Replace __attribute references with __attribute__Peter Tyser2009-04-28-1/+1
| | | | | | | | __attribute__ follows gcc's documented syntax and is generally more common than __attribute. This change is only asthetic and should not affect functionality. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Update CHANGELOG, coding style cleanup.Wolfgang Denk2009-04-05-1/+0
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