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* Move architecture-specific includes to arch/$ARCH/include/asmPeter Tyser2010-04-13-19980/+0
| | | | | | | | This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* 85xx: Set HID1[mbdd] on e500v2 rev5.0 or greaterSandeep Gopalpet2010-04-07-0/+1
| | | | | | | The HID1[MBDD] bit is new on rev5.0 or greater cores and will optimize the performance of mbar/eieio instructions. Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
* 85xx: Added various P1012/P1013/P1021/P1022 definesKumar Gala2010-04-07-1/+10
| | | | | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list * Added number of LAWs for P1012/P1013/P1021/P1022 * Set CONFIG_MAX_CPUS to 2 for P1021/P1022 * PCI port config Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add defines for BUCSR bits to make code more readableKumar Gala2010-04-07-0/+3
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc86xx: set the DDR BATs after calculating true DDR sizeTimur Tabi2010-03-30-1/+5
| | | | | | | | | | | | | | | | | | | | After determining how much DDR is actually in the system, set DBAT0 and IBAT0 accordingly. This ensures that the CPU won't attempt to access (via speculation) addresses outside of actual memory. On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB and kept that way. If the system has less than 2GB of memory (typical for an MPC8610 HPCD), the CPU may attempt to access this memory during speculation. The zlib code is notorious for generating such memory reads, and indeed on the MPC8610, uncompressing the Linux kernel causes a machine check (without this patch). Currently we are limited to power of two sized DDR since we only use a single bat. If a non-power of two size is used that is less than CONFIG_MAX_MEM_MAPPED u-boot will crash. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Fix enabling of L1 cache parity on secondary coresKumar Gala2010-03-30-0/+2
| | | | | | | | | | | Use the same code between primary and secondary cores to init the L1 cache. We were not enabling cache parity on the secondary cores. Also, reworked the L1 cache init code to match the e500mc L2 init code that first invalidates the cache and locks. Than enables the cache and makes sure its enabled before continuing. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* PPC: Record U-Boot's relocated address in RAM and show in bdinfo.Richard Retanubun2010-03-11-2/+0
| | | | | | | | | | | This patch uses gd->relocaddr variable to store uboot's relocated address in RAM and shows it in bdinfo command. This patch moves CONFIG_AMIGAONEG3SE style copying of the address in board_init_f to just before relocation is actually done. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com> Tested-by: Detlev Zundel <dzu@denx.de>
* ppc4xx: Corrected EBC register bit definitionsEugene O'Brien2010-03-02-6/+18
| | | | | | | | | | Corrected the bit field positions of the external master priority low and the external master priority high values in the EBC configuration register. These bit field positions differ between PPC405 and PPC440 processors Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com> Signed-off-by: Stefan Roese <sr@denx.de>
* 86xx: Add support for 'cpu disable' commandKumar Gala2010-01-26-15/+18
| | | | | | Support disabling of a core via user command 'cpu disable'. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* lmb: only force on arches that use itMike Frysinger2010-01-21-0/+2
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* ppc/p4080: Add Corenet Platform Cache (CPC) registersBecky Bruce2010-01-05-0/+75
| | | | | Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl-ddr: add override for the Rtt_WrDave Liu2010-01-05-0/+1
| | | | | | | | | Different boards may require different settings of Dynamic ODT (Rtt_Wr). We provide a means to allow the board specific code to provide its own value of Rtt_Wr. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl-ddr: add the override for write levelingDave Liu2010-01-05-1/+6
| | | | | | | | add the override for write leveling sampling and start time according to specific board. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_law: add SRIO2 target id and law_size_bits() macroLi Yang2010-01-05-0/+3
| | | | | Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc: Added macro to test for specific SVR revisionKumar Gala2010-01-05-0/+3
| | | | | | | Various SoC errata are specific to a given revision of silicon. This patch gives us a simple macro to use when doing such tests. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Add tracking of TLB CAM usageKumar Gala2010-01-05-0/+12
| | | | | | | | | We need to track which TLB CAM entries are used to allow us to "dynamically" allocate entries later in the code. For example the SPD DDR code today hard codes which TLB entries it uses. We can now make that pick entries that are free. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/8xxx: Remove is_fsl_pci_agentKumar Gala2010-01-05-2/+3
| | | | | | | | All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent that uses the standard PCI programming model to determine host vs agent/end-point. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* NET: Base support for etsec2.0Kumar Gala2010-01-05-3/+13
| | | | | | | | | | 1. Modified the tsec_mdio structure to include the new regs 2. Modified the MDIO_BASE_ADDR so that it will handle both older version and new version of etsec. Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* NET: Move MDIO regs out of TSEC SpaceSandeep Gopalpet2010-01-05-2/+19
| | | | | | | | | | | | | | | | | Moved the mdio regs out of the tsec structure,and provided different offsets for tsec base and mdio base so that provision for etsec2.0 can be provided. This patch helps in providing the support for etsec2.0 In etsec2.0, the MDIO register space and the etsec reg space are different. Also, moved the TSEC_BASE_ADDR and MDIO_BASE_ADDR definitons into platform specific files. Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/p4080: Added p4080 SERDES registers & USB offsetKumar Gala2010-01-05-0/+87
| | | | | | | | Added immap definition for SERDES registers on p4080, the USB offset (since it was missing) and a GPL header. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc4xx: Consolidate pci_master_init() functionStefan Roese2009-11-19-0/+1
| | | | | | | | This patch removes the duplicted implementations of the pci_master_init() function by introducing a weak default function for it. It can be overridden by a board specific version. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate pci_pre_init() functionStefan Roese2009-11-19-0/+5
| | | | | | | | | This patch removes the duplicted implementations of the pci_pre_init() function by introducing a weak default function for it. This weak default has a different implementation for some PPC variants. It can be overridden by a board specific version. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate pci_target_init() functionStefan Roese2009-11-19-0/+2
| | | | | | | | | | This patch removes the duplicted implementations of the pci_target_init() function by introducing a weak default function for it. This weak default has a different implementation for 440EP(x)/GR(x) PPC's. It can be overridden by a board specific version (e.g. PMC440, korat). Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* fsl_pci_init_port end-point initialization is brokenEd Swarthout2009-11-04-0/+1
| | | | | | | | | | | | | commit 70ed869e broke fsl pcie end-point initialization. Returning 0 is not correct. The function must return the first free bus number for the next controller. fsl_pci_init() must still be called and a bus allocated even if the controller is an end-point. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Revert "ppc/85xx/pci: fsl_pci_init: pcie agent mode support"Kumar Gala2009-11-04-2/+1
| | | | | | | | | | | This reverts commit 70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc. There isn't any need to modify the API for fsl_pci_init_port to pass the status of host/agent(end-point) status. We can determine that internally to fsl_pci_init_port. Revert the patch that makes the API change. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: MP Boot Page Translation updatePeter Tyser2009-10-27-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx/pci: fsl_pci_init: pcie agent mode supportVivek Mahajan2009-10-27-1/+2
| | | | | | | | | | | | | | | Originally written by Jason Jin and Mingkai Hu for mpc8536. When QorIQ based board is configured as a PCIe agent, then unlock/enable inbound PCI configuration cycles and init a 4K inbound memory window; so that a PCIe host can access the PCIe agents SDRAM at address 0x0 * Supported in fsl_pci_init_port() after adding pcie_ep as a param * Revamped copyright in drivers/pci/fsl_pci_init.c * Mods in 85xx based board specific pci init after this change Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc512x: fix System Clock Control constants for USB1 & USB2Martha Stan2009-10-18-2/+2
| | | | Signer-off-by: Martha Stan <mmarx@silicontkx.com>
* Merge branch 'reloc'Wolfgang Denk2009-10-09-1/+4
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| * ppc: Remove reloc_off field from global_data structurePeter Tyser2009-10-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that proper relocation is supported, the reloc_off field is no longer necessary. Note that the location of the standalone application jump table pointer in the global data structure is affected by this change, breaking execution of standalone applications compiled for previous versions of U-Boot. We therefore increment XF_VERSION to 6 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
| * ppc: Enable full relocation to RAMPeter Tyser2009-10-03-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The following changes allow U-Boot to fully relocate from flash to RAM: - Remove linker scripts' .fixup sections from the .text section - Add -mrelocatable to PLATFORM_RELFLAGS for all boards - Define CONFIG_RELOC_FIXUP_WORKS for all boards Previously, U-Boot would partially relocate, but statically initialized pointers needed to be manually relocated. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | mpc512x: fix fixed_sdram() init code.Wolfgang Denk2009-10-08-1/+12
| | | | | | | | | | | | | | | | | | | | Commit 054197ba and later fixes used an array to initialize some of the MDDRC parameters; however, the use of an array turned out to be a bad idea as it was not possible to correlate structure entries to array indices in readable and reliable way. Now we use a struct instead, which makes this self-explanatory. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | ppc4xx: Add PPC405EX(r) Rev D supportStefan Roese2009-10-07-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately some Rev D PPC405EX/405EXr PVR's are identical with older 405EX(r) parts. Here a list: 0x12911475 - 405EX Rev D with Security *and* 405EX Rev A/B witout Sec 0x12911473 - 405EX Rev D without Security *and* 405EXr Rev A/B with Sec Since there are only a few older parts in the field, this patch now changes the PVR's above to represent the new Rev D versions. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Phong Vo" <pvo@amcc.com>
* | ppc4xx: Merge PPC4xx DDR and DDR2 ECC handlingStefan Roese2009-10-02-3/+4
|/ | | | | | | | | | | | | | | | | This patch merges the ECC handling (ECC parity byte writing) into one file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx. This exception is because only those PPC's use the completely different Denali SDRAM controller core. Previously we had two routines to generate/write the ECC parity bytes. With this patch we now only have one core function left. Tested on Kilauea (no ECC) and Katmai (with and without ECC). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Felix Radensky <felix@embedded-sol.com> Cc: Grant Erickson <gerickson@nuovations.com> Cc: Pieter Voorthuijsen <pv@prodrive.nl>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2009-09-30-1589/+1586
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| * ppc/85xx: Clean up immap_85xx.hKumar Gala2009-09-28-1589/+1586
| | | | | | | | | | | | | | | | | | * Converted all white space to tabs * Converted all types to u8/u16/u32 * Reduce lines to fit in 80 columns * Renamed MPC85xx_{Q,B}MAN -> FSL_CORENET_{Q,B}MAN Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper caseStefan Roese2009-09-28-51/+35
| | | | | | | | | | | | | | | | | | The latest PPC4xx register cleanup patch missed some SDRAM defines. This patch now changes lower case UIC defines to upper case. Also some names are changed to match the naming in the IBM/AMCC users manuals (e.g. mem_mcopt1 -> SDRAM0_CFG). Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Convert PPC4xx UIC defines from lower case to upper caseStefan Roese2009-09-28-49/+37
|/ | | | | | | The latest PPC4xx register cleanup patch missed the UIC defines. This patch now changes lower case UIC defines to upper case. Signed-off-by: Stefan Roese <sr@denx.de>
* Fix "ppc/85xx: Clean up use of LAWAR defines" breakageWolfgang Denk2009-09-25-1/+1
| | | | | | | | | Commit 002741ae86 modified include/asm-ppc/mmu.h such that the LAWAR_ defines were only enabled for the 83xx platform, but they are also needed on MPC512x system. Enabling these for E300 systems seems thus more appropriate. Signed-off-by: Wolfgang Denk <wd@denx.de>
* mpc512x: Streamlined fixed_sdram() init sequence.Martha M Stan2009-09-25-1/+5
| | | | | | | | | | | | | | | | | | | Signed-off-by: Martha M Stan <mmarx@silicontkx.com> Minor cleanup: Re-ordered default_mddrc_config[] to have matching indices. This allows to use the same index "N" for source and target fields; before, we had code like this out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]); which always looked like a copy & paste error because 2 != 3. Also, use NULL when meaning a null pointer. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc/p4080: Add various p4080 related defines (and p4040)Kumar Gala2009-09-24-2/+8
| | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p4080 & p4040 to cpu_type_list and SVR list * Added number of LAWs for p4080 * Set CONFIG_MAX_CPUS to 8 for p4080 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/p4080: Add support for CoreNet style platform LAWsKumar Gala2009-09-24-0/+31
| | | | | | | | | | | | | | | | On CoreNet based platforms the LAW address is split between an high & low register and we no longer shift the address. Also, the target IDs on CoreNet platforms have been completely re-assigned. Additionally, added a new find_law() API to which LAW an address hits in. This is need for the CoreNet style boot release code since it will need to determine what the target ID should be set to for boot window translation. Finally, enamed LAWAR_EN to LAW_EN and moved to header so we can use it elsewhere. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/p4080: Add p4080 platform immap definitionsKumar Gala2009-09-24-20/+271
| | | | | | | | | | | | | | | The p4080 SoC has a significant amount of commonality with the 85xx/PQ3 platform. We reuse the 85xx immap and just add new definitions for local access and global utils. The global utils is now broken into global utils, clocking and run control/power management. The offsets from CCSR for a number of blocks have also changed. We introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of platform from the new p4080 platform. We don't use QoirQ as there are products (like p2020) that are PQ3 based platforms but have the QoirQ name. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* immap_85xx: add porpllsr's plat ratio definitionMingkai Hu2009-09-24-0/+2
| | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_pci: create a SET_STD_PCI_INFO() helper wrapperPaul Gortmaker2009-09-24-0/+12
| | | | | | | | Recycle the recently added PCI-e wrapper used to reduce board duplication of code by creating a similar version for plain PCI. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Clean up use of LAWAR definesKumar Gala2009-09-24-7/+2
| | | | | | | | | On 85xx platforms we shouldn't be using any LAWAR_* defines but using the LAW_* ones provided by fsl-law.h. Rename any such uses and limit the LAWAR_ to the 83xx platform as the only user so we will get compile errors in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Fix LCRR_CLKDIV definesKumar Gala2009-09-24-0/+8
| | | | | | | | | | | | | | | | | | | | | For some reason the CLKDIV field varies between SoC in how it interprets the bit values. All 83xx and early (e500v1) PQ3 devices support: clk/2: CLKDIV = 2 clk/4: CLKDIV = 4 clk/8: CLKDIV = 8 Newer PQ3 (e500v2) and MPC86xx support: clk/4: CLKDIV = 2 clk/8: CLKDIV = 4 clk/16: CLKDIV = 8 Ensure that the MPC86xx and MPC85xx still get the same behavior and make the defines reflect their logical view (not the value of the field). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Peter Tyser <ptyser@xes-inc.com>
* Correct ffs/fls regression for PowerPC etcSimon Kagstrom2009-09-17-2/+2
| | | | | | | | | | | | | | | Commits 02f99901ed1c9d828e3ea117f94ce2264bf8389e 52d61227b66d4099b39c8309ab37cb67ee09a405 introduced a regression where platform-specific ffs/fls implementations were defined away. This patch corrects that by using PLATFORM_xxx instead of the name itself. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de>
* ppc/85xx: Repack tlb_table to save spaceKumar Gala2009-09-15-11/+10
| | | | | | | | We can pack the initial tlb_table in MAS register format and use write_tlb to set things up. This savings can be helpful for NAND style first stage boot loaders. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Introduce low level write_tlb functionKumar Gala2009-09-15-0/+4
| | | | | | | | | Factor out the code we use to actually write a tlb entry. set_tlb is a logical view of the TLB while write_tlb is a low level matching the MAS registers. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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