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* ppc4xx: Add AMCC Canyonlands support (460EX) (3/3)Stefan Roese2008-03-15-2/+3
| | | | | | | This patch adds support for the AMCC Canyonlands 460EX evaluation board. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add basic support for AMCC 460EX/460GT (3/5)Stefan Roese2008-03-15-3/+157
| | | | | | This patch adds basic support for the AMCC 460EX/460GT PPC's. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: program_tlb now uses 64bit physical addessStefan Roese2008-03-15-9/+9
| | | | | | | | This patch changes the physical addess parameter from 32bit to 64bit. This is needed for 36bit 4xx platforms to access areas located beyond the 4GB border, like SoC peripherals (EBC etc.). Signed-off-by: Stefan Roese <sr@denx.de>
* MPC5121e ADS PCI support take 3John Rigby2008-03-02-6/+56
| | | | | | | | | | | | | | | | Adds PCI support for MPC5121 Tested with drivers/net/rtl8139.c Support is conditional since PCI on old silicon does not work. ads5121_PCI_config turns on PCI In this version, condition compilation of PCI code has been moved from ifdef in board/ads5121/pci.c to board/ads5121/Makefile as suggested by Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: John Rigby <jrigby@freescale.com>
* Remove the __STRICT_ANSI__ check from the __u64/__s64 declaration on 32bit ↵Shinya Kuribayashi2008-02-23-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | targets. ---------------------------------------------------------------- Olaf Hering [Wed, 17 Oct 2007 06:27:13 +0000 (23:27 -0700)] Remove the __STRICT_ANSI__ check from the __u64/__s64 declaration on 32bit targets. GCC can be made to warn about usage of long long types with ISO C90 (-ansi), but only with -pedantic. You can write this in a way that even then it doesn't cause warnings, namely by: #ifdef __GNUC__ __extension__ typedef __signed__ long long __s64; __extension__ typedef unsigned long long __u64; #endif The __extension__ keyword in front of this switches off any pedantic warnings for this expression. Signed-off-by: Olaf Hering <olh@suse.de> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> ---------------------------------------------------------------- Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
* Merge branch 'master' of git://www.denx.de/git/u-boot-mpc86xxWolfgang Denk2008-02-22-4/+8
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| * 86xx: Fix GUR PCI config registers properly.Jon Loeliger2008-02-20-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Back in commit 975a083a5ef785c414b35f9c5b8ae25b26b41524 where I tried to "8610HPCD: Fix typos in two PCI setup registers", I botched it due to not realizing that 8610 and 8641 had different Global Utility Register defintions, one of which was like 85xx, and the other wasn't. Correct this problem by introducing two symbols, one for each 86xx SoC, but neither of which is named anything like 85xx. My bad. Lovely Wednesday with git bisect. You know. Signed-off-by: Jon Loeliger <jdl@freescale.com>
| * 8610HPCD: Fix typos in two PCI setup registers.Jon Loeliger2008-02-19-2/+0
| | | | | | | | | | | | | | | | | | The two symbols MPC86xx_PORDEVSR_IO_SEL and MPC86xx_PORBMSR_HA were erroneously present as 85xx names and values, leftover from the clone wars. Fix this by removing the 85xx cruft from the 86xx codebase. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* | Remove duplicate defines for ARRAY_SIZEKumar Gala2008-02-22-2/+0
|/ | | | | | | A few duplicate of the ARRAY_SIZE macro sneaked in since we put the define in common.h. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-mpc86xxWolfgang Denk2008-02-15-0/+6
|\ | | | | | | | | | | | | | | Conflicts: common/cmd_reginfo.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Add CFG_MPC86xx_DDR_ADDR and CFG_MPC86xx_DDR2_ADDR symbolsJon Loeliger2008-02-13-0/+5
| | | | | | | | | | | | These replace direct structure references for IMMR sections. Signed-off-by: Jon Loeliger <jdl@freescale.com>
| * 86xx: Add print_laws function to fsl_law.cBecky Bruce2008-01-24-0/+1
| | | | | | | | | | | | | | This can be used for debug, and will be used by board code to help implement reginfo. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* | 85xx, 86xx: Determine I2C clock frequencies and store in global_dataTimur Tabi2008-02-14-2/+4
| | | | | | | | | | | | | | | | | | Update global_data to define i2c1_clk and i2c2_clk to 85xx and 86xx. Update the get_clocks() function in 85xx and 86xx to determine the I2C clock frequency and store it in gd->i2c1_clk and gd->i2c2_clk. Signed-off-by: Timur Tabi <timur@freescale.com>
* | PPC: Use r2 instead of r29 as global data pointerWolfgang Denk2008-02-14-1/+1
|/ | | | | | | | | | | | R29 was an unlucky choice as with recent toolchains (gcc-4.2.x) gcc will refuse to use load/store multiple insns; instead, it issues a list of simple load/store instructions upon function entry and exit, resulting in bigger code size, which in turn makes the build for a few boards fail. Use r2 instead. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxWolfgang Denk2008-01-23-0/+111
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| * 85xx: Introduce new tlb APIKumar Gala2008-01-17-0/+31
| | | | | | | | | | | | | | | | | | | | Add a set of functions to manipulate TLB entries: * set_tlb() - write a tlb entry * invalidate_tlb() - invalidate a tlb array * disable_tlb() - disable a variable size tlb entry * init_tlbs() - setup initial tlbs based on static table Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Move LAW init code into CKumar Gala2008-01-16-0/+80
| | | | | | | | | | | | | | | | | | | | | | Move the initialization of the LAWs into C code and provide an API to allow modification of LAWs after init. Board code is responsible to provide a law_table and num_law_entries. We should be able to use the same code on 86xx as well. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | mpc83xx: Correct the struct spi8xxx in mpc8xxx_spi.hDave Liu2008-01-18-15/+1
| | | | | | | | | | | | | | | | | | | | | | The commit 04a9e1180ac76a7bacc15a6fcd95ad839d65bddb cause the 83xx immap broken, so the DMA and PCI will be failed. The patch fix the struct spi8xxx and rm struct spi83xx. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | codingstyle cleanup for spi driverKim Phillips2008-01-17-2/+1
| | | | | | | | | | | | ..and rm unused CONFIG_FSL_SPI define Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Add support for a Freescale non-CPM SPI controllerBen Warren2008-01-17-4/+54
|/ | | | | | | | | This patch adds support for the SPI controller found on Freescale PowerPC processors such as the MCP834x family. Additionally, a new config option, CONFIG_HARD_SPI, is added for general purpose SPI controller use. Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* MPC512X: Cleanup bus clock names.Grzegorz Bernacki2008-01-12-1/+1
| | | | Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* ads5121: Added support for FDT.Grzegorz Bernacki2008-01-12-0/+3
| | | | Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* mpc83xx: Fix the typo in global data structDave Liu2008-01-10-1/+1
| | | | | | | Fix the typo in global_data.h Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* 85xx: add ability to upload QE firmwareTimur Tabi2008-01-09-2/+31
| | | | | | | | | | | Define the layout of a binary blob that contains a QE firmware and instructions on how to upload it. Add function qe_upload_firmware() to parse the blob and perform the actual upload. Add command-line command "qe fw" to take a firmware blob in memory and upload it. Update ft_cpu_setup() on 85xx to create the 'firmware' device tree node if U-Boot has uploaded a firmware. Fully define 'struct rsp' in immap_qe.h to include the actual RISC Special Registers. Signed-off-by: Timur Tabi <timur@freescale.com>
* 85xx: Remove cache config from configs.hKumar Gala2008-01-09-6/+8
| | | | | | | | | Either use the standard defines in asm/cache.h or grab the information at runtime from the L1CFG SPR. Also, minor cleanup in cache.h to make the code a bit more readable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Reworked FSL Book-E TLB macros to be more readableKumar Gala2008-01-09-0/+13
| | | | | | | | | | | The old macros made it difficult to know what WIMGE and perm bits were set for a TLB entry. Actually use the bit masks for these items since they are only a single bit. Also moved the macros into mmu.h out of e500.h since they aren't specific to e500. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Use FSL Book-E MMU macros from Linux KernelKumar Gala2008-01-09-47/+53
| | | | | | | | Grab the FSL Book-E MAS register macros from Linux. Also added defines for page sizes up to 4TB and removed SHAREN since it doesnt really exist. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-mpc83xxWolfgang Denk2008-01-09-4/+156
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| * mpc83xx: Add the support of MPC8315E SoCDave Liu2008-01-08-1/+65
| | | | | | | | | | | | | | The MPC8315E SoC including e300c3 core and new IP blocks, such as TDM, PCI Express and SATA controller. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * mpc83xx: Add the support of MPC837x SoCDave Liu2008-01-08-3/+91
| | | | | | | | | | | | | | The MPC837x SoC including e300c4 core and new IP blocks, such as SDHC, PCI Express and SATA controller. Signed-off-by: Dave Liu <daveliu@freescale.com>
* | ppc4xx: Move cpu/ppc4xx/vecnum.h into include pathMatthias Fuchs2008-01-09-0/+403
|/ | | | | | | This patch allows the use of 4xx interrupt vector number defines in board specific code outside cpu/ppc4xx. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* ppc4xx: Add functionality to GPIO supportLawrence R. Johnson2008-01-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes two additions to GPIO support: First, it adds function gpio_read_in_bit() to read the a bit from the GPIO Input Register (GPIOx_IR) in the same way that function gpio_read_out_bit() reads a bit from the GPIO Output Register (GPIOx_OR). Second, it modifies function gpio_set_chip_configuration() to provide an additional option for configuring the GPIO from the "CFG_4xx_GPIO_TABLE". According to the 440EPx User's Manual, when an alternate output is used, the three-state control is configured in one of two ways, depending on the particular output. The first option is to select the corresponding alternate three-state control in the GPIOx_TRSH/L registers. The second option is to select the GPIO Three-State Control Register (GPIOx_TCR) in the GPIOx_TRSH/L registers, and set the corresponding bit in the GPIOx_TCR register to enable the output. For example, the Manual specifies configuring the GPIO00 Alternate 1 Signal (PreAddr07) to use the alternate three-state control (first option), and specifies configuring the GPIO32 Alternate 1 Signal (USB2OM0) with the output enabled in the GPIOx_TCR register (second option). Currently, gpio_set_chip_configuration() configures all alternate signal outputs to use the first option. This patch allow the second option to be selected by setting the "out_val" element in the table entry to "GPIO_OUT_1". The first option is used when the "out_val" element is set to "GPIO_OUT_0". Because "out_val" is not currently used when an alternate signal is selected, and because all current GPIO tables set "out_val" to "GPIO_OUT_0" for all alternate signals, this patch should not change any existing configurations. Signed-off-by: Larry Johnson <lrj@acm.org>
* Merge commit 'wd/master'Jon Loeliger2008-01-03-51/+558
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| * Merge branch 'master' of /home/stefan/git/u-boot/u-boot into for-1.3.2-ver2Stefan Roese2007-12-27-46/+105
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| | * Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxWolfgang Denk2007-12-27-45/+48
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| | | * Handle MPC85xx PCIe reset errata (PCI-Ex 38)Kumar Gala2007-12-11-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On the MPC85xx boards that have PCIe enable the PCIe errata fix. (MPC8544DS, MPC8548CDS, MPC8568MDS). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | | * Use standard LAWAR_TRGT_IF_* defines for LAW setup on 85xxKumar Gala2007-12-11-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We already had defines for LAWAR_TRGT_IF_* that we should use rather than creating new ones. Also, added some missing defines for PCIE targets. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | | * Stop using immap_t on 85xxKumar Gala2007-12-11-24/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_*_ADDR as the base of the registers instead of getting it via &immap. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | | * Stop using immap_t for cpm offset on 85xxKumar Gala2007-12-11-21/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers instead of getting it via &immap->im_cpm. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | | * Stop using immap_t for guts offset on 85xxKumar Gala2007-12-11-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers instead of getting it via &immap->im_gur. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | Introduce map_physmem() and unmap_physmem()Haavard Skinnemoen2007-12-13-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | map_physmem() returns a virtual address which can be used to access a given physical address without involving the cache. unmap_physmem() should be called when the virtual address returned by map_physmem() is no longer needed. This patch adds a stub implementation which simply returns the physical address cast to a uchar * for all architectures except AVR32, which converts the physical address to an uncached virtual mapping. unmap_physmem() is a no-op on all architectures, but if any architecture needs to do such mappings through the TLB, this is the hook where those TLB entries can be invalidated. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
| | * | Implement __raw_{read,write}[bwl] on all architecturesHaavard Skinnemoen2007-12-13-1/+31
| | |/ | | | | | | | | | | | | | | | | | | | | | This adds implementations of __raw_read[bwl] and __raw_write[bwl] to m68k, ppc, nios and nios2. The m68k and ppc implementations were taken from Linux. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
| * | ppc4xx: Enable 405EX PCIe UTL register configurationStefan Roese2007-11-16-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Till now the UTL registers on 405EX were not initialized but left with their default values. This patch new initializes some of the UTL registers on 405EX. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platformsStefan Roese2007-11-15-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | - Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE - Cleanup of the 4xx GPIO functions - Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Add change_tlb function to modify I attribute of TLB(s)Stefan Roese2007-10-31-0/+1
| | | | | | | | | | | | | | | | | | | | | This function is used to either turn cache on or off in a specific memory area. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Rework 4xx cache supportStefan Roese2007-10-31-5/+16
| | | | | | | | | | | | | | | | | | | | | New cache handling functions added and all existing functions moved from start.S into seperate cache.S. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Correct UART input clock calculation and passing to fdtStefan Roese2007-10-31-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | We now use a value in the gd (global data) structure for the UART input frequency, since the PPC4xx_SYS_INFO struct is always rewritten completely in get_sys_info(). Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Define CONFIG_BOOKE for all PPC440 based processorsEugene O'Brien2007-10-31-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_BOOKE must be defined for PPC440 processors so that the proper SPR number is used to access system registers. Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Add PCIe endpoint support on Kilauea (405EX)Stefan Roese2007-10-31-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds endpoint support for the AMCC Kilauea eval board. It can be tested by connecting a reworked PCIe cable (only 1x lane singles connected) to another root-complex. In this test setup, a 64MB inbound window is configured at BAR0 which maps to 0 on the PLB side. So accessing this BAR0 from the root-complex will access the first 64MB of the SDRAM on the PPC side. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint modeStefan Roese2007-10-31-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for dynamic configuration of PCIe ports for the AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe boards Yucca & Katmai and the 405EX board Kilauea. This dynamic configuration is done via the "pcie_mode" environement variable. This variable can be set to "EP" or "RP" for endpoint or rootpoint mode. Multiple values can be joined via the ":" delimiter. Here an example: pcie_mode=RP:EP:EP This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2 as endpoint. Per default Yucca will be configured as: pcie_mode=RP:EP:EP Per default Katmai will be configured as: pcie_mode=RP:RP:REP Per default Kilauea will be configured as: pcie_mode=RP:RP Signed-off-by: Tirumala R Marri <tmarri@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
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