summaryrefslogtreecommitdiff
path: root/include/asm-ppc/mmu.h
Commit message (Collapse)AuthorAgeLines
* ppc4xx: program_tlb now uses 64bit physical addessStefan Roese2008-03-15-9/+9
| | | | | | | | This patch changes the physical addess parameter from 32bit to 64bit. This is needed for 36bit 4xx platforms to access areas located beyond the 4GB border, like SoC peripherals (EBC etc.). Signed-off-by: Stefan Roese <sr@denx.de>
* Remove duplicate defines for ARRAY_SIZEKumar Gala2008-02-22-1/+0
| | | | | | | A few duplicate of the ARRAY_SIZE macro sneaked in since we put the define in common.h. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Introduce new tlb APIKumar Gala2008-01-17-0/+31
| | | | | | | | | | Add a set of functions to manipulate TLB entries: * set_tlb() - write a tlb entry * invalidate_tlb() - invalidate a tlb array * disable_tlb() - disable a variable size tlb entry * init_tlbs() - setup initial tlbs based on static table Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Reworked FSL Book-E TLB macros to be more readableKumar Gala2008-01-09-0/+13
| | | | | | | | | | | The old macros made it difficult to know what WIMGE and perm bits were set for a TLB entry. Actually use the bit masks for these items since they are only a single bit. Also moved the macros into mmu.h out of e500.h since they aren't specific to e500. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Use FSL Book-E MMU macros from Linux KernelKumar Gala2008-01-09-47/+53
| | | | | | | | Grab the FSL Book-E MAS register macros from Linux. Also added defines for page sizes up to 4TB and removed SHAREN since it doesnt really exist. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of /home/stefan/git/u-boot/u-boot into for-1.3.2-ver2Stefan Roese2007-12-27-1/+3
|\
| * Use standard LAWAR_TRGT_IF_* defines for LAW setup on 85xxKumar Gala2007-12-11-1/+3
| | | | | | | | | | | | | | | | We already had defines for LAWAR_TRGT_IF_* that we should use rather than creating new ones. Also, added some missing defines for PCIE targets. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc4xx: Add change_tlb function to modify I attribute of TLB(s)Stefan Roese2007-10-31-0/+1
|/ | | | | | | This function is used to either turn cache on or off in a specific memory area. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add remove_tlb() function to remove a mem area from TLB setupStefan Roese2007-07-16-0/+3
| | | | | | | | | | The new function remove_tlb() can be used to remove the TLB's used to map a specific memory region. This is especially useful for the DDR(2) setup routines which configure the SDRAM area temporarily as a cached area (for speedup on auto-calibration and ECC generation) and later need this area uncached for normal usage. Signed-off-by: Stefan Roese <sr@denx.de>
* Changed BOOKE_PAGESZ_nGB to BOOKE_PAGESZ_nGAndy Fleming2007-04-23-2/+2
| | | | | | | The other pagesz constants use one letter to specify order of magnitude. Also change the one reference to it in mpc8548cds/init.S Signed-off-by: Andy Fleming <afleming@freescale.com>
* u-boot: Enable PCI function and add PEX & rapidio memory map on MPC8548CDS boardZang Roy-r619112007-04-23-0/+1
| | | | | | Enable PCI function and add PEX & rapidio memory map on MPC8548CDS board. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
* [PATCH] PPC4xx: Add 440SP(e) DDR2 SPD DIMM supportStefan Roese2007-02-20-42/+166
| | | | | | | | | | | | | | | | | This patch adds support for the DDR2 controller used on the 440SP and 440SPe. It is tested on the Katmai (440SPe) eval board and works fine with the following DIMM modules: - Corsair CM2X512-5400C4 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM) This patch also adds the nice functionality to dynamically create the TLB entries for the SDRAM (tlb.c). So we should never run into such problems with wrong (too short) TLB initialization again on these platforms. Signed-off-by: Stefan Roese <sr@denx.de>
* Fixed leading whitespace issues.Jon Loeliger2006-10-13-3/+2
| | | | | | Removed spurious LAWAR thing. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Merge branch 'mpc86xx'Jon Loeliger2006-08-22-9/+9
|\
| * Cleanup poorly introduced whitespace.Jon Loeliger2006-08-22-9/+9
| |
* | Merge branch 'wd'Jon Loeliger2006-08-09-0/+41
|\ \ | |/ |/|
| * Add support for AMCC 440SPe CPU based eval board (Yucca).Marian Balakowicz2006-06-30-0/+41
| |
* | Initial support for MPC8641 HPCN board.Jon Loeliger2006-04-26-1/+14
|/
* Patch by Jon Loeliger, 17 June 2004:wdenk2004-07-09-0/+2
| | | | | | | | Completion of the 8540ADS/8560ADS updates: Fix some PCI and Rapid I/O memory maps, Initialize both TSEC 1 and 2, Initialize SDRAM Update MAINTAINER for 85xx boards and README.mpc85xxads
* * Patches by Xianghua Xiao, 15 Oct 2003:wdenk2003-10-15-0/+98
| | | | | | | | - Added Motorola CPU 8540/8560 support (cpu/85xx) - Added Motorola MPC8540ADS board support (board/mpc8540ads) - Added Motorola MPC8560ADS board support (board/mpc8560ads) * Minor code cleanup
* Initial revisionwdenk2002-03-31-0/+373
generated by cgit v1.1 at 2024-11-09 12:14:29 +0000