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path: root/include/asm-ppc/immap_85xx.h
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* Move architecture-specific includes to arch/$ARCH/include/asmPeter Tyser2010-04-13-2106/+0
| | | | | | | | This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc/p4080: Add Corenet Platform Cache (CPC) registersBecky Bruce2010-01-05-0/+75
| | | | | Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* NET: Base support for etsec2.0Kumar Gala2010-01-05-1/+5
| | | | | | | | | | 1. Modified the tsec_mdio structure to include the new regs 2. Modified the MDIO_BASE_ADDR so that it will handle both older version and new version of etsec. Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* NET: Move MDIO regs out of TSEC SpaceSandeep Gopalpet2010-01-05-0/+5
| | | | | | | | | | | | | | | | | Moved the mdio regs out of the tsec structure,and provided different offsets for tsec base and mdio base so that provision for etsec2.0 can be provided. This patch helps in providing the support for etsec2.0 In etsec2.0, the MDIO register space and the etsec reg space are different. Also, moved the TSEC_BASE_ADDR and MDIO_BASE_ADDR definitons into platform specific files. Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/p4080: Added p4080 SERDES registers & USB offsetKumar Gala2010-01-05-0/+87
| | | | | | | | Added immap definition for SERDES registers on p4080, the USB offset (since it was missing) and a GPL header. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Clean up immap_85xx.hKumar Gala2009-09-28-1589/+1586
| | | | | | | | | * Converted all white space to tabs * Converted all types to u8/u16/u32 * Reduce lines to fit in 80 columns * Renamed MPC85xx_{Q,B}MAN -> FSL_CORENET_{Q,B}MAN Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/p4080: Add p4080 platform immap definitionsKumar Gala2009-09-24-20/+267
| | | | | | | | | | | | | | | The p4080 SoC has a significant amount of commonality with the 85xx/PQ3 platform. We reuse the 85xx immap and just add new definitions for local access and global utils. The global utils is now broken into global utils, clocking and run control/power management. The offsets from CCSR for a number of blocks have also changed. We introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of platform from the new p4080 platform. We don't use QoirQ as there are products (like p2020) that are PQ3 based platforms but have the QoirQ name. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* immap_85xx: add porpllsr's plat ratio definitionMingkai Hu2009-09-24-0/+2
| | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/8xxx: Remove ddr_pd_cntl register since it doesn't existKumar Gala2009-09-08-1/+1
| | | | | | | | The ddr_pd_cntl isn't defined in any reference manual and thus we wil remove especially since we set it to 0, which would most likely be its POR value. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add L2SRAM Register's macro definitionMingkai Hu2009-08-28-0/+5
| | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Adds GPIO registers to MPC85xx Memory Map.Poonam Aggrwal2009-07-02-0/+11
| | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add PORBMSR and PORDEVSR shift definesPeter Tyser2009-06-12-0/+2
| | | | | | | | | Add defines similar to those already used for the the 86xx architecture. This will ease sharing of PCI code between the 85xx and 86xx architectures. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl: Create common fsl_dma.h for 85xx and 86xx cpusPeter Tyser2009-06-12-73/+3
| | | | | | | | Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to reduce a large amount of code duplication Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add QE clk supportHaiying Wang2009-06-12-0/+2
| | | | | | Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: Timur Tabi <Timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: USB: Add supportVivek Mahajan2009-06-12-1/+4
| | | | | | | | The following patch adds 85xx-specific USB support and also revamps Copyright in immap_85xx.h Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
* eSPI: add the eSPI register supportMingkai Hu2009-04-04-0/+17
| | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
* MPC85xx: Add MPC8569 CPU supportHaiying Wang2009-03-30-1/+12
| | | | | | | | | There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage, then invalidate it after LBCR bit 13 is set. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Add eTSEC 1/2 IO override control (corrected)ksi@koi8.net2009-03-09-1/+1
| | | | | | This adds tsec12ioovcr to include/asm-ppc/immap_85xx.h (was reserved.) Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
* 85xx: Add eSDHC support for 8536 DSAndy Fleming2009-02-16-0/+3
| | | | Signed-off-by: Andy Fleming <afleming@freescale.com>
* mpc85xx: Add support for the P2020Srikanth Srinivasan2009-02-16-2/+23
| | | | | | | | | | | Added various p2020 processor specific details: * SVR for p2020, p2020E * immap updates for LAWs and DDR on p2020 * LAW defines related to p2020 Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add PORDEVSR_PCI1 definePeter Tyser2008-12-04-2/+1
| | | | | | | | | Add define used to determine if PCI1 interface is in PCI or PCIX mode. Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Make Freescale local bus registers available for both 83xx and 85xx.Haiying Wang2008-10-29-0/+1
| | | | | | | | | | | | | - Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it can be shared by both 83xx and 85xx - Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards files which use lbus83xx_t. - Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that 85xx can share them. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* 85xx: Update MPC85xx_PORDEVSR_IO_SEL maskPeter Tyser2008-10-27-1/+1
| | | | | | | | | The MPC8572 has a 4-bit wide PORDEVSR IO_SEL field. Other MPC85xx processors have a 3-bit wide IO_SEL field but have the most significant bit is wired to 0 so this change should not affect them. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* 85xx: properly document MPC85xx_PORDEVSR2_SEC_CFGTimur Tabi2008-10-21-0/+1
| | | | | | | | | Commit f7d190b1 corrected the value of MPC85xx_PORDEVSR2_SEC_CFG, but forgot to add a comment that the correct value disagrees with the 8544 reference manual. The changelog for that commit is also wrong, as it says "bit 28" when it should be "bit 24". Signed-off-by: Timur Tabi <timur@freescale.com>
* Merge 'next' branchWolfgang Denk2008-10-18-32/+32
|\ | | | | | | | | | | | | | | | | Conflicts: board/freescale/mpc8536ds/mpc8536ds.c include/configs/mgcoge.h Signed-off-by: Wolfgang Denk <wd@denx.de>
| * rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-32/+32
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | 85xx: Using proper I2C source clock divider for MPC8544Kumar Gala2008-10-17-1/+1
|/ | | | | | | | | | The MPC8544 RM incorrect shows the SEC_CFG bit in PORDEVSR2 as being bit 26, instead it should be bit 28. This caused in incorrect interpretation of the i2c_clk which is the same as the SEC clk on MPC8544. The SEC clk is controlled by cfg_sec_freq that is reported in PORDEVSR2. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Fix the incorrect DDR clk freq reporting on 8536DSJason Jin2008-10-07-0/+7
| | | | | | | | | On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), The display is still sync mode DDR freq. This patch try to fix this. The display DDR freq is now the actual freq in both sync and async mode. Signed-off-by: Jason Jin <Jason.jin@freescale.com>
* mpc85xx: Add support for the MPC8536Kumar Gala2008-08-27-0/+11
| | | | | | | | | | | The MPC8536 Adds SDHC and SATA controllers to the PQ3 family. We also have SERDES init code for the 8536. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com>
* Big white-space cleanup.Wolfgang Denk2008-05-21-30/+30
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* 85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docsKumar Gala2008-04-29-1/+1
| | | | | | | All the 85xx and 86xx UM describe the register as timing_cfg_3 not as ext_refrec. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx/86xx: Rename DDR init address and init extended address registerKumar Gala2008-04-29-2/+2
| | | | | | | Rename init_addr and init_ext_addr to match the docs between 85xx and 86xx. Both now use 'init_addr' and 'init_ext_addr'. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Fix calculation of I2C clock for some 85xx chipsTimur Tabi2008-04-18-1/+3
| | | | | | | | | | | Some 85xx chips use CCB as the base clock for the I2C. Some use CCB/2, and some use CCB/3. There is no pattern that can be used to determine which chips use which frequency, so the only way to determine is to look up the actual SOC designation and use the right value for that SOC. Update immap_85xx.h to include the GUTS PORDEVSR2 register. Signed-off-by: Timur Tabi <timur@freescale.com>
* Coding Style cleanup; update CHANGELOGWolfgang Denk2008-04-13-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* 85xx: Expand CCSR space with more DDR controller registers.James Yang2008-03-26-4/+21
| | | | | | Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Added support for multicore boot mechanismKumar Gala2008-03-26-0/+4
| | | | | | | | | Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Stop using immap_t on 85xxKumar Gala2007-12-11-24/+20
| | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_*_ADDR as the base of the registers instead of getting it via &immap. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Stop using immap_t for cpm offset on 85xxKumar Gala2007-12-11-1/+3
| | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers instead of getting it via &immap->im_cpm. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Stop using immap_t for guts offset on 85xxKumar Gala2007-12-11-2/+3
| | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers instead of getting it via &immap->im_gur. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Fix numerous bugs in the 8568 UEC supportAndy Fleming2007-08-16-1/+1
| | | | | | | | | | | | | | | | | | | | | Actually, fixed a large bug in the UEC for *all* platforms. How did this ever work? uec_init() did not follow the spec for eth_init(), and returned 0 on success. Switch it to return the link like tsec_init() (and 0 on error) The immap for the 8568 was defined based on MPC8568, rather than CONFIG_MPC8568 CONFIG_QE was off CONFIG_ETHPRIME was set to "Freescale GETH". Now is "FSL UEC0" Fixed a comment about the ranges for CONFIG_ETHPRIME if TSEC_ENET is enabled Signed-off-by: Andy Fleming <afleming@freescale.com>
* Add PCI support for MPC8568MDS boardHaiying Wang2007-08-14-0/+17
| | | | | | | This patch is against u-boot-mpc85xx.git of www.denx.com Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>
* 8544ds PCIE supportEd Swarthout2007-08-14-1/+36
| | | | | | | | | | | | | | | | | | PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address. Enable LBC and ECM errors and clear error registers. Add tftpflash env var to get uboot from tftp server and flash it. Add pci/pcie convenience env vars to display register space: "run pcie3regs" to see all pcie3 ccsr registers "run pcie3cfg" to see all cfg registers Whitespace cleanup and MPC8544DS.h Enable CONFIG_INTERRUPTS. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* From: eran liberty <eran.liberty@gmail.com>Andy Fleming2007-07-11-1/+3
| | | | | | | adds the reset register to 85xx immap Signed-off-by: Eran Liberty <eran.liberty@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Use generic I2C register block on 85xx and 86xx.Jon Loeliger2006-10-20-31/+5
| | | | | | | Replace private IMMAP I2C structures with generic reg block and allow 86xx to have multiple I2C device busses. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* * Added support for initializing second PCI bus on 85xx Patch by Andy ↵Matthew McClintock2006-08-09-2/+23
| | | | | | Fleming 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com>
* Fix style issues primarily in 85xx and 83xx boards.Jon Loeliger2005-08-01-31/+38
| | | | | | | | - C++ comments - Trailing white space - Indentation not by TAB - Excessive amount of empty lines - Trailing empty lines
* * Patch by Jon Loeliger, 2005-05-05Jon Loeliger2005-07-25-10/+25
| | | | | | | | Implemented support for MPC8548CDS board. Added DDR II support based on SPD values for MPC85xx boards. This roll-up patch also includes bugfies for the previously published patches: DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
* * Patch by Jon Loeliger, Kumar Gala 2005-02-08Jon Loeliger2005-07-23-3/+1
| | | | | | | | - Convert the CPM2 based functionality to use new CONFIG_CPM2 option rather than a myriad of CONFIG_MPC8560-like variants. Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560. Eliminates the CONFIG_MPC8560 option entirely. Distributes the new CONFIG_CPM2 option to each 8260 board.
* Fix timer handling on MPC85xx systemswdenk2005-05-13-0/+2
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* Patches by Jon Loeliger, 24 Aug 2004:wdenk2004-10-10-2/+6
| | | | | - Add support for the MPC8541 and MPC8555 CDS boards - Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR
generated by cgit v1.1 at 2024-08-28 17:40:12 +0000