| Commit message (Collapse) | Author | Age | Lines |
|---|
| |
|
|
|
|
|
| |
The masks for various bit defines of LSDMR are common and thus we can
define them in one place rather than replicating them in each config.h
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| |
|
|
|
|
|
|
|
|
|
|
| |
The eLBC only handles 32-bit physical address in systems with 36-bit
physical. The previos generation of LBC handled 34-bit physical
address in 36-bit systems. Added a new CONFIG option to convey
the difference between the LBC and eLBC.
Also added defines for XAM bits used in LBC for the extended 34-bit
support.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.
In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It
should be safe as the fifth bit was defined as reserved and set to 0.
Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
|
| |
|
|
|
|
|
|
|
|
|
| |
The BR_PHYS_ADDR macro is useful on all machines that have local bus
which is pretty much all 83xx/85xx/86xx chips.
Additionally most 85xx & 86xx will need it if they want to support
36-bit physical addresses.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
- Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it
can be shared by both 83xx and 85xx
- Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards
files which use lbus83xx_t.
- Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that
85xx can share them.
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
|
| |
|
|
| |
Signed-off-by: Stefan Roese <sr@denx.de>
|
| |
|
|
|
| |
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
83xx/85xx/86xx: add more MxMR local bus definitions
This patch adds more macro definitions for the UPM Machine Mode Registers
They are copied from "include/mpc82xx.h" to simplify the merge of all 8xxx
common local bus definitions into include/asm-ppc/fsl_lbc.h. They are
required for my forthcoming FSL NAND UPM driver re-write and the support
for the TQM8548 module.
This patch is based on the following two patches from Anton Vorontsov:
http://www.mail-archive.com/u-boot-users@lists.sourceforge.net/msg06511.html
http://www.mail-archive.com/u-boot-users@lists.sourceforge.net/msg06587.html
I leave coding style violation fixes, code beautification and name
corrections to somebody else ;-(.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
|
| |
|
|
|
|
|
| |
Merge mpc85xx.h's LBC defines to fsl_lbc.h. Also, adopt ACS names
from mpc85xx.h, so ACS_0b10 renamed to ACS_DIV4, ACS_0b11 to ACS_DIV2.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
|
|
|
This patch moves Freescale Localbus defines out of mpc83xx.h, so we could
use it on MPC85xx and MPC86xx processors.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
|
