summaryrefslogtreecommitdiff
path: root/include/asm-arm
Commit message (Collapse)AuthorAgeLines
* TI: Davinci: NAND Driver CleanupCyril Chemparathy2010-03-23-41/+36
| | | | | | | Modified to use IO accessor routines consistently. Eliminated volatile usage to keep checkpatch.pl happy. Signed-off-by: Cyril Chemparathy <cyril@ti.com>
* correct a syntax typo in at91_matrix.hAsen Dimov2010-03-21-1/+1
| | | | Signed-off-by: Asen Dimov <dimov@ronetix.at>
* mod change 755 => 644 for multiple filesThomas Weber2010-03-21-0/+0
| | | | | | | | I executed 'find . -name "*.[chS]" -perm 755 -exec chmod 644 {} \;' Signed-off-by: Thomas Weber <swirl@gmx.li> Add some more: neither Makefile nor config.mk need execute permissions. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Prepare v2010.03-rc1v2010.03-rc1Wolfgang Denk2010-03-12-1/+0
| | | | | | Coding style cleanup, update CHANGELOG. Signed-off-by: Wolfgang Denk <wd@denx.de>
* updates the at91 main_clock calculationJens Scharsig2010-03-07-0/+3
| | | | | | | * updates the conditional main_clock calculation (if AT91_MAIN_CLOCK defined) to c structure SoC access * add need register flags Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
* MX51: removed warnings for the mx51evkStefano Babic2010-03-07-23/+44
| | | | | | | | | | | The patch removes warnings at compile time and provides some cleanup code: - Removed comment on NAND (not yet supported) from lowlevel_init.S - Removed NFMS bit definition from imx-regs.h The bit is only related to MX.25/35 and can lead to confusion - Moved is_soc_rev() to soc specific code (removed from mx51evk.c) Signed-off-by: Stefano Babic <sbabic@denx.de>
* fec_mxc: add MX25 supportJohn Rigby2010-03-07-0/+1
| | | | | | | | Use RMII for MX25 Add code to init gasket that enables RMII Signed-off-by: John Rigby <jcrigby@gmail.com> CC: Ben Warren <biggerbadderben@gmail.com>
* fec_mxc: cleanup and factor out MX27 dependenciesJohn Rigby2010-03-07-0/+1
| | | | | | | | | | | | | general cleanup move clock init to cpu_eth_init in cpu/arm926ejs/mx27/generic.c make MX27 specific phy init conditional on CONFIG_MX27 replace call to imx_get_ahbclk with one to imx_get_fecclk and define imx_get_fecclk in include/asm-arm/arch-mx27/clock.h Signed-off-by: John Rigby <jcrigby@gmail.com> CC: Ben Warren <biggerbadderben@gmail.com> CC: Fred Fan <fanyefeng@gmail.com> CC: Tom <Tom.Rix@windriver.com>
* Add support for Freescale MX25 SOCJohn Rigby2010-03-07-0/+772
| | | | | | | | | ARM926EJS core with MX31 peripherals. Signed-off-by: John Rigby <jcrigby@gmail.com> Earlier Version Signed-off-by: Wolfgang Denk <wd@denx.de> CC: Fred Fan <fanyefeng@gmail.com> CC: Tom <Tom.Rix@windriver.com>
* mxc_serial replace platform specific clockJohn Rigby2010-03-07-0/+3
| | | | | | | | | | | | remove ifdef'd clock selection code from serial_mxc.c and replace with call to imx_get_uartclk Add definitions for imx_get_uartclk to imx31 and imx27 include files. This makes it easier to add new imx platforms. Signed-off-by: John Rigby <jcrigby@gmail.com>
* fsl_esdhc: add support for mx51 processorStefano Babic2010-03-07-0/+3
| | | | | | | | | The esdhc controller in the mx51 processor is quite the same as the one in some powerpc processors (MPC83xx, MPC85xx). This patches adapts the driver to support the arm mx51. Signed-off-by: Stefano Babic <sbabic@denx.de>
* ARM: add accessors functionsStefano Babic2010-03-07-0/+55
| | | | | | | | | | Some Freescale's processors of different architecture have the same peripheral (eSDHC controller in PowerPC and i.MX51). This patch adds accessors for the internal registers of the SOCs, as already implemented in the PowerPC architecture. Signed-off-by: Stefano Babic <sbabic@denx.de>
* MX51: Add pin and multiplexer definitions.Stefano Babic2010-03-07-0/+567
| | | | | | | | The patch add header files to support the pin multiplexer of the the Freescale i.MX51 processor. Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Fred Fan <fanyefeng@gmail.com>
* MX51: Add register definitionsStefano Babic2010-03-07-0/+524
| | | | | | | | The patch add header files to support the Freescale i.MX51 processor, setting definitions for internal registers. Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Fred Fan <fanyefeng@gmail.com>
* MX51: Add initial support for the Freescale MX51Stefano Babic2010-03-07-0/+31
| | | | | | | | The patch add initial support for the Freescale i.MX51 processor (family arm cortex_a8). Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Fred Fan <fanyefeng@gmail.com>
* ARM Update mach-typesTom Rix2010-03-07-7/+1021
| | | | | | | | | | Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit aea187c46f7d03ce985e55eb1398d0776a15b928 Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* ARM change name of defines for AT91 arm926ejsAchim Ehrlich2010-03-07-8/+8
| | | | | | | | | | Configuration defines should be preceeded with CONFIG_SYS_. Renamed some at91 specific defines to conform to this naming convention: AT91_CPU_NAME to CONFIG_SYS_AT91_CPU_NAME AT91_MAIN_CLOCK to CONFIG_SYS_AT91_MAIN_CLOCK Signed-off-by: Achim Ehrlich <aehrlich@taskit.de>
* da830evm: Add support for TI EMACNick Thompson2010-03-07-0/+1
| | | | | | | | | | | Adds support for ethernet networking on the da830evm platform. This platform uses an SoC EMAC interface and a 3 port ethernet switch as a PHY with an RMII interface. The PHY also has a i2c interface for configuring the switch functions. Signed-off-by: Nick Thompson <nick.thompson@ge.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* new at91_emac network driver (NET_MULTI api)Jens Scharsig2010-02-12-3/+1
| | | | | | | | | | | * add's at91_emac (AT91RM9200) network driver (NET_MULTI api) * enable driver with CONFIG_DRIVER_AT91EMAC * generic PHY initialization * modify AT91RM9200 boards to use NET_MULTI driver * the drivers has been tested with LXT971 Phy and DM9161 Phy at MII and RMII interface Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
* prepare joining at91rm9200 into at91Jens Scharsig2010-02-12-6/+365
| | | | | | | | | | | | * prepare joining at91 and at91rm9200 * add modified copy of soc files to cpu/arm920t/at91 to make possible to compile at91rm9200 boards in at91 tree instead of at91rm9200 * add header files with c structure defs for AT91 MC, ST and TC * the new cpu files are using at91 c structure soc access * please read README.soc-at91 for details Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
* add a new AT91 GPIO driverJens Scharsig2010-02-12-152/+30
| | | | | | | | | * add a real AT91 GPIO driver instead of header inline code * resolve the mixing of port and pins * change board config files to use new driver * add macros to gpio to realize backward compatibility Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
* add c structures for SoC accessJens Scharsig2010-02-12-3/+596
| | | | | | * add's c structures for SoC access to pheriperials head files Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
* Davinci: Add EMIF-A macros for setting chip select parametersNick Thompson2010-02-12-1/+17
| | | | | | | The patch adds EMIF-A macros for setting chip select parameters Signed-off-by: Nick Thompson <nick.thompson@ge.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* EP93xx: fix syscon_regs definitionAlessandro Rubini2010-02-12-1/+2
| | | | | | | | The structure was missing a reserved entry (not listed in the manual, actually), so the last registers had a wrong offset. This prevented all swlocked registers to be modified as swlock is last in the structure. Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
* ARM: Add support for EP93xx SoCsMatthias Kaehlcke2010-02-12-0/+595
| | | | | | | Add support for the Cirrus EP93xx platform Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net> Acked-by: Tom <Tom.Rix@windriver.com>
* OMAP3 Move declaration of gpmc_cfg.Tom Rix2010-02-12-0/+4
| | | | | | | | | Every omap3 board config file declared the global variable gpmc_cfg. This changes moves the declaration to a better location in the arch dependent header file cpu.h. Signed-off-by: Tom Rix <Tom.Rix@windriver.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* new at91_emac network driver (NET_MULTI api)Jens Scharsig2010-01-31-0/+145
| | | | | | | | | | | | * add's at91_emac (AT91RM9200) network driver (NET_MULTI api) * enable driver with CONFIG_DRIVER_AT91EMAC * generic PHY initialization * modify AT91RM9200 boards to use NET_MULTI driver * the drivers has been tested with LXT971 Phy and DM9161 Phy at MII and RMII interface Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* TI: DaVinci: Updating EMAC driver for DM365, DM646x and DA8XXNick Thompson2010-01-31-4/+55
| | | | | | | | | The EMAC IP on DM365, DM646x and DA830 is slightly different from that on DM644x. This change updates the DaVinci EMAC driver so that EMAC becomes operational on SOCs with EMAC v2. Signed-off-by: Nick Thompson <nick.thompson@ge.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* SPEAr : emi controller initialization for CFI driver supportVipin KUMAR2010-01-23-0/+54
| | | | | | | | | SPEAr310 and SPEAr320 SoCs contain an EMI controller to interface Paraller NOR flashes. This patch adds the support for this IP The standard CFI driver is used to interface with NOR flashes Signed-off-by: Vipin <vipin.kumar@st.com>
* SPEAr : Support for HW mac id read/write from i2c memVipin KUMAR2010-01-23-0/+8
| | | | | | | | | | | | | | | This patch adds the support to read and write mac id from i2c memory. For reading: if (env contains ethaddr) pick env ethaddr else pick ethaddr from i2c memory For writing: chip_config ethaddr XX:XX:XX:XX:XX:XX writes the mac id in i2c memory Signed-off-by: Vipin <vipin.kumar@st.com>
* SPEAr : Support added for SPEAr600 boardVipin KUMAR2010-01-23-0/+105
| | | | | | | | | | | | SPEAr600 SoC support contains basic spear600 support along with the usage of following drivers - serial driver(UART) - i2c driver - smi driver - nand driver(FSMC) - usbd driver Signed-off-by: Vipin <vipin.kumar@st.com>
* SPEAr : nand driver support for SPEAr SoCsVipin KUMAR2010-01-23-0/+57
| | | | | | | | SPEAr SoCs contain an FSMC controller which can be used to interface with a range of memories eg. NAND, SRAM, NOR. Currently, this driver supports interfacing FSMC with NAND memories Signed-off-by: Vipin <vipin.kumar@st.com>
* SPEAr : smi driver support for SPEAr SoCsVipin KUMAR2010-01-23-0/+115
| | | | | | | | SPEAr SoCs contain a serial memory interface controller. This controller is used to interface with spi based memories. This patch adds the driver for this IP. Signed-off-by: Vipin <vipin.kumar@st.com>
* SPEAr : i2c driver support added for SPEAr SoCsVipin KUMAR2010-01-23-0/+146
| | | | | | | SPEAr SoCs contain a synopsys i2c controller. This patch adds the driver for this IP. Signed-off-by: Vipin <vipin.kumar@st.com>
* SPEAr : Adding basic SPEAr architecture support.Vipin KUMAR2010-01-23-0/+319
| | | | | | | | | | SPEAr Architecture support added. It contains the support for following SPEAr blocks - Timer - System controller - Misc registers Signed-off-by: Vipin <vipin.kumar@st.com>
* ARM Update mach-typesTom Rix2010-01-23-0/+351
| | | | | | | | | | Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit 2045124ffd1a5e46d157349016a2c50f19c8c91d Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* Kirkwood: Upgated licencing for files imported from linux source to GPLv2 or ↵Prafulla Wadaskar2010-01-23-6/+34
| | | | | | | | | | | | | | later These are few files directly imported from Linux kernel source. Those are not modifyed at all ar per strategy. These files contains source with GPLv2 only whereas u-boot expects GPLv2 or latter These files are updated for the same from prior permission from original writes Acked-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* s5pc1xx: update cache routinesMinkyu Kang2010-01-23-0/+32
| | | | | | | | | | Because of v7_flush_dcache_all is moved to omap3/cache.S and s5pc110 needs cache routines, update s5pc1xx cache routines. l2_cache_enable and l2_caceh_disable are moved from cache.c to cache.S and invalidate_dcache is modified for SoC specific. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* samsung: fix DMC1_MEM_CFG for s3c64xxSeunghyeon Rhee2010-01-23-2/+2
| | | | | | | | | | | | | | | The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control for S3C6400. In the configuration of SMDK6400, however, two 16-bit mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit memory bus and there is no need to control CKE for each chip separately. AFAIK, CKE1 is not at all connected. Only CKE0 is used. Futhermore, it should be '0' always for S3C6410. When tested with a board which has a S3C6410 and the same memory configuration, a side effect is observed that u-boot command "reset" doesn't work leading to system hang. Leaving the bit clear is safe in most cases. Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* MX31: Add struct definition for clock control module in i.MX31.Magnus Lilja2010-01-19-0/+39
| | | | Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-01-12-14/+630
|\
| * ARM Update mach-typesTom Rix2010-01-06-10/+621
| | | | | | | | | | | | | | | | | | | | Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit c9f937e4a3f4ebf9924ec21d80632e5eb61d949c Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
| * Davinci: NAND enable ECC even when not in NAND boot modeNick Thompson2010-01-04-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Davinci: NAND enable ECC even when not in NAND boot mode On Davinci platforms, the default NAND device is enabled (for ECC) in low level boot code when NAND boot mode is used. If booting in another mode, NAND ECC is not enabled. The driver should make sure ECC is enabled regardless of boot mode if NAND is configured in U-Boot. Signed-off-by: Nick Thompson <nick.thompson@ge.com>
| * Davinci: Configurable NAND chip selectsNick Thompson2010-01-04-4/+10
| | | | | | | | | | | | | | | | | | | | Davinci: Configurable NAND chip selects Add a CONFIG_SYS_NAND_CS setting to all davinci configs and use it to setup the NAND controller in the davinci_nand mtd driver. Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
* | DA8xx: Add GPIO register definitionsAjay Kumar Gupta2010-01-09-0/+14
|/ | | | | | | | Added DA8xx GPIO base addresses in gpio_defs.h and pointers to different BANKs which can be used to program GPIOs. Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com> Signed-off-by: Swaminathan S <swami.iyer@ti.com>
* ARM Update mach-typesTom Rix2009-11-29-0/+481
| | | | | | | | | | Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit 3fcca9ac6cbce35b3e81e247d375534117d5f4cd Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* arm: A320: Add support for Faraday A320 evaluation boardPo-Yu Chuang2009-11-27-0/+436
| | | | | | | | This patch adds support for A320 evaluation board from Faraday. This board uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM. FA526 is an ARMv4 processor and uses the ARM920T source in this patch. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
* OMAP3: Fix SDRC initNishanth Menon2009-11-27-0/+1
| | | | | | | | | | Defaults are for Infineon DDR timings. Since none of the supported boards currently do XIP boot, these seem to be faulty. fix the values as per the calculations(ACTIMA,B), conf the sdrc power with pwdnen and wakeupproc bits Signed-off-by: Nishanth Menon <nm@ti.com>
* OMAP3:SDRC: introduce DDR typesNishanth Menon2009-11-27-19/+72
| | | | | | | | | | | | | | Micron DDR timings based on: http://www.sakoman.net/cgi-bin/gitweb.cgi?p=x-load-omap3.git;a=blob;f=include/asm/arch-omap3/mem.h;h=e6fbfe3947f5d0d85fea776e30821d4017316d86;hb=HEAD Introduce Micron DDR timings and provide CONFIG_OMAP3_INFINEON_DDR and CONFIG_OMAP3_MICRON_DDR config options to allow for platform files to setup their timings as per the type of DDR selected Reported-by: Steve Sakoman in http://www.nabble.com/forum/Permalink.jtp?root=25779518&post=25959734&page=y Signed-off-by: Nishanth Menon <nm@ti.com>
* OMAP3:SDRC: Cleanup references to SDPNishanth Menon2009-11-27-9/+2
| | | | | | Remove SDP referenced unused defines Signed-off-by: Nishanth Menon <nm@ti.com>
generated by cgit v1.1 at 2024-11-06 09:21:50 +0000