summaryrefslogtreecommitdiff
path: root/include/asm-arm
Commit message (Collapse)AuthorAgeLines
* OMAP3 Move declaration of gpmc_cfg.Tom Rix2010-01-31-0/+4
| | | | | | | | | Every omap3 board config file declared the global variable gpmc_cfg. This changes moves the declaration to a better location in the arch dependent header file cpu.h. Signed-off-by: Tom Rix <Tom.Rix@windriver.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* SPEAr : emi controller initialization for CFI driver supportVipin KUMAR2010-01-23-0/+54
| | | | | | | | | SPEAr310 and SPEAr320 SoCs contain an EMI controller to interface Paraller NOR flashes. This patch adds the support for this IP The standard CFI driver is used to interface with NOR flashes Signed-off-by: Vipin <vipin.kumar@st.com>
* SPEAr : Support for HW mac id read/write from i2c memVipin KUMAR2010-01-23-0/+8
| | | | | | | | | | | | | | | This patch adds the support to read and write mac id from i2c memory. For reading: if (env contains ethaddr) pick env ethaddr else pick ethaddr from i2c memory For writing: chip_config ethaddr XX:XX:XX:XX:XX:XX writes the mac id in i2c memory Signed-off-by: Vipin <vipin.kumar@st.com>
* SPEAr : Support added for SPEAr600 boardVipin KUMAR2010-01-23-0/+105
| | | | | | | | | | | | SPEAr600 SoC support contains basic spear600 support along with the usage of following drivers - serial driver(UART) - i2c driver - smi driver - nand driver(FSMC) - usbd driver Signed-off-by: Vipin <vipin.kumar@st.com>
* SPEAr : nand driver support for SPEAr SoCsVipin KUMAR2010-01-23-0/+57
| | | | | | | | SPEAr SoCs contain an FSMC controller which can be used to interface with a range of memories eg. NAND, SRAM, NOR. Currently, this driver supports interfacing FSMC with NAND memories Signed-off-by: Vipin <vipin.kumar@st.com>
* SPEAr : smi driver support for SPEAr SoCsVipin KUMAR2010-01-23-0/+115
| | | | | | | | SPEAr SoCs contain a serial memory interface controller. This controller is used to interface with spi based memories. This patch adds the driver for this IP. Signed-off-by: Vipin <vipin.kumar@st.com>
* SPEAr : i2c driver support added for SPEAr SoCsVipin KUMAR2010-01-23-0/+146
| | | | | | | SPEAr SoCs contain a synopsys i2c controller. This patch adds the driver for this IP. Signed-off-by: Vipin <vipin.kumar@st.com>
* SPEAr : Adding basic SPEAr architecture support.Vipin KUMAR2010-01-23-0/+319
| | | | | | | | | | SPEAr Architecture support added. It contains the support for following SPEAr blocks - Timer - System controller - Misc registers Signed-off-by: Vipin <vipin.kumar@st.com>
* ARM Update mach-typesTom Rix2010-01-23-0/+351
| | | | | | | | | | Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit 2045124ffd1a5e46d157349016a2c50f19c8c91d Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* Kirkwood: Upgated licencing for files imported from linux source to GPLv2 or ↵Prafulla Wadaskar2010-01-23-6/+34
| | | | | | | | | | | | | | later These are few files directly imported from Linux kernel source. Those are not modifyed at all ar per strategy. These files contains source with GPLv2 only whereas u-boot expects GPLv2 or latter These files are updated for the same from prior permission from original writes Acked-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* s5pc1xx: update cache routinesMinkyu Kang2010-01-23-0/+32
| | | | | | | | | | Because of v7_flush_dcache_all is moved to omap3/cache.S and s5pc110 needs cache routines, update s5pc1xx cache routines. l2_cache_enable and l2_caceh_disable are moved from cache.c to cache.S and invalidate_dcache is modified for SoC specific. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* samsung: fix DMC1_MEM_CFG for s3c64xxSeunghyeon Rhee2010-01-23-2/+2
| | | | | | | | | | | | | | | The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control for S3C6400. In the configuration of SMDK6400, however, two 16-bit mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit memory bus and there is no need to control CKE for each chip separately. AFAIK, CKE1 is not at all connected. Only CKE0 is used. Futhermore, it should be '0' always for S3C6410. When tested with a board which has a S3C6410 and the same memory configuration, a side effect is observed that u-boot command "reset" doesn't work leading to system hang. Leaving the bit clear is safe in most cases. Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* MX31: Add struct definition for clock control module in i.MX31.Magnus Lilja2010-01-19-0/+39
| | | | Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-01-12-14/+630
|\
| * ARM Update mach-typesTom Rix2010-01-06-10/+621
| | | | | | | | | | | | | | | | | | | | Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit c9f937e4a3f4ebf9924ec21d80632e5eb61d949c Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
| * Davinci: NAND enable ECC even when not in NAND boot modeNick Thompson2010-01-04-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Davinci: NAND enable ECC even when not in NAND boot mode On Davinci platforms, the default NAND device is enabled (for ECC) in low level boot code when NAND boot mode is used. If booting in another mode, NAND ECC is not enabled. The driver should make sure ECC is enabled regardless of boot mode if NAND is configured in U-Boot. Signed-off-by: Nick Thompson <nick.thompson@ge.com>
| * Davinci: Configurable NAND chip selectsNick Thompson2010-01-04-4/+10
| | | | | | | | | | | | | | | | | | | | Davinci: Configurable NAND chip selects Add a CONFIG_SYS_NAND_CS setting to all davinci configs and use it to setup the NAND controller in the davinci_nand mtd driver. Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
* | DA8xx: Add GPIO register definitionsAjay Kumar Gupta2010-01-09-0/+14
|/ | | | | | | | Added DA8xx GPIO base addresses in gpio_defs.h and pointers to different BANKs which can be used to program GPIOs. Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com> Signed-off-by: Swaminathan S <swami.iyer@ti.com>
* ARM Update mach-typesTom Rix2009-11-29-0/+481
| | | | | | | | | | Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit 3fcca9ac6cbce35b3e81e247d375534117d5f4cd Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* arm: A320: Add support for Faraday A320 evaluation boardPo-Yu Chuang2009-11-27-0/+436
| | | | | | | | This patch adds support for A320 evaluation board from Faraday. This board uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM. FA526 is an ARMv4 processor and uses the ARM920T source in this patch. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
* OMAP3: Fix SDRC initNishanth Menon2009-11-27-0/+1
| | | | | | | | | | Defaults are for Infineon DDR timings. Since none of the supported boards currently do XIP boot, these seem to be faulty. fix the values as per the calculations(ACTIMA,B), conf the sdrc power with pwdnen and wakeupproc bits Signed-off-by: Nishanth Menon <nm@ti.com>
* OMAP3:SDRC: introduce DDR typesNishanth Menon2009-11-27-19/+72
| | | | | | | | | | | | | | Micron DDR timings based on: http://www.sakoman.net/cgi-bin/gitweb.cgi?p=x-load-omap3.git;a=blob;f=include/asm/arch-omap3/mem.h;h=e6fbfe3947f5d0d85fea776e30821d4017316d86;hb=HEAD Introduce Micron DDR timings and provide CONFIG_OMAP3_INFINEON_DDR and CONFIG_OMAP3_MICRON_DDR config options to allow for platform files to setup their timings as per the type of DDR selected Reported-by: Steve Sakoman in http://www.nabble.com/forum/Permalink.jtp?root=25779518&post=25959734&page=y Signed-off-by: Nishanth Menon <nm@ti.com>
* OMAP3:SDRC: Cleanup references to SDPNishanth Menon2009-11-27-9/+2
| | | | | | Remove SDP referenced unused defines Signed-off-by: Nishanth Menon <nm@ti.com>
* Add TI DA8xx support: DA8xx includesNick Thompson2009-11-27-0/+242
| | | | | | | | | | | Provides initial support for TI OMAP-L1x/DA8xx SoC devices. See http://www.ti.com The DA8xx devices are similar to DaVinci devices but have a differing memory map and updated peripheral versions. Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
* Add a unified s3c24x0 header filekevin.morfitt@fearnside-systems.co.uk2009-11-27-0/+27
| | | | | | | | | | This patch adds a unified s3c24x0 cpu header file that selects the header file for the specific s3c24x0 cpu from the SOC and CPU configs defined in board config file. This removes the current chain of s3c24-type #ifdef's from the s3c24x0 code. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Clean-up of s3c24x0 header fileskevin.morfitt@fearnside-systems.co.uk2009-11-27-454/+483
| | | | | | | | | | | | | | Cleans up the s3c24x0 header files: s4c24x0.h: removes the use of 'volatile' from the S3C24X0_REG8, S3C24X0_REG16 and S3C24X0_REG32 register typedef's. Registers are always accessed using the IO accessor functions which cast the register address as 'volatile' anyway so it isn't required here. s3c2400.h and s3c2410.h: insert a blank line between the static inline functions Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
* s3c64xx: move s3c64xx header files to asm-arm/arch-s3c64xxMinkyu Kang2009-11-27-0/+985
| | | | | | | This patch moves the s3c64xx header files from include/ to include/asm-arm/arch-s3c64xx Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Move s3c24x0 header files to asm-arm/arch-s3c24x0/kevin.morfitt@fearnside-systems.co.uk2009-11-27-0/+938
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the s3c24x0 header files from include/ to include/asm-arm/arch-s3c24x0/. checkpatch.pl showed 2 errors and 3 warnings. The 2 errors were both due to a non-UTF8 character in David M?ller's name: ERROR: Invalid UTF-8, patch and commit message should be encoded in UTF-8 #489: FILE: include/asm-arm/arch-s3c24x0/s3c2410.h:3: + * David M?ller ELSOFT AG Switzerland. d.mueller@elsoft.ch As David's name correctly contains a non-UTF8 character I haven't fixed these errors. The 3 warnings were all because of the use of 'volatile' in s3c24x0.h: WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt #673: FILE: include/asm-arm/arch-s3c24x0/s3c24x0.h:35: +typedef volatile u8 S3C24X0_REG8; +typedef volatile u16 S3C24X0_REG16; +typedef volatile u32 S3C24X0_REG32; I'll fix these errors in another patch. Tested by running MAKEALL for ARM8 targets and ensuring there were no new errors or warnings. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARM Update mach-typesTom Rix2009-11-27-2/+1211
| | | | | | | | | | Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit 156171c71a0dc4bce12b4408bb1591f8fe32dc1a Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* ARM Update mach-types.hTom Rix2009-11-27-19/+263
| | | | | | | | From http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm Commit id 0996391139f43d032335b5360db11da62a2cbb39 Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* OMAP2/3: I2C: Add support for second and third busDirk Behme2009-11-16-31/+71
| | | | | | | | | | Add support to use second and third I2C bus, too. Bus 0 is still the default, but by calling i2c_set_bus_num(1/2) before doing I2C accesses, code can switch to bus 1 and 2, too. Don't forget to switch back afterwards, then. Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
* ARM: Use Linux version for unaligned access codeRemy Bohmer2009-11-07-1/+2
| | | | | | | | | | | | | | | | | | | | | The asm-arm/unaligned.h includes linux/unaligned/access_ok.h This file is unsafe to be used on ARM, since it does an unaligned memory accesses which fails on ARM. Lookin at Linux the basic difference seems to be the header "include/asm-arm/unaligned.h". The Linux version of "unaligned.h" does *not* include "access_ok.h" at all. It includes "le_byteshift.h" and "be_byteshift.h" instead. Signed-off-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Stefan Roese <sr@denx.de> -- include/asm-arm/unaligned.h | 3 - include/linux/unaligned/be_byteshift.h | 70 +++++++++++++++++++++++++++++++++ include/linux/unaligned/le_byteshift.h | 70 +++++++++++++++++++++++++++++++++ 3 files changed, 142 insertions(+), 1 deletion(-) create mode 100644 include/linux/unaligned/be_byteshift.h create mode 100644 include/linux/unaligned/le_byteshift.h
* Coding Style cleanup; update CHANGELOG, prepare -rc1v2009.11-rc1Wolfgang Denk2009-10-28-1/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* s5pc1xx: SMDKC100: fix compile warningsMinkyu Kang2009-10-24-77/+77
| | | | | | | fix the following compile warnings warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* TI DaVinci: Fix DM6467 EVM Compilation WarningSandeep Paulraj2009-10-24-0/+2
| | | | | | | | | | | Due to new TI boards being added to U-Boot, the hardware.h is getting very messy. The warning being fixed is due to the EMIF addresses being redefined. The long term solution(after 2009.11) to this is to have SOC specific header files. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* TI OMAP3: make gpmc_config as constNishanth Menon2009-10-24-1/+1
| | | | | | | | | | | gpmc_config should not be a variant as it is board specific hence make it a const parameter Fixes issues identified by Dirk: - build issue for zoom2 - warnings for all other OMAP3 platforms using nand/onenand etc Signed-off-by: Nishanth Menon <nm@ti.com>
* OMAP3: export enable_gpmc_cs_config to board filesNishanth Menon2009-10-18-0/+2
| | | | | | | | | Export enable_gpmc_cs_config into common header to prevent warning: warning: implicit declaration of function 'enable_gpmc_cs_config' Signed-off-by: Nishanth Menon <nm@ti.com>
* s5pc1xx: support Samsung s5pc1xx SoCMinkyu Kang2009-10-13-0/+475
| | | | | | | | This patch adds support for the Samsung s5pc100 and s5pc110 SoCs. The s5pc1xx SoC is an ARM Cortex A8 processor. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
* TI: DaVinci: GPIO header file and definitionsSandeep Paulraj2009-10-13-0/+53
| | | | | | | | | | | Some DaVinci SOC's use GPIOs to enable EMAC and DM9000. This patch adds some definitions for GPIO registers and also adds structures for GPIO. A separate header file is being added so that in future we can have a DaVinci GPIO driver similer to OMAP. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Acked-by: Tom Rix <Tom.Rix@windriver.com>
* TI: DaVinci DM646x: Update flag used to represent DM646x SOC'sSandeep Paulraj2009-10-13-3/+3
| | | | | | | | | | | In the DaVinci specific code, we use both CONFIG_SOC_DM646X and CONFIG_SOC_DM646x to represent DM646x specific code. This patch changes occurrences of CONFIG_SOC_DM646x to CONFIG_SOC_DM646X. This is because for DM644x series of SOCs we use the flag CONFIG_SOC_DM644X. We want some uniformity. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Acked-by: Tom Rix <Tom.Rix@windriver.com>
* OMAP3 MMC: Fix warning dereferencing type-punned pointerDirk Behme2009-10-13-0/+7
| | | | | | | | | Fix warning Dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Dirk Behme <dirk.behme@googlemail.com> CC: Steve Sakoman <sakoman@gmail.com> Acked-by: Tom Rix <Tom.Rix@windriver.com>
* TI DaVinci: DM646x: Initial Support for DM646x SOCSandeep Paulraj2009-10-13-0/+11
| | | | | | | | | DM646x is an SOC from TI which has both an ARM and a DSP. There are multiple variants of the SOC mainly dealing with different core speeds. This patch adds the initial framework for the DM646x SOC. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* OMAP3 Move cache routine to cache.STom Rix2009-10-13-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v7_flush_dcache_all, because it depends on omap ROM code is not generic. Rename the function to 'invalidate_dcache' and move it to the omap cpu directory. Collect the other omap cache routines l2_cache_enable and l2_cache_disable with invalide_dcache into cache.S. This means removing the old cache.c file that contained l2_cache_enable and l2_cache_disable. The conversion from cache.c to cache.S was done most through disassembling the uboot binary. The only significant change was to change the comparision for the return of get_cpu_rev from cmp r0, #0 beq earlier_than_label Which was lost information to cmp r0, #CPU_3XX_ES20 blt earlier_than_label The paths through the enable routine were verified by adding an infinite loop and seeing the hang. Then removing the infinite loop and seeing it continue. The disable routine is similar enough that it was not tested with this method. Run tested by cold booting from nand on beagle and zoom1. Compile tested on MAKEALL arm. Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* arm/microblaze/nios/nios2/sh: Remove relocation fixupsPeter Tyser2009-10-03-1/+3
| | | | | | | | | | | | | | | | | These architectures don't need relocation fixups, so reduce their codesize a bit by defining CONFIG_RELOC_FIXUP_WORKS. Also remove the reloc_off field from their global data structures as it is no longer needed. Note that the location of the standalone application jump table pointer in the global data structure is affected by this change, breaking execution of standalone applications compiled for previous versions of U-Boot. We will therefore increment XF_VERSION in the next commit, which also touches this area. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Correct ffs/fls regression for PowerPC etcSimon Kagstrom2009-09-17-8/+0
| | | | | | | | | | | | | | | Commits 02f99901ed1c9d828e3ea117f94ce2264bf8389e 52d61227b66d4099b39c8309ab37cb67ee09a405 introduced a regression where platform-specific ffs/fls implementations were defined away. This patch corrects that by using PLATFORM_xxx instead of the name itself. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de>
* arm: Define test_and_set_bit and test_and_clear bit for ARMSimon Kagstrom2009-09-15-3/+25
| | | | | | Needed for (e.g.) ubifs support to work. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
* arm: Make arm bitops endianness-independentSimon Kagstrom2009-09-15-28/+19
| | | | | | | | Bring over the bitop implementations from the Linux include/asm-generic/bitops/non-atomic.h to provide endianness-independence. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
* Move __set/clear_bit from ubifs.h to bitops.hSimon Kagstrom2009-09-15-0/+2
| | | | | | | | | __set_bit and __clear_bit are defined in ubifs.h as well as in asm/include/bitops.h for some architectures. This patch moves the generic implementation to include/linux/bitops.h and uses that unless it's defined by the architecture. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-09-07-30/+14
|\
| * arm: Kirkwood: add SYSRSTn Duration Counter SupportPrafulla Wadaskar2009-09-01-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This feature can be used to trigger special command "sysrstcmd" using reset key long press event and environment variable "sysrstdelay" is set (useful for reset to factory or manufacturing mode execution) Kirkwood SoC implements a hardware-based SYSRSTn duration counter. When SYSRSTn is asserted low, a SYSRSTn duration counter is running. The counter value is stored in the SYSRSTn Length Counter Register The counter is based on the 25-MHz reference clock (40ns) It is a 29-bit counter, yielding a maximum counting duration of 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value, it remains at this value until counter reset is triggered by setting bit 31 of KW_REG_SYSRST_CNT Implementation: Upon long reset assertion (> ${sysrstdelay} in secs) sysrstcmd will be executed if pre-defined in environment variables. This feature will be disabled if "sysrstdelay" variable is unset. for-ex. setenv sysrst_cmd "echo starting factory reset; nand erase 0xa0000 0x20000; echo finish ed sysrst command;" will erase particular nand sector if triggered by this event Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
generated by cgit v1.1 at 2024-12-25 08:20:29 +0000