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* Correct ffs/fls regression for PowerPC etcSimon Kagstrom2009-09-17-8/+0
| | | | | | | | | | | | | | | Commits 02f99901ed1c9d828e3ea117f94ce2264bf8389e 52d61227b66d4099b39c8309ab37cb67ee09a405 introduced a regression where platform-specific ffs/fls implementations were defined away. This patch corrects that by using PLATFORM_xxx instead of the name itself. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de>
* arm: Define test_and_set_bit and test_and_clear bit for ARMSimon Kagstrom2009-09-15-3/+25
| | | | | | Needed for (e.g.) ubifs support to work. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
* arm: Make arm bitops endianness-independentSimon Kagstrom2009-09-15-28/+19
| | | | | | | | Bring over the bitop implementations from the Linux include/asm-generic/bitops/non-atomic.h to provide endianness-independence. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
* Move __set/clear_bit from ubifs.h to bitops.hSimon Kagstrom2009-09-15-0/+2
| | | | | | | | | __set_bit and __clear_bit are defined in ubifs.h as well as in asm/include/bitops.h for some architectures. This patch moves the generic implementation to include/linux/bitops.h and uses that unless it's defined by the architecture. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-09-07-30/+14
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| * arm: Kirkwood: add SYSRSTn Duration Counter SupportPrafulla Wadaskar2009-09-01-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This feature can be used to trigger special command "sysrstcmd" using reset key long press event and environment variable "sysrstdelay" is set (useful for reset to factory or manufacturing mode execution) Kirkwood SoC implements a hardware-based SYSRSTn duration counter. When SYSRSTn is asserted low, a SYSRSTn duration counter is running. The counter value is stored in the SYSRSTn Length Counter Register The counter is based on the 25-MHz reference clock (40ns) It is a 29-bit counter, yielding a maximum counting duration of 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value, it remains at this value until counter reset is triggered by setting bit 31 of KW_REG_SYSRST_CNT Implementation: Upon long reset assertion (> ${sysrstdelay} in secs) sysrstcmd will be executed if pre-defined in environment variables. This feature will be disabled if "sysrstdelay" variable is unset. for-ex. setenv sysrst_cmd "echo starting factory reset; nand erase 0xa0000 0x20000; echo finish ed sysrst command;" will erase particular nand sector if triggered by this event Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
| * imx27lite: add support for imx27lite board from LogicPDIlya Yanok2009-09-01-0/+12
| | | | | | | | | | | | | | | | | | This patch adds support for i.MX27-LITEKIT development board from LogicPD. This board uses i.MX27 SoC and has 2MB NOR flash, 64MB NAND flash, FEC ethernet controller integrated into i.MX27. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Acked-by: Wolfgang Denk <wd@denx.de>
| * Remove duplicate set_crSimon Kagstrom2009-09-01-30/+0
| | | | | | | | | | | | | | | | | | | | Remove duplicate set_cr set_cr is defined in both asm-arm/proc-armv/system.h and include/asm-arm/system.h. This patch removes it (and some duplicate defines) from the former. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
* | ARM: Update mach-typesWolfgang Denk2009-09-04-12/+2056
|/ | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* NAND: DaVinci: V2 Adding 4 BIT ECC supportSandeep Paulraj2009-08-26-0/+10
| | | | | | | | This patch adds 4 BIT ECC support in the DaVinci NAND driver. Tested on both the DM355 and DM365. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* omap3: Fixed a problem with hweccBen Goska2009-08-18-2/+2
| | | | | | | | In commit 187af954cf7958c24efcf0fd62289bbdb4f1f24e there was a typo that offset all the ecc registers by 4 bytes, fixed that. Signed-off-by: Ben Goska <goskab@onid.oregonstate.edu> Acked-by: Dirk Behme <dirk.behme@googlemail.com>
* Monahans: avoid floating point calculationsWolfgang Denk2009-08-17-1/+1
| | | | | | | | | | | Current code for the Monahans CPU defined OSCR_CLK_FREQ as 3.250 (MHz) which caused floating point operations to be used. This resulted in unresolved references to some FP related libgcc functions when using U-Boot's private libgcc functions. Change the code to use fixed point math only. Signed-off-by: Wolfgang Denk <wd@denx.de>
* OMAP3: Fix missing GPMC_CONFIG_CS0_BASEDirk Behme2009-08-10-0/+1
| | | | | | | | | | Applying two indepenent OMAP3 patches resulted in missing GPMC_CONFIG_CS0_BASE. Patch "omap3: embedd gpmc_cs into gpmc config struct" removes GPMC_CONFIG_CS0_BASE, independent patch "omap3: bug fix for NOR boot support" introduces it's usage. Re-introduce GPMC_CONFIG_CS0_BASE. Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
* mxc-mmc: sdhc host driver for MX2 and MX3 proccessorIlya Yanok2009-08-09-0/+25
| | | | | | | | | | This is a port of Linux driver for SDHC host controller hardware found on Freescale's MX2 and MX3 processors. Uses new generic MMC framework (CONFIG_GENERIC_MMC) and it looks like there are some problems with a framework (at least on LE cpus). Some of these problems are addressed in the following patches. Signed-off-by: Ilya Yanok <yanok@emcraft.com>
* kirkwood/gpio.h: remove duplicate definitionAlessandro Rubini2009-08-09-2/+0
| | | | Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
* omap3: use only fixed-size types inside ctrl_structsDirk Behme2009-08-08-194/+218
| | | | | | | | | | replace variable types in ctrl_structs for omap3 by those with fixed size (u8, u16, u32). Additional ifndef-protection is needed by examples which do not compile when including asm/types.h Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
* omap3: remove typedefs for configuration structsDirk Behme2009-08-08-31/+31
| | | | | Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
* omap3: embedd gpmc_cs into gpmc config structMatthias Ludwig2009-08-07-23/+18
| | | | | | | | | Embedd chip select configuration into struct for gpmc config instead of having it completely separated as suggested by Wolfgang Denk on http://lists.denx.de/pipermail/u-boot/2009-May/052247.html Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de>
* pxa: Fix typo in GCDR(x)David Hunter2009-08-01-1/+1
| | | | | | Fix a typo in the GCDR(x) macro. It's a good thing no one was using it. Signed-off-by: David Hunter <hunterd42@gmail.com>
* arm nomadik: add gpio supportAlessandro Rubini2009-07-29-0/+42
| | | | | | Signed-off-by: Alessandro Rubini <rubini@unipv.it> Acked-by: Andrea Gallo <andrea.gallo@stericsson.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* OMAP3 Remove twl4030 definesTom Rix2009-07-29-35/+0
| | | | | | | | | These defines have been subplanted by the equivelent defines in include/twl4030.h Signed-off-by: Tom Rix <Tom.Rix@windriver.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Heiko Schocher <hs@denx.de>
* OMAP I2C Fix the sampling clock.Tom Rix2009-07-28-7/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This problem is seen on Zoom1 and Zoom2 in the startup and when i2c probe is used Before : In: serial Out: serial Err: serial timed out in wait_for_bb: I2C_STAT=1000 timed out in wait_for_bb: I2C_STAT=1000 timed out in wait_for_bb: I2C_STAT=1000 timed out in wait_for_pin: I2C_STAT=1000 I2C read: I/O error timed out in wait_for_bb: I2C_STAT=1000 timed out in wait_for_bb: I2C_STAT=1000 Die ID #327c00020000000004013ddd05026013 Hit any key to stop autoboot: 0 OMAP3 Zoom1# i2c probe Valid chip addresses:timed out in wait_for_bb: I2C_STAT=1000 02 03 04 05 06 07 08 09 0A 0B 0C 0D <snip> After : In: serial Out: serial Err: serial Die ID #327c00020000000004013ddd05026013 Hit any key to stop autoboot: 0 OMAP3 Zoom1# i2c probe Valid chip addresses: 48 49 4A 4B The addresses are for the twl4030. The prescalar that converts the function clock to the sampling clock is hardcoded to 0. The reference manual recommends 7 if the function clock is 96MHz. Instead of just changing the hardcoded values, the prescalar is calculated from the value I2C_IP_CLK. The i2c #defines are in kHz. The speed passed into the i2c init routine is in Hz. To be consistent, change the defines to be in Hz. The timing calculations are based on what is done in the linux 2.6.30 kernel in drivers/i2c/buses/i2c_omap.c as apposed to what is done in TRM. The major variables in the timing caculations are specified as #defines that can be overriden as required. The variables and their defaults are I2C_IP_CLK SYSTEM_CLOCK_96 I2C_INTERNAL_SAMPLING_CLK 19200000 I2C_FASTSPEED_SCLL_TRIM 6 I2C_FASTSPEED_SCLH_TRIM 6 I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM I2C_HIGHSPEED_PHASE_TWO_SCLH I2C_FASTSPEED_SCLH_TRIM This was runtime verified on Zoom1, Zoom2, Beagle and Overo. The 400kHz and 3.4M cases were verifed on test Zoom1, Zoom2, Beagle and Overo configurations. Testing for omap2 will be done in a second step as Nishanth and Jean-Christophe commented. Signed-off-by: Tom Rix <Tom.Rix@windriver.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Heiko Schocher <hs@denx.de>
* arm, kirkwood: added kw_gpio_set_valid() in gpio.hHeiko Schocher2009-07-23-0/+2
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* Kirkwood: add Marvell Kirkwood gpio driverDieter Kiermaier2009-07-23-0/+51
| | | | | | Signed-off-by: Dieter Kiermaier <dk-arm-linux@gmx.de> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Tested-by: Heiko Schocher <hs@denx.de>
* arm, kirkwood: added KW_TWSI_BASE in kirkwood.hHeiko Schocher2009-07-23-0/+1
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* Add unaligned.h for armSimon Kagstrom2009-07-19-0/+18
| | | | | | | | | This patch adds unaligned.h for ARM (needed to build with LZO compression). The file is taken from the linux kernel, but includes u-boot headers instead. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net> Acked-by: Stefan Roese <sr@denx.de>
* Merge branch 'asm-generic' of git://git.denx.de/u-boot-microblazeWolfgang Denk2009-07-16-138/+1
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| * asm-generic: Consolidate errno.h to asm-generic/errno.hMichal Simek2009-07-09-138/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch use blackfin errno.h implementation which correspond Linux kernel one. MIPS implemetation is different that's why I keep it. I removed ppc_error_no.h from Marvell boards which was the same too. I have got ack from ppc40x, blackfin, arm, coldfire and avr custodians. Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Michal Simek <monstr@monstr.eu>
* | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-07-13-8/+316
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| * | at91: Introduction of at91sam9g10 SOC.Sedji Gaouaou2009-07-12-1/+1
| | | | | | | | | | | | | | | | | | | | | AT91sam9g10 is an ARM 926ej-s SOC. It is an evolution of the at91sam9261 with a faster clock speed: 266/133MHz. Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
| * | at91: Introduction of at91sam9g45 SOC.Sedji Gaouaou2009-07-12-0/+307
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AT91sam9g45 series is an ARM 926ej-s SOC family clocked at 400/133MHz. It embeds USB high speed host and device, LCD, DDR2 RAM, and a full set of peripherals. The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES. On the board you can find 2 USART, USB high speed, a 480*272 LG lcd, ethernet, gpio/joystick/buttons. Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
| * | pxa: fix CKEN_B register bitsDaniel Mack2009-07-12-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | The current defition for CKEN_B register bits is nonsense. Adding 32 to the shifted value is equal to '| (1 << 5)', and this bit is marked 'reserved' in the PXA docs. Signed-off-by: Daniel Mack <daniel@caiaq.de>
| * | pxa: add clock for system bus 2 arbiterDaniel Mack2009-07-12-0/+1
| | | | | | | | | | | | | | | | | | | | | This clock is needed for systems using the USB2 device unit or the 2d graphics accelerator. Signed-off-by: Daniel Mack <daniel@caiaq.de>
| * | arm: Kirkwood: bugfix: UART1 bar correctionPrafulla Wadaskar2009-07-12-1/+1
| |/ | | | | | | Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* | davinci_nand chipselect/init cleanupDavid Brownell2009-07-07-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update chipselect handling in davinci_nand.c so that it can handle 2 GByte chips the same way Linux does: as one device, even though it has two halves with independent chip selects. For such chips the "nand info" command reports: Device 0: 2x nand0, sector size 128 KiB Switch to use the default chipselect function unless the board really needs its own. The logic for the Sonata board moves out of the driver into board-specific code. (Which doesn't affect current build breakage if its NAND support is enabled...) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | NAND DaVinci: Update to ALE/CLE Mask valuesSandeep Paulraj2009-07-07-0/+5
| | | | | | | | | | | | | | | | | | | | | | All DaVinci SOC's use a CLE mask of 0x10 and an ALE mask of 0x8 except the DM646x. This was decided by the design team driving the design. This patch updates the CLE and ALE values for DM646x. Updated patches for DM646x will be sent shortly. This applies to u-boot-nand-flash git Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | ARM DaVinci: Changing ALE Mask ValueSandeep Paulraj2009-07-07-1/+1
| | | | | | | | | | | | | | | | The ALE mask used by DaVinci SOCs is wrong. The patch changes the mask value from '0xa' to '0x8'. This is the mask we use for all TI releases. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | davinci_nand: cleanup II (CONFIG_SYS_DAVINCI_BROKEN_ECC)David Brownell2009-07-07-69/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove CONFIG_SYS_DAVINCI_BROKEN_ECC option. It's not just nasty; it's also unused by any current boards, and doesn't even match the main U-Boot distributions from TI (which use soft ECC, or 4-bit ECC on newer chips that support it). DaVinci GIT kernels since 2.6.24, and mainline Linux since 2.6.30, match non-BROKEN code paths for 1-bit HW ECC. The BROKEN code paths do seem to partially match what MontaVista/TI kernels (4.0/2.6.10, and 5.0/2.6.18) do ... but only for small pages. Large page support is really broken (and it's unclear just what software it was trying to match!), and the ECC layout was making three more bytes available for use by filesystem (or whatever) code. Since this option itself seems broken, remove it. Add a comment about the MV/TI compat issue, and the most straightforward way to address it (should someone really need to solve it). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | davinci_nand: cleanup I (minor)David Brownell2009-07-07-54/+0
|/ | | | | | | | | | | | | | | | | | | | | | | | Minor cleanup for DaVinci NAND code: - Use I/O addresses from nand_chip; CONFIG_SYS_NAND_BASE won't be defined when there are multiple chipselect lines in use (as with common 2 GByte chips). - Cleanup handling of EMIF control registers * Only need one pointer pointing to them * Remove incorrect and unused struct supersetting them - Use the standard waitfunc; we don't need a custom version - Partial legacy cleanup: * Don't initialize every board like it's a DM6446 EVM * #ifdef a bit more code for BROKEN_ECC Sanity checked with small page NAND on dm355 and dm6446 EVMs; and large page on dm355 EVM (packaged as two devices, not one). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Coding style cleanup; update CHANGELOGWolfgang Denk2009-07-07-2/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* MX31: Add NAND SPL boot support to i.MX31 PDK board.Magnus Lilja2009-07-06-0/+54
| | | | Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
* arm: Kirkwood: arch specific updated for ehci-Kirkwood driver supportPrafulla Wadaskar2009-07-06-0/+9
| | | | | | This patch abstracts Kirkwood arch specific changes to support ehci-kirkwood driver Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* arm nomadik: use 1000 as HZ value and rewrite timer codeAlessandro Rubini2009-07-06-0/+66
| | | | | | | | | | | | This sets CONFIG_SYS_HZ to 1000 as required, and completely rewrites timer code, which is now both correct and much smaller. Unused functions like udelay_masked() have been removed as no driver uses them, even the ones that are not currently active for this board. mtu.h is copied literally from the kernel sources. Signed-off-by: Alessandro Rubini <rubini@unipv.it> Acked-by: Andrea Gallo <andrea.gallo@stericsson.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* ARM: Update mach-typesJean-Christophe PLAGNIOL-VILLARD2009-07-06-39/+1612
| | | | | | update against linux v2.6.30 Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* at91: Add CAN init functionDaniel Gorsulowski2009-07-06-0/+1
| | | | | | | | | To enable CAN init, CONFIG_CAN has to be defined in the board config file and at91_can_hw_init() has to be called in the board specific code. CAN is available on AT91SAM9263 and AT91CAP9 SoC. Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
* arm: Kirkwood: Correct header defineSimon Kagstrom2009-07-06-1/+1
| | | | | | Correct define typo (. -> ,) Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
* MX31: Add basic support for Freescale i.MX31 PDK board.Magnus Lilja2009-07-06-0/+2
| | | | | | | | | | | Add support for Freescale's i.MX31 PDK board (a.k.a. 3 stack board). This patch assumes that some other program performs the actual NAND boot. Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com> Acked-by: Fabio Estevam <fabioestevam@yahoo.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* move L2 cache enable/disable function to cache.c in the omap3 SoC directoryKim, Heung Jun2009-07-06-0/+4
| | | | | | Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com> CC: Dirk Behme <dirk.behme@googlemail.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* arm: Kirkwood: Basic SOCs supportPrafulla Wadaskar2009-07-06-0/+605
| | | | | | | | | | | | | | | | | | | | | | Kirkwood family controllers are highly integrated SOCs based on Feroceon-88FR131/Sheeva-88SV131/arm926ejs cpu core. SOC versions supported:- 1) 88F6281-A0 define CONFIG_KW88F6281_A0 2) 88F6192-A0 define CONFIG_KW88F6192_A0 Other supported features:- 1) get_random_hex() fucntion 2) PCI Express port initialization 3) NS16550 driver support Contributors: Yotam Admon <yotam@marvell.com> Michael Blostein <michaelbl@marvell.com Reviewed-by: Ronen Shitrit <rshitrit@marvell.com> Acked-by: Stefan Rose <sr@denx.de> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* arm: generic cache.h for ARM architecturesPrafulla Wadaskar2009-07-06-0/+41
| | | | | | | This patch is required for Kirkwood SoC support may be used by other ARM architectures Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
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