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* ENGR00179437-2 u-boot: mx6q: iomux: code clean upimx-android-r13.2.1imx_v2009.08Jason Liu2012-04-13-16/+1
| | | | | | | Remove the dead definiton which never used by iomux-v3 framework And move the SION bit definiton to arch-mx6/iomux-v3.h for sharing Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00179437-1: u-boot: iomux: NO_PAD_I/NO_PAD_MUX not set corretlyJason Liu2012-04-13-4/+4
| | | | | | | | NO_PAD_I/NO_PAD_MUX not defined correctly, which will cause build error. And According to iomux-v3.h, the NO_PAD_I/NO_PAD_MUX should be 0 for the pins which does not have PAD/MUX config. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00139223-1 [MX6Q] Secure Boot, enable HAB on ARM2 platform (Stage 1)Eric Sun2012-04-01-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first stage of High Assurance Boot (HAB) is the authentication of U-boot. A CST tool is used to generate the CSF data, which include public key, certificate and instruction of authentication process. Then it is attached to the original u-boot.bin The IVT should be modified to contain a pointer to the CSF data. The original u-boot.bin is with size between 0x27000 to 0x28000. For convinence, we first extend the u-boot.bin to 0x2F000 (with fill 0xFF). Then concatenate it with the CSF data. The combined image is again extend to a fixed length (0x31000), which is used as the IVT size parameter. The new memory layout is as the following. U-Boot Image +-------------+ | Blank | |-------------| 0x400 | IVT |-----------------------+ |-------------| | | | | | | | | | | |Remaining UB | | CSF pointer | | | | | | | | | |-------------| | | | | | Fill Data | | | | | |-------------| 0x2F000 <-------------+ | | | CSF Data | | | |-------------| | | | Fill Data | | | +-------------+ 0x31000 HAB APIs are ROM implemented, the entry table is located in a fixed location in the ROM. We export them so that during the HAB we can have some information about the secure boot process. For convinience some wrapper API is implemented based on the HAB APIs. - get_hab_status : used to dump information of authentication result - authenticate_image : used by u-boot to authenticate uImage For security hardware to function, CAAM related clock (CG0[4~6]) must be open. They are default closed in the original U-boot. "hab_caam_clock_enable" and "hab_caam_clock_disable" are created to open and close these clock gates. The generation of CSF data is not in the scope of this patch. CST tool will be used for this purpose. The procedure will be introduced in another document. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00177909: mx6q/mx6dl SabreSD: SPI-NOR flash not probed as expectedJason Liu2012-03-26-9/+9
| | | | | | | | | | | | SPI NOR flash(m25p32-vmw6tg) not probed and function as expected, this due to the lack of iomux pad config and incorrect CS line. This patch fix the above issue and also fix the mfg config file (For the code readable, I intent to omit the following checkpatch warning: in the iomux/mx6_pins.h WARNING: line over 80 characters) Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00177244 - imx6 : Use common fsl_sys_rev to check board reversionFugang Duan2012-03-20-0/+10
| | | | | | | | | - Use fsl_sys_rev to check Sebreauto board reversion. - Add macro define for expedient print the board and chip name. mx6_chip_name() mx6_board_rev_name() Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176834-1 - [imx6] : add fsl_system_rev to check chip and board.Fugang Duan2012-03-20-1/+20
| | | | | | | | | | | | | | | - Add fsl_system_rev to distinguish chip ID and board reversion. - Add some api: mx6_chip_is_dq() mx6_chip_is_dl() mx6_chip_is_solo() mx6_chip_is_sololite() mx6_board_is_reva() mx6_board_is_revb() mx6_board_is_revc() Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176347-5 mx6solo sabreauto: set system_revLily Zhang2012-03-13-1/+4
| | | | | | | | | | | | | | | | | Add set_system_rev function. The layout of system_rev is: bit 0-7: Chip Revision ID. Read from Anatop register bit 8-11: Board Revision ID. Read from fuse OCOTP_GP1[15:8] 1: RevA Board 0: RevB board, Unknown board bit 12-19: Chip Silicon ID. Read from Anatop register 0x63: i.MX 6Dual/Quad 0x61: i.MX 6Solo/DualLite board_is_rev(system_rev,BOARD_REV_1) can be used to distinguish RevB board. board_is_rev(system_rev,BOARD_REV_2) is for RevA board. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00139213: Add read and change voltage support for mx6Terry Lv2012-02-16-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dd read and change voltage support for mx6. For help, pls type "help regul" Detail command info: regul list - List all regulators' name regul show all - Display all regulators' voltage regul show core - Show core voltage in mV regul show periph - Show peripheral voltage in mV regul show <regulator name> - Show regulator's voltage in mV regul set core <voltage value> - Set core voltage in mV regul set periph <voltage value> - Set periph voltage in mV regul set <regulator name> <voltage value> - Set regulator's voltage in mV Example: MX6Q ARM2 U-Boot > regul list Name Voltage vddpu vddcore vddsoc vdd2p5 vdd1p1 vdd3p0 MX6Q ARM2 U-Boot > regul show all Name Voltage vddpu 1100000 vddcore 1100000 vddsoc 1200000 vdd2p5 2400000 vdd1p1 1100000 vdd3p0 3000000 MX6Q ARM2 U-Boot > regul show periph Name Voltage periph: 1100000 MX6Q ARM2 U-Boot > regul show core Name Voltage core: 1100000 MX6Q ARM2 U-Boot > regul set core 1100000 Set voltage succeed! Name Voltage core: 1100000 Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00173966-1: i.mx6dl: add the iomux head fileJason Liu2012-02-07-0/+3717
| | | | | | | | | | | Checkpatch will throw some warnings in iomux-mx6dl.h file as: WARNING: line over 80 characters But for the readable, I intend not to fix these warnings, and linux/uboot upstream also has so many such kind of cases Acked-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00172343 Add suport for i.MX 6Q Sabre Smart DeviceNancy Chen2012-01-24-0/+13
| | | | | | | | Add suport for i.MX 6Quad SABRE Smart Device. Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com> Signed-off-by: Tony Lin <tony.lin@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com>
* ENGR00170299-1 Android: add support fastboot functionZhang Jiejing2011-12-15-0/+9
| | | | | | add support for otg in MX6Q uboot to enable fastboot function. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00169919 MX6Q ARM2 U-Boot : Support Pop CPU BoardEric Sun2011-12-13-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for MX6Q ARM2 LPDDR2 POP CPU Board. Change thing include - TEXT_BASE - RAM address and size - Initialization DCD - MMU related code Use mx6q_arm2_lpddr2pop_config as the build config. After u-boot.bin is generated, set the board to serial download mode, use sb loader to run the bootloader. There is one line in the original DDR initialization script setmem /32 0x00B00000 = 0x1 however this address can not be accessed by DCD. A try to add it later in "dram_init" block the boot up. Waiting for IC team to give an explanation on it. Hold temperorily The MMU Change can be concluded as the following - Cacheable and Uncacheable SDRAM allocation changes to Phys Virtual Size Property ---------- ---------- -------- ---------- 0x10000000 0x10000000 256M cacheable 0x80000000 0x20000000 16M uncacheable 0x81000000 0x21000000 240M cacheable - TEXT_BASE change to 0x10800000, which reserves 8MB of memory at the start of SDRAM. This address makes sure that the text section of U-boot have the same Physical and Virtural address, thus the PC don't need to change when MMU is enabled. Also the text section is all allocated in cacheable memory, which may increase excecution performance. - Since this SDRAM allocation avoid overlap in physical memory between cacheable and uncacheable memory, the implementation of __ioremap can be ignored Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00163513 MX6Q-UBOOT : Add download_mode cmdEric Sun2011-11-30-0/+3
| | | | | | | | | | | | | Add "download_mode" command to U-Boot. It will force a system reset and let boot running in "boot from serial rom" mode, which can be used by manufacturing tool. The command will triggle a write to SRC_GPR9 and SRC_GPR10, then triggle a watchdog reset. GPR9 and GPR10 can maintain their value during the reset, the value in it make ROM to start in "boot from serial rom" mode. After that GPR9 and GPR10 are written by their original value for normal boot. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00162938 MX5: Add download_mode command in uboot to enter MFG download mode.Zhang Jiejing2011-11-23-0/+3
| | | | | | | | | | | | Add download_mode command in uboot to enter MFG dowload mode , you can try download mode command in uboot and enter download mode. it first set srtc register, then before enter linux, it will clear these register to prevent the up comming watchdog reset will enter mfgtool mode. only add mx53 now. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00162709 Add Support for MX6Q Sabre AutoEric Sun2011-11-21-1/+1
| | | | | | | 1. Change RAM size from 2GB to 1GB 2. Default boot from MMC Dev 2 Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00162437 uboot mc34708 pcba : add spi support on mc34708Robin Gong2011-11-17-0/+33
| | | | | | | | Rev C of pcba will connect mc34708 by spi default, so uboot should support it: 1. add spi support in mx53_pcba 2. move pmic voltage config from board_init to board_late_init 3. support both I2C and SPI on mc34708 in one image Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00161254 MX6Q: Add NAND support in UbootAllen Xu2011-11-03-0/+5
| | | | | | | | Add iomux and clock setting in Uboot code to support NAND, due to the conflict between NAND and SD, NAND function is not enabled in default configuration. Signed-off-by: Allen Xu <allen.xu@freescale.com>
* ENGR00161277 Add fuse access capability for MX6 Sabre-liteMahesh Mahadevan2011-11-02-1/+1
| | | | | | Add support to read and program fuses in the MX6 Sabre-lite Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00139215 iMX61 Uboot support blow fuseRyan QIAN2011-11-02-0/+367
| | | | | | | | 1. add force option to blow operation 2. add blown value check 3. add simple validation for zeros returned by 'simple_strtoul' call Signed-off-by: Ryan QIAN <b32804@freescale.com>
* ENGR00161133: Add spi-nor support for mx6qTerry Lv2011-11-01-1/+1
| | | | | | Add spi-nor support for mx6q. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00161004 MX6Q Uboot Rename sabreauto to arm2 boardAnish Trivedi2011-10-28-0/+13
| | | | | | | | | Sabreauto is an inaccurate name for the Armadillo2 board that this code is actually meant for. So, replaced "sabreauto" in folder names, file names, configs, and code with "arm2". Created a new machine id for ARM2 board. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00139221 USDHC Add SDXC UHS-I supportAnish Trivedi2011-10-27-2/+2
| | | | | | | Modified MMC library for UHS-I command sequence Added support to USDHC driver for UHS-I Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00160399 Added support for the MX6Q Sabre-lite boardMahesh Mahadevan2011-10-25-47/+26
| | | | | | Includes support for uSDHC read, write, FEC, SPI-NOR etc. Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00160507 Update the IOMUX implementation for MX6Mahesh Mahadevan2011-10-20-6/+5
| | | | | | | The MX6 code incorrectly uses the Hysteresis bit to decide NO_PAD_CTRL operation Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00156930: Update MX35 DDR2 scriptsTerry Lv2011-10-18-6/+11
| | | | | | | | | | Update MX35 DDR2 scripts for that when enabling 256MB, the CSD1 is not stable. 1. Add CSD1 configs to support 256M RAM. 2. Add mx35 TO2 256M RAM configs. 3. Update DDR init code in lowlevel_init.S for external boot. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00158184 mx53 smd: use highest value for unknown board revision valueWayne Zou2011-09-26-0/+1
| | | | | | mx53 smd: use highest value for unknown board revision value Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00139254: Enable MX6Q Uboot Splash ScreenSandor Yu2011-09-02-31/+48
| | | | | | | | | | | | | | Only support LVDS0 splash screen. Enable splash process: 1.define CONFIG_SPLASH_SCREEN in mx6q_sabreauto.h 2.Config U-boot with followed command:() setenv splashimage '0x30000000' #Set splash position as Center setenv splashpos 'm,m' #Set LVDS via LVDS bridge 0 setenv lvds_num 0 Signed-off-by: Sandor Yu <r01008@freescale.com>
* ENGR00155283: Set dpgdck0_2_en to 0 when freq is lower than 300MHzTerry Lv2011-09-01-5/+8
| | | | | | | | 1. Set dpgdck0_2_en to 0 when required freq is lower than 300Mhz. 2. When dpgdck0_2_en is 0, the formula to calculate output freq will be changed to 2 * freq * []. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00153526 mx53 pcba: add pcba board revB support in ubootXinyu Chen2011-07-27-3/+6
| | | | | | | | | | | | | | | Add new machine type for pcba. Add UART, I2C, SD/MMC, PMIC, DDR initial support. Add MFG tool support. Add support for MC34708 on revB pcba board. Update VDDGP setting on MC34708 PMIC for revB board. Close unused clock, for fastboot it will enable usb_phy usb_oh3 clock by itself, still need to verify this work or not when revB bootup. Signed-off-by: Wayne Zou <b36644@freescale.com> Signed-off-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00139206 MX6 USDHC eMMC 4.4 supportAnish Trivedi2011-07-05-2/+2
| | | | | | | | | | | New bit definitions in USDHC. Added is_usdhc variable to fsl_esdhc_cfg to distinguish between ESDHC and USDHC. Enabled DDR mode support in USDHC. Created a config to customize target delay for DDR mode. Modified USDHC pad settings to make DDR mode work for all emmcs at 50 MHz. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00139198: iMX61 uBoot add ENET supportZeng Zhaoming2011-06-27-63/+67
| | | | | | | | | | | | | | | | Add ENET and AR8031 PHY support to uboot. To make it works on sabreauto, need do following changes: 1. rework phy to output 125M clock from CLK_25M signal, and the 125M clock input to SoC as reference clock to generate RGMII_TXC clock. 2. Enable TXC delay in PHY debug register. 3. set ENET working in RMII mode. 4. set ENET working at 1000M or 100M/10M. 5. set ENET TX fifo to maximum to avoid underrun error. 6. force AR8031 PHY working at 100M Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
* ENGR00144424 MX6: enable uboot for ARM2(SABREAUTO) CPU boardAnson Huang2011-06-24-0/+7650
| | | | | | | | | | | | | Use 528M DDR script Disable L2 cache because rom enable L2 cache when use plug-in Fix usdhc pad settings Remove mac address hardcode Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00142995 MX50: Enable uSDHC instead of eSDHC for SDR modeAnish Trivedi2011-05-10-0/+1
| | | | | | | | | | | | | | | | | | On SD3 on MX50, there is an option to choose eSDHC or uSDHC controller. By default eSDHC is selected. However, eSDHC shows some borderline timing in SDR mode at 50 MHz, whereas uSDHC shows borderline timing in DDR mode at 50 MHz. Therefore, add a compile time option to uboot for MX50 to select uSDHC in SDR mode or eSDHC in DDR mode on SD3 port. By default the compile time option, CONFIG_MX50_ENABLE_USDHC_SDR, is commented out in the include/configs/mx50_<board>.h file to select eSDHC with DDR mode enabled. Uncomment the define to select uSDHC with only SDR mode enabled. Also increased max frequency supported by ESDHC to 52 MHz instead of 50 MHz. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00141556: Fix copyright issueTerry Lv2011-04-08-2/+2
| | | | | | | | | | | We're following the following rules: 1. FSL copyright should be added for freescale added and modified files. 2. FSL copyright should go after existing copyrights. 3. For Duplicate FSL copyright, Our copyright will go after that also. 4. FSL copyright should not include personal names as part. 5. For only FSL copyright, "All rights reserved" is not mattered. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00141000 MX50_RDP: add android recovery support.Zhang Jiejing2011-03-23-1/+2
| | | | | | Add android recovery related config and code. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00140824 Android: Enable fastboot support for mx50 rdpSammy He2011-03-21-1/+6
| | | | | | Enable fastboot support for mx50 rdp. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00140825: Add mx53 to2.1 chip id recognitionTerry2011-03-20-0/+2
| | | | | | Add mx53 to2.1 chip id recognition. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00139747: Read fuse to distinguish between mx53 revA and revBTerry Lv2011-03-02-0/+7
| | | | | | | | | Read fuse to distinguish between mx53 revA and revB. Now SoC efuse is used for board id. Thus we now check fuse value for board rev and id. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00137894-2 MX53: Add ipu base addr and ipu clockLiu Ying2011-01-13-0/+5
| | | | | | This patch adds ipu base address and ipu clock. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137894-1 Add imx pwm driver supportLiu Ying2011-01-13-0/+37
| | | | | | | This patch adds imx pwm driver support as a misc device. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137604: Change PLL4 to 455MHz for mx53Terry Lv2011-01-07-1/+5
| | | | | | | Required by display to set ldb. We need to set PLL4 to 455MHz. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00137497-2 MX53: Add LOCO board supportLily Zhang2010-12-30-2/+2
| | | | | | | | | | | Add MX53 LOCO board support The following functions are tested in the board: - Micro SD boot - MMC/SD read/write. - clk command - fuse command Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137497-1 Import new mach-type header fileLily Zhang2010-12-30-33/+2387
| | | | | | | | Import new mach-type header file for MX53 LOCO board Signed-off-by: Lily Zhang <r58066@freescale.com> Acked-by: Lily Zhang <r58066@freescale.com>
* ENGR00136075 MX53: Add SMD board supportLily Zhang2010-12-30-0/+20
| | | | | | | | | | | | | | | | | | | | | | | Add MX53 SMD support: - Use DDR3 script for SMD board from Mike Kjar: "Rita_init_LCB_CMOS.inc" - Set the default CPU core frequency as 1GHZ. The following functions are tested on SMD board: - SD/MMC boot, read, write via SDHC1 - eMMC4.4 boot, read, write via SDHC3. - SATA boot, read, write. To support SATA boot via internal clock, please ensure the fuse "SATA_ALT_CLK_REF" was blown. - FEC - UART - clk command - iim command Signed-off-by: Liu Ying <b17645@freescale.com> Signed-off-by: Jason Chen <b02280@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137372 MX53: Switch back to use DCD and update DDR scriptsLily Zhang2010-12-28-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. This patch is used to switch back to use DCD for flash header instead of plug-in. This change request is due to the following reasons: 1) U-boot community doesn't accept current plug-in solution when upstreaming. 2) Plug-in isn't supported by MX53 ROM serial download mode. No effective workaround is found now. To use the same code base to support normal U-Boot and MFG tool better, adopt DCD solution firstly. 3) Current MX53 DDR scripts don't exceed the length limitation of DCD. For MX53 TO2.0 EVK/ARM2 board, raise DDR frequency to 400MHZ after VCC and VDDA voltages are raised as 1.3V. Since ARM2 CPU2 board share the same script with EVK, delete ARM2 CPU2 config files. ARM2 CPU2 board can share the same bootloader with EVK. 2. Update MX53 DDR2 scripts for TO1.0/TO2.0 EVK/ARD/ARM2 boards The script "MX53_TO2_DDR2_EVK_ARD.inc" is located under http://compass.freescale.net/livelink/livelink? func=ll&objId=221058910&objAction=browse&viewType=1 This script is published by ATX and FIL team on Dec 16th, 2010 3. Update MX53 ARM2 CPU3 DDR3 script "MX53_TO2_DDR3_CPU3.inc" under the same compass folder Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00134220-1 NAND: fix up the chip select handlingJason Liu2010-12-07-2/+10
| | | | | | | | When the NAND has multi-cs, the chip select other than cs0 is not handled correctly which will lead to NAND not function as expected Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00133437 MX50 Uboot support for TO 1.1.1 precodeAnish Trivedi2010-12-01-0/+3
| | | | | | | Precoding: Update DDR configuration plugin to check SI Rev and change ROM addresses as needed. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00134098-2 MX53: Add fastboot support for android.Sammy He2010-11-26-1/+4
| | | | | | Add fastboot support for mx53 EVK android. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00133551-1 Add freescale usb udc support for i.mx51 platform.Sammy He2010-11-18-0/+4
| | | | | | | Add imx_udc for usb gadget on i.mx51 platform. Signed-off-by: Hu Hui <b29976@freescale.com> Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00132909 MX53 Uboot: Support for TO2Anish Trivedi2010-11-15-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support new DDR script entitled "Rita_TO2_init_DDR2_CPU2_CMOS_TEST_CAL_v1.inc" for DDR2 boards including MX53 EVK, ARD, and ARM2 CPU2. These new settings did not apply to TO1. Therefore, changed the DCD for these boards to a plugin so that TO1 and TO2 can both be supported using conditional execution of new DDR settings. During bootup on TO2, DDR frequency is required to be below 400 MHz. Therefore, BOOT_CFG2[4] must be set to enable DDR at 333 MHz in ROM on all boards. Uboot determines silicon version and for TO2 boosts the VCC and VDDA voltages to 1.3V, after which the DDR frequency is also increased to 400 MHz. This requirement meant that uboot does not calibrate PLL2 anymore until the voltage is increased. Removed the calibration from lowlevel_init.S and from all mx53 include/configs files. Also required that during config_periph_clk(), only CBCMR register is touched to set source PLL. Other changes to CBCDR were removed. Switching to PLL2 bypass clk during reprogram was also removed. All these changes are required to increase DDR frequency to 400 MHz. DDR2 CPU2 board with TO1 requires the following hw cfgs: JP3 populated, and J8 set to 2-3. For DDR2 CPU2 board with TO2, both these jumpers should be depopulated. ARM2 CPU3 (with DDR3) DDR configurations were not changed. TO1 and TO2 can run well using existing DDR3 script. However, DCD was converted to plugin to align with other boards. Signed-off-by: Anish Trivedi <anish@freescale.com>
generated by cgit v1.1 at 2024-09-27 17:23:31 +0000