| Commit message (Collapse) | Author | Age | Lines |
|---|
| |
|
|
|
|
|
|
|
| |
SPEAr310 and SPEAr320 SoCs contain an EMI controller to interface
Paraller NOR flashes. This patch adds the support for this IP
The standard CFI driver is used to interface with NOR flashes
Signed-off-by: Vipin <vipin.kumar@st.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This patch adds the support to read and write mac id from i2c
memory.
For reading:
if (env contains ethaddr)
pick env ethaddr
else
pick ethaddr from i2c memory
For writing:
chip_config ethaddr XX:XX:XX:XX:XX:XX writes the mac id
in i2c memory
Signed-off-by: Vipin <vipin.kumar@st.com>
|
| |
|
|
|
|
|
|
|
|
|
|
| |
SPEAr600 SoC support contains basic spear600 support along with the
usage of following drivers
- serial driver(UART)
- i2c driver
- smi driver
- nand driver(FSMC)
- usbd driver
Signed-off-by: Vipin <vipin.kumar@st.com>
|
| |
|
|
|
|
|
|
| |
SPEAr SoCs contain an FSMC controller which can be used to interface
with a range of memories eg. NAND, SRAM, NOR.
Currently, this driver supports interfacing FSMC with NAND memories
Signed-off-by: Vipin <vipin.kumar@st.com>
|
| |
|
|
|
|
|
|
| |
SPEAr SoCs contain a serial memory interface controller. This
controller is used to interface with spi based memories.
This patch adds the driver for this IP.
Signed-off-by: Vipin <vipin.kumar@st.com>
|
| |
|
|
|
|
|
| |
SPEAr SoCs contain a synopsys i2c controller.
This patch adds the driver for this IP.
Signed-off-by: Vipin <vipin.kumar@st.com>
|
|
|
SPEAr Architecture support added. It contains the support for
following SPEAr blocks
- Timer
- System controller
- Misc registers
Signed-off-by: Vipin <vipin.kumar@st.com>
|
