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* ENGR00255977 mx6sl: correct the information for chip and board revisionRobby Cai2013-04-16-1/+2
| | | | | | | | | | mx6sl chip revision is from different-offset register in anatop module comparing to other mx6 series. This patch fixes it and also uses board 'RevC' to indicate the latest board revision if this information can not be obtained from fuse. Signed-off-by: Robby Cai <R63905@freescale.com> (cherry picked from commit 39e36b5e5a7cfe53fd6e286d9fe9024b365f1a29)
* ENGR00242042 MX6DQ/DL: fix boot fail issue on mx6dl boardsjb4.2.1_1.0.0-alphaLin Fuzhen2013-01-28-1/+2
| | | | | | | | MX6DQ and MX6DL share the common board file, but only MX6DQ has built-in SATA, for the SATA PDDQ should be enabled default, so it needs to add code to distinguish different chip ID. Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
* ENGR00235817 mx6: use SNVS LPGPR register to store boot mode value.Zhang Jiejing2012-12-11-0/+2
| | | | | | | | | | | | | | | | | After using POR reset, the content in SRC will be reset. See RM: 63.5.1.2.3 IPP_RESET_B(POR) Because POR reset will reset most of register in IC, so use SNVS_LP General Purpose Register (LPGPR) to store the boot mode value. Below copy from SNVS_BlockGuide.pdf: The SNVS_LP General Purpose Register provides a 32 bit read write register, which can be used by any application for retaining 32 bit data during a power-down mode This Patch will use [7,8] bits of this register. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00230967 Enable recovery mode by keys when bootLiGang2012-10-30-5/+8
| | | | | | | | | | 1. Add matrix key support 2. Add recovery mode support by pressing power key and volume down key when boot SW10 on MX6SL-EVK board configed as volume down key. SW1 on MX6SL-EVK board configed as power key Signed-off-by: LiGang <b41990@freescale.com>
* ENGR00221503-2 imx6: add cpu serial number support.Zhang Jiejing2012-08-31-0/+10
| | | | | | | | add cpu serial number tag, kernel will read this number and put it in /proc/cpuinfo, as 'Serial' part it can be used as a UUID source in software. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00211117 - U-Boot: Add EPDC splash screen for MX 6DL/S platformsDanny Nold2012-05-30-6/+7
| | | | | | | | | - EPDC Splash support for MX6DL/S Sabre SD - EPDC Splash support for MX6DL/S ARM2 - Currently, splash screen consists of a simple black border around a white screen. Done this way to save in memory footprint. Signed-off-by: Danny Nold <dannynold@freescale.com>
* ENGR00211038 Fix the PAD_LVE implementationMahesh Mahadevan2012-05-30-1/+1
| | | | | | Fix the PAD_LVE implementation used on MX6SL. Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@freescale.com>
* ENGR00209899-1 mx6x: add generic gpio interface.Zhang Jiejing2012-05-21-0/+103
| | | | | | | | | | | | | | | | | | | | | | Add generic gpio interface in uboot. Seems more and more gpio operation invoke in uboot, without RAW register operation, we should use generic gpio interface. you should define the CONFIG_MXC_GPIO use generic gpio interface: gpio_request, gpio_direction_output, gpio_direction_input, gpio_set_value, gpio_get_value, etc. Test on MX6Q, MX6DL. Other MX6X should also define this config. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00210014 i.mx6 : i.mx6sl : add PAD_CTL_LVE support for pad configurationEric Sun2012-05-18-5/+6
| | | | | | | | | | | Original pad configuration don't provide enough bitfield width to hold all necessary information. For MX6Sololite, a "PAD_CTL_LVE" is needed to be configed for many pins. iomux_v3_cfg_t is re-orgnized to address this issue. PAD_CTRL is extended by 1 bit to hold the "PAD_CTL_LVE". Which is mapped to proper bit location when configure the PAD config register. Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00181337-1 i.mx6 : add initial support for i.mx6slEric Sun2012-05-02-11/+3056
| | | | | | | | | | | | | | This patch is to add the initial support for Freescale i.mx6sl chip. i.mx6sl is the SoloLite verison of Freescale i.mx6 family. The patch does: - memory layout support, - iomux support, - clock support, Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Ryan QIAN <b32804@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00180623 fastboot: add fastboot in MX6Q_SABERSD boardsZhang Jiejing2012-04-24-0/+3
| | | | | | | | add fastboot function back in MX6Q_SABERSD board. the MX6DL_SABERSD have usb init related issue which will keep RESET, but left as later developement. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00179437-2 u-boot: mx6q: iomux: code clean upimx-android-r13.2.1imx_v2009.08Jason Liu2012-04-13-16/+1
| | | | | | | Remove the dead definiton which never used by iomux-v3 framework And move the SION bit definiton to arch-mx6/iomux-v3.h for sharing Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00179437-1: u-boot: iomux: NO_PAD_I/NO_PAD_MUX not set corretlyJason Liu2012-04-13-4/+4
| | | | | | | | NO_PAD_I/NO_PAD_MUX not defined correctly, which will cause build error. And According to iomux-v3.h, the NO_PAD_I/NO_PAD_MUX should be 0 for the pins which does not have PAD/MUX config. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00139223-1 [MX6Q] Secure Boot, enable HAB on ARM2 platform (Stage 1)Eric Sun2012-04-01-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first stage of High Assurance Boot (HAB) is the authentication of U-boot. A CST tool is used to generate the CSF data, which include public key, certificate and instruction of authentication process. Then it is attached to the original u-boot.bin The IVT should be modified to contain a pointer to the CSF data. The original u-boot.bin is with size between 0x27000 to 0x28000. For convinence, we first extend the u-boot.bin to 0x2F000 (with fill 0xFF). Then concatenate it with the CSF data. The combined image is again extend to a fixed length (0x31000), which is used as the IVT size parameter. The new memory layout is as the following. U-Boot Image +-------------+ | Blank | |-------------| 0x400 | IVT |-----------------------+ |-------------| | | | | | | | | | | |Remaining UB | | CSF pointer | | | | | | | | | |-------------| | | | | | Fill Data | | | | | |-------------| 0x2F000 <-------------+ | | | CSF Data | | | |-------------| | | | Fill Data | | | +-------------+ 0x31000 HAB APIs are ROM implemented, the entry table is located in a fixed location in the ROM. We export them so that during the HAB we can have some information about the secure boot process. For convinience some wrapper API is implemented based on the HAB APIs. - get_hab_status : used to dump information of authentication result - authenticate_image : used by u-boot to authenticate uImage For security hardware to function, CAAM related clock (CG0[4~6]) must be open. They are default closed in the original U-boot. "hab_caam_clock_enable" and "hab_caam_clock_disable" are created to open and close these clock gates. The generation of CSF data is not in the scope of this patch. CST tool will be used for this purpose. The procedure will be introduced in another document. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00177909: mx6q/mx6dl SabreSD: SPI-NOR flash not probed as expectedJason Liu2012-03-26-9/+9
| | | | | | | | | | | | SPI NOR flash(m25p32-vmw6tg) not probed and function as expected, this due to the lack of iomux pad config and incorrect CS line. This patch fix the above issue and also fix the mfg config file (For the code readable, I intent to omit the following checkpatch warning: in the iomux/mx6_pins.h WARNING: line over 80 characters) Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00177244 - imx6 : Use common fsl_sys_rev to check board reversionFugang Duan2012-03-20-0/+10
| | | | | | | | | - Use fsl_sys_rev to check Sebreauto board reversion. - Add macro define for expedient print the board and chip name. mx6_chip_name() mx6_board_rev_name() Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176834-1 - [imx6] : add fsl_system_rev to check chip and board.Fugang Duan2012-03-20-1/+20
| | | | | | | | | | | | | | | - Add fsl_system_rev to distinguish chip ID and board reversion. - Add some api: mx6_chip_is_dq() mx6_chip_is_dl() mx6_chip_is_solo() mx6_chip_is_sololite() mx6_board_is_reva() mx6_board_is_revb() mx6_board_is_revc() Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176347-5 mx6solo sabreauto: set system_revLily Zhang2012-03-13-1/+4
| | | | | | | | | | | | | | | | | Add set_system_rev function. The layout of system_rev is: bit 0-7: Chip Revision ID. Read from Anatop register bit 8-11: Board Revision ID. Read from fuse OCOTP_GP1[15:8] 1: RevA Board 0: RevB board, Unknown board bit 12-19: Chip Silicon ID. Read from Anatop register 0x63: i.MX 6Dual/Quad 0x61: i.MX 6Solo/DualLite board_is_rev(system_rev,BOARD_REV_1) can be used to distinguish RevB board. board_is_rev(system_rev,BOARD_REV_2) is for RevA board. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00173966-1: i.mx6dl: add the iomux head fileJason Liu2012-02-07-0/+3717
| | | | | | | | | | | Checkpatch will throw some warnings in iomux-mx6dl.h file as: WARNING: line over 80 characters But for the readable, I intend not to fix these warnings, and linux/uboot upstream also has so many such kind of cases Acked-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00170299-1 Android: add support fastboot functionZhang Jiejing2011-12-15-0/+9
| | | | | | add support for otg in MX6Q uboot to enable fastboot function. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00169919 MX6Q ARM2 U-Boot : Support Pop CPU BoardEric Sun2011-12-13-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for MX6Q ARM2 LPDDR2 POP CPU Board. Change thing include - TEXT_BASE - RAM address and size - Initialization DCD - MMU related code Use mx6q_arm2_lpddr2pop_config as the build config. After u-boot.bin is generated, set the board to serial download mode, use sb loader to run the bootloader. There is one line in the original DDR initialization script setmem /32 0x00B00000 = 0x1 however this address can not be accessed by DCD. A try to add it later in "dram_init" block the boot up. Waiting for IC team to give an explanation on it. Hold temperorily The MMU Change can be concluded as the following - Cacheable and Uncacheable SDRAM allocation changes to Phys Virtual Size Property ---------- ---------- -------- ---------- 0x10000000 0x10000000 256M cacheable 0x80000000 0x20000000 16M uncacheable 0x81000000 0x21000000 240M cacheable - TEXT_BASE change to 0x10800000, which reserves 8MB of memory at the start of SDRAM. This address makes sure that the text section of U-boot have the same Physical and Virtural address, thus the PC don't need to change when MMU is enabled. Also the text section is all allocated in cacheable memory, which may increase excecution performance. - Since this SDRAM allocation avoid overlap in physical memory between cacheable and uncacheable memory, the implementation of __ioremap can be ignored Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00163513 MX6Q-UBOOT : Add download_mode cmdEric Sun2011-11-30-0/+3
| | | | | | | | | | | | | Add "download_mode" command to U-Boot. It will force a system reset and let boot running in "boot from serial rom" mode, which can be used by manufacturing tool. The command will triggle a write to SRC_GPR9 and SRC_GPR10, then triggle a watchdog reset. GPR9 and GPR10 can maintain their value during the reset, the value in it make ROM to start in "boot from serial rom" mode. After that GPR9 and GPR10 are written by their original value for normal boot. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00161254 MX6Q: Add NAND support in UbootAllen Xu2011-11-03-0/+5
| | | | | | | | Add iomux and clock setting in Uboot code to support NAND, due to the conflict between NAND and SD, NAND function is not enabled in default configuration. Signed-off-by: Allen Xu <allen.xu@freescale.com>
* ENGR00161277 Add fuse access capability for MX6 Sabre-liteMahesh Mahadevan2011-11-02-1/+1
| | | | | | Add support to read and program fuses in the MX6 Sabre-lite Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00139215 iMX61 Uboot support blow fuseRyan QIAN2011-11-02-0/+367
| | | | | | | | 1. add force option to blow operation 2. add blown value check 3. add simple validation for zeros returned by 'simple_strtoul' call Signed-off-by: Ryan QIAN <b32804@freescale.com>
* ENGR00161133: Add spi-nor support for mx6qTerry Lv2011-11-01-1/+1
| | | | | | Add spi-nor support for mx6q. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00139221 USDHC Add SDXC UHS-I supportAnish Trivedi2011-10-27-2/+2
| | | | | | | Modified MMC library for UHS-I command sequence Added support to USDHC driver for UHS-I Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00160399 Added support for the MX6Q Sabre-lite boardMahesh Mahadevan2011-10-25-46/+12
| | | | | | Includes support for uSDHC read, write, FEC, SPI-NOR etc. Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00160507 Update the IOMUX implementation for MX6Mahesh Mahadevan2011-10-20-6/+5
| | | | | | | The MX6 code incorrectly uses the Hysteresis bit to decide NO_PAD_CTRL operation Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00139254: Enable MX6Q Uboot Splash ScreenSandor Yu2011-09-02-31/+48
| | | | | | | | | | | | | | Only support LVDS0 splash screen. Enable splash process: 1.define CONFIG_SPLASH_SCREEN in mx6q_sabreauto.h 2.Config U-boot with followed command:() setenv splashimage '0x30000000' #Set splash position as Center setenv splashpos 'm,m' #Set LVDS via LVDS bridge 0 setenv lvds_num 0 Signed-off-by: Sandor Yu <r01008@freescale.com>
* ENGR00139206 MX6 USDHC eMMC 4.4 supportAnish Trivedi2011-07-05-2/+2
| | | | | | | | | | | New bit definitions in USDHC. Added is_usdhc variable to fsl_esdhc_cfg to distinguish between ESDHC and USDHC. Enabled DDR mode support in USDHC. Created a config to customize target delay for DDR mode. Modified USDHC pad settings to make DDR mode work for all emmcs at 50 MHz. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00139198: iMX61 uBoot add ENET supportZeng Zhaoming2011-06-27-62/+65
| | | | | | | | | | | | | | | | Add ENET and AR8031 PHY support to uboot. To make it works on sabreauto, need do following changes: 1. rework phy to output 125M clock from CLK_25M signal, and the 125M clock input to SoC as reference clock to generate RGMII_TXC clock. 2. Enable TXC delay in PHY debug register. 3. set ENET working in RMII mode. 4. set ENET working at 1000M or 100M/10M. 5. set ENET TX fifo to maximum to avoid underrun error. 6. force AR8031 PHY working at 100M Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
* ENGR00144424 MX6: enable uboot for ARM2(SABREAUTO) CPU boardAnson Huang2011-06-24-0/+7637
Use 528M DDR script Disable L2 cache because rom enable L2 cache when use plug-in Fix usdhc pad settings Remove mac address hardcode Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
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