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Remove the dead definiton which never used by iomux-v3 framework
And move the SION bit definiton to arch-mx6/iomux-v3.h for sharing
Signed-off-by: Jason Liu <r64343@freescale.com>
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NO_PAD_I/NO_PAD_MUX not defined correctly, which will cause build error.
And According to iomux-v3.h, the NO_PAD_I/NO_PAD_MUX should be 0 for the
pins which does not have PAD/MUX config.
Signed-off-by: Jason Liu <r64343@freescale.com>
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SPI NOR flash(m25p32-vmw6tg) not probed and function as expected, this
due to the lack of iomux pad config and incorrect CS line.
This patch fix the above issue and also fix the mfg config file
(For the code readable, I intent to omit the following checkpatch warning:
in the iomux/mx6_pins.h WARNING: line over 80 characters)
Signed-off-by: Jason Liu <r64343@freescale.com>
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add support for otg in MX6Q uboot to enable fastboot function.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Add spi-nor support for mx6q.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Modified MMC library for UHS-I command sequence
Added support to USDHC driver for UHS-I
Signed-off-by: Anish Trivedi <anish@freescale.com>
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Includes support for uSDHC read, write, FEC, SPI-NOR etc.
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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Only support LVDS0 splash screen.
Enable splash process:
1.define CONFIG_SPLASH_SCREEN in mx6q_sabreauto.h
2.Config U-boot with followed command:()
setenv splashimage '0x30000000'
#Set splash position as Center
setenv splashpos 'm,m'
#Set LVDS via LVDS bridge 0
setenv lvds_num 0
Signed-off-by: Sandor Yu <r01008@freescale.com>
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New bit definitions in USDHC.
Added is_usdhc variable to fsl_esdhc_cfg to distinguish between ESDHC
and USDHC.
Enabled DDR mode support in USDHC.
Created a config to customize target delay for DDR mode.
Modified USDHC pad settings to make DDR mode work for all emmcs at 50 MHz.
Signed-off-by: Anish Trivedi <anish@freescale.com>
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Add ENET and AR8031 PHY support to uboot.
To make it works on sabreauto, need do following changes:
1. rework phy to output 125M clock from CLK_25M signal,
and the 125M clock input to SoC as reference clock to generate
RGMII_TXC clock.
2. Enable TXC delay in PHY debug register.
3. set ENET working in RMII mode.
4. set ENET working at 1000M or 100M/10M.
5. set ENET TX fifo to maximum to avoid underrun error.
6. force AR8031 PHY working at 100M
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
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Use 528M DDR script
Disable L2 cache because rom enable L2 cache when use plug-in
Fix usdhc pad settings
Remove mac address hardcode
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Richard Zhu <r65037@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Anish Trivedi <anish@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
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