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* driver/ddr/fsl: Fix timing_cfg_2York Sun2016-08-02-1/+1
| | | | | | | | | Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the change was wrong. wr_lat has 5 bits with MSB at [13] and lower 4 bits at [9:12], in big-endian convention. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Thomas Schaefer <Thomas.Schaefer@kontron.com>
* crypto/fsl: Update blob cmd to accept 64bit addressesSumit Garg2016-08-02-3/+10
| | | | | | | | | Update blob cmd to accept 64bit source, key modifier and destination addresses. Also correct output result print format for fsl specific implementation of blob cmd. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* driver: spi: fsl-qspi: remove compile WarningsYunhui Cui2016-08-02-1/+3
| | | | | | | | | | Warnins log: drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’: drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len); Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2016-07-31-5/+22
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| * rockchip: rk3288: Fix pinctrl for GPIO bank 0John Keeping2016-07-31-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers rather than the GRF registers. In the GRF the top half of the register is used as a mask so that some bits can be updated without affecting the others, but in the PMU this feature is not provided and the top half of the register is reserved. Take the same approach as the Linux driver to update the value via read-modify-write but setting the mask for only the bits that have changed. The PMU registers ignore the top 16 bits so this works for both GRF and PMU iomux registers. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * mmc-uclass: correct the device numberKever Yang2016-07-31-3/+3
| | | | | | | | | | | | | | | | | | Not like the mmc-legacy which the devnum starts from 1, it starts from 0 in mmc-uclass, so the device number should be (devnum + 1) in get_mmc_num(). Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffersHans de Goede2016-07-31-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: gpio: Add .xlate function for gpio phandle resolutionChen-Yu Tsai2016-07-31-0/+16
|/ | | | | | | | | | | | | sunxi uses a 2 cell phandle for gpio bindings. Also there are no seperate nodes for each pin bank. Add a custom .xlate function to map gpio phandles to the correct pin bank device. This fixes gpio_request_by_name usage. Fixes: 7aa974858422 ("dm: sunxi: Modify the GPIO driver to support driver model") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* spi: ti_qspi: dra7xx: Add support to use 76.8MHz clockVignesh R2016-07-30-5/+12
| | | | | | | | | | According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update the driver to use the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* sf: sf_params: Add AT25DF321 flash supportWenyou Yang2016-07-30-1/+2
| | | | | | | | Add AT25DF321 flash support. Fix AT25DF321A device name. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: ti_qspi: Remove delay in read path for dra7xxVignesh R2016-07-30-3/+0
| | | | | | | | | | | | As per commit b545a98f5dc563 ("spi: ti_qspi: Add delay for successful bulk erase) says its added to meet bulk erase timing constraints. But bulk erase is a cmd to flash and delay in read path does not make sense. Morever, testing on DRA74/DRA72 evm has shown that this delay is no longer required. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* spi: ti_qspi: Fix compiler warning when DEBUG macro is setVignesh R2016-07-30-2/+2
| | | | | | | | | | clk_div is uninitialized at the beginning of ti_spi_set_speed(), move debug() print after clk_div calculation to avoid compiler warning and to have proper value of clk_div printed during debugging. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* spi: ti_qspi: Fix failure on multiple READ_ID cmdVignesh R2016-07-30-3/+2
| | | | | | | | | | | | | | Populating QSPI_RD_SNGL bit(0x1) in priv->cmd means that value QSPI_INVAL (0x4) is not written to CMD field of QSPI_SPI_CMD_REG in ti_qspi_cs_deactivate(). Therefore CS is never deactivated between successive READ ID which results in sf probe to fail. Fix this by not populating priv->cmd with QSPI_RD_SNGL and OR it wih priv->cmd as required (similar to the convention followed in the driver). Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* spi: Add support for N25Q016AMoritz Fischer2016-07-30-0/+1
| | | | | | | | This commit adds support in the spi-nor driver for the N25Q016A, a 16Mbit SPI NOR flash from Micron. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-07-28-8/+42
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| * pci: allow disabling of pci init/enum via envTim Harvey2016-07-28-0/+4
| | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * serial_mxc: Remove unconditional DCE settingBreno Lima2016-07-21-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 83fd908f28c ("dm: imx: serial: Support DTE mode when using driver model") breaks the serial output for the imx boards that do not use the serial driver model. The reason for the breakage is that it's setting UFCR_DCEDTE unconditionally for the non-dm case. So keep the original behavior by removing UFCR_DCEDTE setting in the non-dm case. Tested on mx7sabresd and mx6wandboard. Signed-off-by: Breno Lima <breno.lima@nxp.com> Acked-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * imx_watchdog: add weak attribute to reset_cpu functionStefan Agner2016-07-19-1/+1
| | | | | | | | | | | | | | This allows to overwrite reset_cpu function in case a board level reset is preferred (e.g. through PMIC). Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * usb: ehci-mx6: introduce config for high active power pinStefan Agner2016-07-19-0/+13
| | | | | | | | | | | | | | | | | | Add a new config CONFIG_MXC_USB_OTG_HACTIVE which configures the OTG Power Pin to be high active. Low active is the reset value of the affected configuration register, hence the config option is named by the non-reset configuration. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * usb: ehci-mx6: configure power polarity in usb_power_configStefan Agner2016-07-19-5/+5
| | | | | | | | | | | | | | | | USBNC_n_CTRL1 bit 9 actually controls the power pin polarity. Rename UCTRL_PM to align reference manual and set the bit in the appropriate callback usb_power_config. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * usb: move CONFIG_USB_EHCI_MX7 to KconfigStefan Agner2016-07-19-0/+7
| | | | | | | | | | | | | | Create an entry for "config USB_EHCI_MX7" in Kconfig and switch over to it for all boards. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * dm: imx: serial: Support DTE mode when using driver modelStefan Agner2016-07-19-1/+8
| | | | | | | | | | | | | | | | | | | | The MXC UART IP can be run in DTE or DCE mode. This depends on the board wiring and the pinmux used and hence is board specific. This extends platform data with a new field to choose wheather DTE mode shall be used. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * driver/net/fec: support fixed speed connectionHannes Schmelzer2016-07-12-0/+4
| | | | | | | | | | | | | | | | | | If MAC is directly connected to another MAC (like a switch for example) we don't need to probe for a phy, autoneogation and so on. We simply have to setup speed. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * pcie_imx: increment timeout for link upStefano Babic2016-07-12-1/+1
| | | | | | | | | | | | | | On some boards, the current 20ms timeout is hit. Increase it to 40mS. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-07-27-199/+451
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| * | mmc: dw_mmc: reduce timeout detection cycleXu Ziyuan2016-07-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | It's no need to speed 10 seconds to wait the mmc device out from busy status. 500 milliseconds enough. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | Add a power domain framework/uclassStephen Warren2016-07-27-0/+300
| | | | | | | | | | | | | | | | | | | | | | | | | | | Many SoCs allow power to be applied to or removed from portions of the SoC (power domains). This may be used to save power. This API provides the means to control such power management hardware. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | dm: socfpga: mmc: Support CONFIG_BLKSimon Glass2016-07-27-1/+31
| | | | | | | | | | | | | | | | | | Update the driver to support using driver model for block devices. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: mmc: zynq: Convert zynq to use driver model for MMCSimon Glass2016-07-27-5/+34
| | | | | | | | | | | | | | | | | | | | | Move zynq to the latest driver model support by enabling CONFIG_DM_MMC, CONFIG_DM_MMC_OPS and CONFIG_BLK. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: zynq: usb: Convert to CONFIG_DM_USBSimon Glass2016-07-27-52/+51
| | | | | | | | | | | | | | | | | | Convert zynq USB to driver model. Note this is tested on zynq-zybo only. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | net: phy: marvell: Add a missing errno.h headerSimon Glass2016-07-27-0/+1
| | | | | | | | | | | | | | | | | | This corrects a build error on zynqmp. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: Use dm_scan_fdt_dev() directly where possibleSimon Glass2016-07-27-108/+19
| | | | | | | | | | | | | | | | | | | | | Quite a few places have a bind() method which just calls dm_scan_fdt_dev(). We may as well call dm_scan_fdt_dev() directly. Update the code to do this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: Convert users from dm_scan_fdt_node() to dm_scan_fdt_dev()Simon Glass2016-07-27-43/+16
| | | | | | | | | | | | | | | | | | | | | This new function is more convenient for callers, and handles pre-relocation situations automatically. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: core: Add a function to bind child devicesSimon Glass2016-07-27-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently use dm_scan_fdt_node() to bind devices. It is an internal function and it requires the caller to know whether we are pre- or post- relocation. This requirement has become quite common in drivers, so the current function is not ideal. Add a new function with fewer arguments, that does not require internal headers. This can be used directly as a post_bind() method if needed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: mmc: dwmmc: use the callback functions as staticJaehoon Chung2016-07-27-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | There are no places to call these functions. It should be used the callback function. Then it can be used as static functions. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2016-07-27-1/+3
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| * | video: allow version string to be optional when using LOGOTim Harvey2016-07-11-1/+3
| |/ | | | | | | | | | | | | The CONFIG_HIDE_LOGO_VERSION config can be used to disable putting the U-Boot version string on top of the logo. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-07-26-12/+1
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| * | net: sun8i_emac: Drop redundant and incorrect setting of syscon registerChen-Yu Tsai2016-07-26-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | net: sun8i_emac: Do not configure AHB2 clockChen-Yu Tsai2016-07-26-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-07-26-5/+129
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| * | | drivers: net/fm: Add Fman support for LS1046AMingkai Hu2016-07-26-0/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Fman module on LS1046A is similiar with that on LS1043A but LS1046A has one more XFI (10GbE) interface. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | DM: crypto/fsl: Enable rsa DM driver usage before relocationSumit Garg2016-07-26-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable rsa signature verification in SPL framework before relocation for verification of main u-boot. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | i2c: fsl: Fix driver initializationmario.six@gdsys.cc2016-07-26-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to a oversight in testing, the initialization of the recently introduced Freescale I2C DM driver works only for 36 bit mode of e.g. the MPC85XX SoCs (specifically, if the physical addresses are 64 bit wide and the DT addresses 32 bit wide). This patch corrects the initialization so that it will work in a more general setting. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: York Sun <york.sun@nxp.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2016-07-26-347/+858
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| * | | | i2c: mvtwsi: Add documentationmario.six@gdsys.cc2016-07-26-19/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add full documentation to all driver functions. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | | i2c: mvtwsi: Make delay times frequency-dependentmario.six@gdsys.cc2016-07-26-42/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices using the MVTWSI driver have the option to run at speeds faster than Standard Mode (100kHZ). On the Armada 38x controllers, this is actually necessary, since due to erratum FE-8471889, a timing violation concerning repeated starts prevents the controller from working correctly in Standard Mode. One of the workarounds recommended in the erratum is to set the bus to Fast Mode (400kHZ) operation and ensure all connected devices are set to Fast Mode. In the current version of the driver, however, the delay times are hard-coded to 10ms, corresponding to Standard Mode operation. To take full advantage of the faster modes, we would need to either keep the currently configured I2C speed in a globally accessible variable, or pass it to the necessary functions as a parameter. For DM, the first option is not a problem, and we can simply keep the speed in the private data of the driver. For the legacy interface, however, we would need to introduce a static variable, which would cause problems with boots from NOR flashes; see commit d6b7757 "i2c: mvtwsi: Eliminate twsi_control_flags." As to not clutter the interface with yet another parameter, we therefore keep the default 10ms delays for the legacy functions. In DM mode, we make the delay time dependant on the frequency to allow taking full advantage of faster modes of operation (tested with up to 1MHZ frequency on Armada MV88F6820). Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | | i2c: mvtwsi: Handle zero-length offsets properlymario.six@gdsys.cc2016-07-26-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zero-length offsets are not properly handled by the driver. When a read operation with a zero-length offset is started, a START condition is asserted, and since no offset bytes are transferred, a repeated START is issued immediately after, which confuses the controller. To fix this, we send the first START only if any address bytes need to be sent, and keep track of the expected start status accordingly. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | | i2c: mvtwsi: Add compatibility to DMmario.six@gdsys.cc2016-07-26-1/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the necessary functions and Kconfig entry to make the MVTWSI I2C driver compatible with the driver model. A possible device tree entry might look like this: i2c@11100 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; clock-frequency = <100000>; u-boot,i2c-slave-addr = <0x0>; }; Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | | i2c: mvtwsi: Make address length variablemario.six@gdsys.cc2016-07-26-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The length of the address parameter of the __twsi_i2c_read and __twsi_i2c_write functions is fixed to four bytes. As a final step in the preparation of the DM conversion, we make the length of this parameter variable by turning it into an array of bytes, and convert the 32 bit value that's passed to the legacy functions into a four-byte-array on the fly. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
generated by cgit v1.1 at 2024-11-07 16:21:01 +0000