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* | | mmc: atmel: rename CONFIG_ATMEL_SDHCI to CONFIG_MMC_SDHCI_ATMELMasahiro Yamada2017-01-31-12/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make the naming scheme consistent; all SDHCI-base drivers prefixed with CONFIG_MMC_SDHCI_. While we are here, add "depends on ARCH_AT91". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | mmc: pic32: rename CONFIG_PIC32_SDHCI to CONFIG_MMC_SDHCI_PIC32Masahiro Yamada2017-01-31-8/+8
| | | | | | | | | | | | | | | | | | | | | Make the naming scheme consistent; all SDHCI-base drivers prefixed with CONFIG_MMC_SDHCI_. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | mmc: msm: rename CONFIG_MSM_SDHCI to CONFIG_MMC_SDHCI_MSMMasahiro Yamada2017-01-31-11/+11
| | | | | | | | | | | | | | | | | | | | | Make the naming scheme consistent; all SDHCI-base drivers prefixed with CONFIG_MMC_SDHCI_. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | mmc: rockchip: rename CONFIG_ROCKCHIP_SDHCI to CONFIG_MMC_SDHCI_ROCKCHIPMasahiro Yamada2017-01-31-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make the naming scheme consistent; all SDHCI-base drivers prefixed with CONFIG_MMC_SDHCI_. While we are here, add "depends on ARCH_ROCKCHIP". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | mmc: zynq: rename CONFIG_ZYNQ_SDHCI to CONFIG_MMC_SDHCI_ZYNQMasahiro Yamada2017-01-31-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make the naming scheme consistent; all SDHCI-base drivers prefixed with CONFIG_MMC_SDHCI_. While we are here, add "depends on ARCH_ZYNQ || ARCH_ZYNQMP". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | mmc: sandbox: rename CONFIG, fix dependency, and use it in MakefileMasahiro Yamada2017-01-31-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [1] Rename CONFIG_SANDBOX_MMC to CONFIG_MMC_SANDBOX for consistency I want all MMC driver options prefixed with CONFIG_MMC_. [2] Fix dependency Add necessary depends on to avoid compile error. Instead "depends on MMC" is unneeded because this config entry resides inside of "if MMC". [3] Currently, this config symbol is not referenced at all. Use it to enable/disable the driver in Makefile. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | mmc: move CONFIG_GENERIC_MMC to KconfigMasahiro Yamada2017-01-31-0/+4
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now, CONFIG_GENERIC_MMC seems equivalent to CONFIG_MMC. Let's create an entry for "config GENERIC_MMC" with "default MMC", then convert all macro defines in headers to Kconfig. Almost all of the defines will go away. I see only two exceptions: configs/blanche_defconfig configs/sandbox_noblk_defconfig They define CONFIG_GENERIC_MMC, but not CONFIG_MMC. Something might be wrong with these two boards, so should be checked later. Anyway, this is the output of the moveconfig tool. This commit was created as follows: [1] create a config entry in drivers/mmc/Kconfig [2] tools/moveconfig.py -r HEAD GENERIC_MMC [3] manual clean-up of garbage comments in doc/README.* and include/configs/*.h Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | i2c: uniphier-f: use readl_poll_timeout() to poll registersMasahiro Yamada2017-01-29-24/+10
| | | | | | | | | | | | | | The readl_poll_timeout() is a useful helper to poll registers and error out if the condition is not met. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | i2c: uniphier(-f): remove unneeded #include <dm/root.h>Masahiro Yamada2017-01-29-2/+0
| | | | | | | | | | | | This include is unnecessary for low-level drivers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | clk: uniphier: fix compatible strings for Pro5, PXs2, LD20 SD clockMasahiro Yamada2017-01-29-3/+3
| | | | | | | | | | | | I missed to update them when DT files were resynced with Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: SPI: stm32: add stm32f746 qspi driverMichael Kurz2017-01-28-0/+637
| | | | | | | | | | | | This patch adds support for the QSPI IP found in stm32f7 devices. Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
* | net: phy: add SMSC LAN8742 phyMichael Kurz2017-01-28-0/+12
| | | | | | | | | | | | | | This patch adds support for SMSC LAN8742 in phylib Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: stm32: add designware mac glue code for stm32Michael Kurz2017-01-28-0/+1
| | | | | | | | | | | | | | | | This patch adds glue code required for enabling the designware mac on stm32f7 devices. Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | aspeed: Add basic ast2500-specific drivers and configurationmaxims@google.com2017-01-28-0/+274
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Add drivers common to all Aspeed SoCsmaxims@google.com2017-01-28-0/+166
|/ | | | | | | | | | | | | | | | | Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge git://www.denx.de/git/u-boot-marvellTom Rini2017-01-26-4/+515
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| * mmc: Add Marvell Xenon SDHCI controller driverStefan Roese2017-01-25-0/+509
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver implementes platform specific code for the Xenon SDHCI controller which is integrated in the Marvell MVEBU Armada 37xx and Armada 7k / 8K SoCs. History: This driver is ported from the Marvell U-Boot version 2015.01 which is written by Victor Gu <xigu@marvell.com> with minor changes ported from the Linux driver which is written by Ziji Hu <huziji@marvell.com>. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * mmc: sdhci: Add support for optional controller specific set_ios_post()Stefan Roese2017-01-25-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SDHCI drivers might need to do some special controller configuration after the common clock set_ios() function has been called (speed / width configuration). This patch adds a call to the newly created function set_ios_port() when its configured in the host driver. This will be used by the Xenon SDHCI controller driver used on the Marvell Armada 3700 and 7k/8k ARM64 SoCs. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * mmc: sdhci: Clear SDHCI_CLOCK_CONTROL before configuring the new valueStefan Roese2017-01-25-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch completely clears the SDHCI_CLOCK_CONTROL register before the new value is configured instead of just clearing the 2 bits SDHCI_CLOCK_CARD_EN and SDHCI_CLOCK_INT_EN. Without this change, some clock configurations will lead to the "Internal clock never stabilised." error message on the Xenon SDHCI controller used on the Marvell Armada 3700 and 7k/8k ARM64 SoCs. The Linux SDHCI core driver also writes 0 to this register before the new value is configured. So this patch simplifies the driver a bit and brings the U-Boot driver more in-line with the Linux one. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2017-01-25-0/+7
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| * | mpc85xx: pcie: Implement workaround for Erratum A007815Tony O'Brien2017-01-24-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The read-only-write-enable bit is set by default and must be cleared to prevent overwriting read-only registers. This should be done immediately after resetting the PCI Express controller. Reviewed-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz> [York S: Move SYS_FSL_ERRATUM_A007815 to Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
* | | Drop CONFIG_WINBOND_83C553Simon Glass2017-01-25-207/+0
| |/ |/| | | | | | | | | This is not used in U-Boot. Drop this option and associated dead code. Signed-off-by: Simon Glass <sjg@chromium.org>
* | mmc: Print error code for mmc_complete_init failureJagan Teki2017-01-23-1/+3
| | | | | | | | | | | | | | | | Print the error code for non-zero (failure case) instead of making debug statement without any condition, this usually gives proper clue in failure condition. Log:
* | mmc: sdhci: Distinguish between base clock and maximum peripheral frequencyStefan Herbrechtsmeier2017-01-23-28/+45
|/ | | | | | | | | | The sdhci controller assumes that the base clock frequency is fully supported by the peripheral and doesn't support hardware limitations. The Linux kernel distinguishes between base clock (max_clk) of the host controller and maximum frequency (f_max) of the card interface. Use the same differentiation and allow the platform to constrain the peripheral interface. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
* pinctrl: uniphier: support UniPhier PXs3 pinctrl driverMasahiro Yamada2017-01-22-9/+156
| | | | | | Add pin configuration and pinmux support for UniPhier PXs3 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* status_led: Kconfig migrationUri Mashiach2017-01-21-54/+54
| | | | | | | | | | | | | Move all of the status LED feature to drivers/led/Kconfig. The LED status definitions were moved from the board configuration files to the defconfig files. TBD: Move all of the definitions in the include/status_led.h to the relevant board's defconfig files. Tested boards: CL-SOM-AM57x, CM-T335 Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
* status_led: Kconfig migration - introductionUri Mashiach2017-01-21-1/+322
| | | | | | | | | Move all of the status LED feature to drivers/led/Kconfig. doc/README.LED updated to reflect the Kconfig implementation. Tested boards: CL-SOM-AM57x, CM-T335 Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
* serial, ns16550: bugfix: ns16550 fifo not enabledHeiko Schocher2017-01-20-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor" breaks u-boot commandline working with long commands sending to the board. Since the above patch, you have to setup the fcr register. For board/archs which enable OF_PLATDATA, the new field fcr in struct ns16550_platdata is not filled with a default value ... This leads in not setting up the uarts fifo, which ends in problems, when you send long commands to u-boots commandline. Detected this issue with automated tbot tests on am335x based shc board. The error does not popup, if you type commands. You need to copy&paste a long command to u-boots commandshell (or send a long command with tbot) Possible boards/plattforms with problems: ./arch/arm/cpu/arm926ejs/lpc32xx/devices.c ./arch/arm/mach-tegra/board.c ./board/overo/overo.c ./board/quipos/cairo/cairo.c ./board/logicpd/omap3som/omap3logic.c ./board/logicpd/zoom1/zoom1.c ./board/timll/devkit8000/devkit8000.c ./board/lg/sniper/sniper.c ./board/ti/beagle/beagle.c ./drivers/serial/serial_rockchip.c Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-01-19-642/+764
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| * mmc: fsl_esdhc: move 'status' property fixup into a weak functionYangbo Lu2017-01-18-7/+14
| | | | | | | | | | | | | | | | Move fdt fixup of 'status' property into a weak function. This allows board to define 'status' fdt fixup by themselves. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * pmic: pmic_mc34vr500: Add a driver for the mc34vr500 pmicHou Zhiqiang2017-01-18-0/+40
| | | | | | | | | | | | | | | | | | This patch adds a simple pmic driver for the mc34vr500 pmic which is used in conjunction with the fsl T1 and LS1 series SoC. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * mmc: fsl_esdhc: add 'fsl, esdhc' into of_match tableYangbo Lu2017-01-18-0/+1
| | | | | | | | | | | | | | | | This patch is to add 'fsl,esdhc' into of_match table to support driver model for QorIQ eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * mmc: fsl_esdhc: make GPIO support optionalYangbo Lu2017-01-18-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | There would be compiling error as below when enable driver model for esdhc. undefined reference to `dm_gpio_get_value' undefined reference to `gpio_request_by_name_nodev' This patch is to make GPIO support optional with CONFIG_DM_GPIO. Because all boards of QorIQ platform don't need it and they just check register for CD/WP status, only some boards of i.MX platform require this. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * kconfig: move FSL_PCIE_COMPAT to platform KconfigHou Zhiqiang2017-01-18-4/+4
| | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * pci: layerscape: remove unnecessary legacy codeMinghuan Lian2017-01-18-716/+1
| | | | | | | | | | | | | | | | | | | | All Layerscape SoCs have supported new PCIe driver based on DM. The lagecy PCIe driver code is unused and can be removed. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * pci: layerscape: add pci driver based on DMMinghuan Lian2017-01-18-0/+754
| | | | | | | | | | | | | | | | | | | | | | | | | | There are more than five kinds of Layerscape SoCs. unfortunately, PCIe controller of each SoC is a little bit different. In order to avoid too many macro definitions, the patch addes a new implementation of PCIe driver based on DM. PCIe dts node is used to describe the difference. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * pci: layerscape: move kernel DT fixup to a separate fileHou Zhiqiang2017-01-18-311/+343
| | | | | | | | | | | | | | | | | | To make the layerscape pcie driver clear, move the kernel DT fixup code from pcie_layerscape.c to pcie_layerscape_fixup.c. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * dm: pci: remove pci_bus_to_hose(0) callingMinghuan Lian2017-01-18-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There may be multiple PCIe controllers in a SoC. It is not correct that always calling pci_bus_to_hose(0) to get the first PCIe controller for the PCIe device connected other controllers. We just remove this calling because hose always point the correct PCIe controller. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * dm: pci: return the real controller in pci_bus_to_hose()Minghuan Lian2017-01-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | for the legacy PCI driver, the function pci_bus_to_hose() returns the real PCIe controller. To keep consistency, this function is changed to return the PCIe controller pointer of the root bus instead of the current PCIe bus. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2017-01-18-63/+149
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| * | i2c: i2c-cdns: No need for dedicated probe functionMoritz Fischer2017-01-18-21/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The generic probe code in dm works, so get rid of the leftover cruft. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Cc: Heiko Schocher <hs@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: u-boot@lists.denx.de
| * | i2c: i2c-cdns: Implement workaround for hold quirk of the rev 1.0Moritz Fischer2017-01-18-30/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revision 1.0 of this IP has a quirk where if during a long read transfer the transfer_size register will go to 0, the master will send a NACK to the slave prematurely. The way to work around this is to reprogram the transfer_size register mid-transfer when the only the receive fifo is known full, i.e. the I2C bus is known non-active. The workaround is based on the implementation in the linux-kernel. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Cc: Heiko Schocher <hs@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: u-boot@lists.denx.de
| * | i2c: i2c-cdns: Reorder timeout loop for interrupt waitingMoritz Fischer2017-01-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reorder the timeout loop such that we first check if the condition is already true, and then call udelay() so if the condition is already true, break early. Reviewed-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Cc: Heiko Schocher <hs@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: u-boot@lists.denx.de
| * | i2c: i2c-cdns: Detect unsupported sequences for rev 1.0Moritz Fischer2017-01-18-14/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revision 1.0 of this IP has a couple of issues, such as not supporting repeated start conditions for read transfers. So scan through the list of i2c messages for these conditions and report an error if they are attempted. This has been fixed for revision 1.4 of the IP, so only report the error when the IP can really not do it. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Cc: Heiko Schocher <hs@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: u-boot@lists.denx.de
| * | i2c: mux: Allow muxes to work as children of i2c bus without i2c-parentMoritz Fischer2017-01-18-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For mux check if the parent is already a device of UCLASS_I2C and if yes just use that. Otherwise see if someone specified an i2c-parent phandle. This mimics the behavior found in the Kernel, as it removes the requirement to explicitly specify a i2c-parent phandle. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Cc: Heiko Schocher <hs@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: u-boot@lists.denx.de
* | | Merge git://git.denx.de/u-boot-samsungTom Rini2017-01-18-1/+12
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| * | i2c: Kconfig: Add SYS_I2C_S3C24X0 entryJaehoon Chung2017-01-18-0/+5
| | | | | | | | | | | | | | | | | | | | | Adding Kconfig for SYS_I2C_S3C24X0. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | i2c: s3c24x0: fix the compiler error for exynos4Jaehoon Chung2017-01-18-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_SYS_I2C_S3C24X0_SLAVE isn't defined, then complie error should be occurred. This patch is for preventing it. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2017-01-17-1/+1
|\ \ \ | | | | | | | | | | | | | | | | | | | | - Enable eMMC driver for LD11/LD20 SoCs - Refactoring of SoC init code - Bug fix of pinctrl driver
| * | | pinctrl: uniphier: fix Ethernet (RMII) pin-mux setting for LD20Masahiro Yamada2017-01-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the pin-mux values for the MDC, MDIO, MDIO_INTL, PHYRSTL pins. Fixes: fc9da85c6059 ("pinctrl: uniphier: add Ethernet pin-mux settings") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit v1.1 at 2024-11-18 02:00:07 +0000