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* spi: add config option to enable the WP pin function on st micron flashesHeiko Schocher2014-07-23-0/+34
| | | | | | | | | enable the W#/Vpp signal to disable writing to the status register on ST MICRON flashes like the N25Q128 thorugh the new config option CONFIG_SYS_SPI_ST_ENABLE_WP_PIN Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* pwm, imx6: add support for pwm modul on imx6Heiko Schocher2014-07-23-0/+162
| | | | | | | | | | add basic support for the pwm modul found on imx6. Pieces of this code are based on linux code from drivers/pwm/pwm-imx.c Commit "cd3de83f1476 Linux 3.16-rc4" Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* usb: phy: omap_usb_phy: implement usb_phy_power() for AM437xFelipe Balbi2014-07-09-1/+16
| | | | | | | | Newer AM437x silicon requires us to explicitly power up the USB2 PHY. By implementing usb_phy_power() we can achieve that. Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: host: xhci: make sure to power up PHYFelipe Balbi2014-07-09-0/+1
| | | | | | | some boards won't work if the PHY isn't explicitly powered up. Signed-off-by: Felipe Balbi <balbi@ti.com>
* board: gdsys: Make gdsys osd hardware detection more robustDirk Eibach2014-07-07-1/+0
| | | | Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* i2c: IHS I2C master driverDirk Eibach2014-07-07-0/+205
| | | | | | | | IHS I2C master support was merely a hack in the osd driver. Now it is a proper u-boot I2C framework driver, supporting the v2.00 master features. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* blackfin: Fix warning about undefined functionVasili Galka2014-07-07-0/+1
| | | | | | | get_sclk() was not defined in bfin_wdt.c, include the corresponding header. Cc: Sonic Zhang <sonic.adi@gmail.com> Signed-off-by: Vasili Galka <vvv444@gmail.com>
* mpc8xx: remove v37 board supportMasahiro Yamada2014-07-07-7/+1
| | | | | | This board is old enough and has no maintainer. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* mpc8xx: remove rbc823 board supportMasahiro Yamada2014-07-07-66/+1
| | | | | | This board is old enough and has no maintainer. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* mpc8xx: remove RPXlite_dw, quantum board supportMasahiro Yamada2014-07-07-89/+0
| | | | | | These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* tpm: don't use unneeded double bracketsJeroen Hofstee2014-07-07-1/+1
| | | | | | | | clang is tempted to inteprete such a condition as a assignment as well. Since it isn't don't use double brackets. cc: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* build: define CPU only when arch/${ARCH}/cpu/${CPU} existsMasahiro Yamada2014-07-07-1/+1
| | | | | | | | | | | | | | | | | | | The directory arch/${ARCH}/cpu/${CPU} does not exist in avr32, blackfin, microblaze, nios2, openrisc, sandbox, x86. These architectures have only one CPU type. Defining CPU should not be required for such architectures. This commit allows cpu field (= the 3rd field of boards.cfg) to be kept blank. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Sonic Zhang <sonic.zhang@analog.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2014-07-07-17/+27
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| * i2c: tegra: dump alen in debug statementsStephen Warren2014-07-03-4/+4
| | | | | | | | | | | | | | | | | | Since tegra_i2c_{read,write}'s debug() call dumps the chip address, dump the address length (alen) too, so the address value can be correctly interpreted. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
| * i2c: tegra: write clean data to TX FIFOStephen Warren2014-07-03-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra I2C controller's TX FIFO contains 32-bit words. If the final FIFO entry of a transaction contains fewer than 4 bytes, the driver currently fills the unused FIFO bytes with uninitialized data. This can be confusing when reading back the FIFO content for debugging purposes. Solve this by explicitly initializing the variable containing FIFO data before filling it (partially) with data. With this change, send_recv_packets()'s loop's if (is_write) code mirrors the else (i.e. read) branch. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
| * i2c: tegra: use repeated start for readsStephen Warren2014-07-03-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I2C read transactions are typically implemented as follows: START(write) address REPEATED_START(read) data... STOP However, Tegra's I2C driver currently implements reads as follows: START(write) address STOP START(read) data... STOP This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board, leading to corrupted read data in some cases. Fix the driver to chain the transactions together using repeated starts to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
* | watchdog/denali: Adding DesignWare watchdog driver supportChin Liang See2014-07-05-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | To add the DesignWare watchdog driver support. It required information such as register base address and clock info from configuration header file within include/configs folder. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
* | arm: ep9315: Return back Cirrus Logic EDB9315A board supportSergey Kostanbaev2014-07-04-0/+314
| | | | | | | | | | | | | | This patch returns back support for old ep93xx processors family Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com> Cc: albert.u.boot@aribaud.net
* | gpio: spear_gpio: Fix gpio_set_value() implementationAxel Lin2014-07-04-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current gpio_set_value() implementation, it always sets the gpio control bit no matter the value argument is 0 or 1. Thus the GPIOs never set to low. This patch fixes this bug. The address bus is used as a mask on read/write operations, so that independent software drivers can set their GPIO bits without affecting any other pins in a single write operation. Thus we don't need a read-modify-write to update the register. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Vipin Kumar <vipin.kumar@st.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
* | armv8/fsl-lsch3: Add support to load and start MC FirmwareJ. German Rivera2014-07-03-0/+275
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
* | ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoCYork Sun2014-07-03-0/+5
|/ | | | | | | | | | | | | | Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-07-02-40/+1035
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| * Merge remote-tracking branch 'u-boot-samsung/master'Albert ARIBAUD2014-07-01-6/+12
| |\ | | | | | | | | | | | | | | | | | | | | | Conflicts: boards.cfg Conflict was trivial between goni maintainer change and lager_nor removal.
| | * PMIC: MAX77686: fix invalid bus checkJeroen Hofstee2014-06-23-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since p->bus is unsigned checking for negative values is optimized away. Since bus is already used as an argument use tmp. While at it, don't declare variables in the middle of a function. cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos: SPI: Fix reading data from SPI flashAkshay Saraswat2014-06-23-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI recieve and transfer code in exynos_spi driver has a logical bug. We read data in a variable which can hold an integer. Then we assign this integer 32 bit value to another variable which has data type uchar. Latter represents a unit of our recieve buffer. Everytime when we write a value to our recieve buffer we step ahead by 4 units when actually we wrote to one unit. This results in the loss of 3 bytes out of every 4 bytes recieved. This patch intends to fix this bug. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-07-01-3/+84
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| | * | spi: davinci: Fix register address for SPI1_BUSAxel Lin2014-06-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix a trivial copy-paste bug. Signed-off-by: Axel Lin <axel.lin@ingics.com>
| | * | ARM: keystone: aemif: move aemif driver to drivers/memory/ti-aemif.cKhoronzhuk, Ivan2014-06-19-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move AEMIF driver to drivers/memory/ti-aemif.c along with AEMIF definitions collected in arch/arm/include/asm/ti-common/ti-aemif.h Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | mtd: nand: davinci: add header file for driver definitionsKhoronzhuk, Ivan2014-06-19-2/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The definitions inside emif_defs.h concern davinci nand driver and should be in it's header. So create header file for davinci nand driver and move definitions from emif_defs.h and nand_defs.h to it. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> [trini: Fixup more davinci breakage] Signed-off-by: Tom Rini <trini@ti.com>
| * | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-30-2/+239
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| | * | dwc_ahsata: return failure for MX6 if not IMX6Q/IMX6DTim Harvey2014-06-06-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return failure instead of attempting a memory access that results in a data abort and reset. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * | spl: nand: add support for mxs nandTim Harvey2014-06-06-0/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This utilizes existing mxs_nand support layer to provide a method to load an image off nand for SPL. The flash device will be detected in order to support multiple flash devices instead of having layout hard coded at build time. Cc: Stefan Roese <sr@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Andy Ng <andreas2025@gmail.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Tom Rini <trini@ti.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * | serial_mxc: disable new features of autobaud detectionEric Nelson2014-05-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bit 7 of UCR3 is described in the i.MX3x/i.MX5x/i.MX6x reference manuals as follows: Autobaud Detection Not Improved-. Disables new features of autobaud detection (See Baud Rate Automatic Detection Protocol, for more details). 0 Autobaud detection new features selected 1 Keep old autobaud detection mechanism On at least i.MX6DQ, i.MX6DLS and i.MX53, the "new features" occasionally cause the receiver to get out of sync and continuously produce received characters of '\xff'. This patch disables the "new feature" on all boards, since there's no support for auto-baud in U-Boot on any of them. More details are available in this post on i.MX Community: https://community.freescale.com/message/403254 Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-25-236/+528
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| * | | | video: atmel_hlcdfb: enable dcache supportWu, Josh2014-06-14-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support dcache, we need flush DMA descriptor buffer before enable lcd DMA. Also we need call lcd_set_flush_dcache(1) to make lcd driver flush the lcd buffer if there is any change. Cc: Anatolij Gustschin <agust@denx.de> Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | | net: macb: enable dcache in macbWu, Josh2014-06-14-4/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add to code to flush the dcache after we writing in DMA buffer. Also we need invalidate the dcache before we check the status in the DMA buffer. Tested in SAMA5D3x-EK with gmac0. Tftp download speed shows in below: Disable DCache: 1.1 MiB/s Enable DCache: 1.6 MiB/s Increase speed with about 40%. The code should have no impact with the boards which are not enable_dcache(). Tested in AT91SAM9M10G45EK. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | | macb: make checkpatch cleanAndreas Bießmann2014-06-14-27/+29
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | This also renames the CONFIG_SYS_MACB_xx defines. They are used just local and therefore don't need the CONFIG_SYS_ prefix. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Josh Wu <josh.wu@atmel.com>
| * | | arm: vf610: Add QSPI driver supportAlison Wang2014-06-09-0/+610
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Freescale QSPI driver support for VF610. Signed-off-by: Alison Wang <Huan.Wang@freescale.com> Signed-off-by: Chao Fu <b44548@freescale.com>
* | | | usb: ci_udc: use var name ep/ci_ep consistentlyStephen Warren2014-07-02-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Almost all of ci_udc.c uses variable name "ep" for a struct usb_ep and "ci_ep" for a struct ci_ep. This is nice and consistent, and helps people know what type a variable is without searching for the declaration. handle_ep_complete() doesn't do this, so fix it to be consistent. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | USB: gadget: atmel: zero out allocated requestsStephen Warren2014-07-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A UDC's alloc_request method should zero out the newly allocated request. Ensure the Atmel driver does so. This issue was found by code inspection, following the investigation of an intermittent issue with ci_udc, which was tracked down to failing to zero out allocated requests following some of my changes. All other UDC drivers already zero out requests in one way or another. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | usb: ci_udc: don't memalign() struct ci_req allocationsStephen Warren2014-07-02-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | struct ci_req is a purely software structure, and needs no specific memory alignment. Hence, allocate it with calloc() rather than memalign(). The use of memalign() was left-over from when struct ci_req was going to hold the aligned bounce buffer, but this is now dynamically allocated. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | usb: ci_udc: remove controller.items arrayStephen Warren2014-07-02-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no need to store an array of QTD pointers in the controller. Since the calculation is so simple, just have ci_get_qtd() perform it at run-time, rather than pre-calculating everything. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | usb: ci_udc: fix items array size/stride calculationStephen Warren2014-07-02-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2 QTDs are allocated for each EP. The current allocation scheme aligns the first QTD in each pair, but simply adds the struct size to calculate the second QTD's address. This will result in a non-cache-aligned addresss IF the system's ARCH_DMA_MINALIGN is not 32 bytes (i.e. the size of struct ept_queue_item). Similarly, the original ilist_ent_sz calculation aligned the value to ARCH_DMA_MINALIGN but didn't take the USB HW's 32-byte alignment requirement into account. This doesn't cause a practical issue unless ARCH_DMA_MINALIGN < 32 (which I suspect is quite unlikely), but we may as well fix the code to be explicit, so it's obviously completely correct. The new value of ILIST_ENT_SZ takes all alignment requirements into account, so we can simplify ci_{flush,invalidate}_qtd() by simply using that macro rather than calling roundup(). Similarly, the calculation of controller.items[i] can be simplified, since each QTD is evenly spaced at its individual alignment requirement, rather than each pair being aligned, and entries within the pair being spaced apart only by structure size. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | usb: ci_udc: lift ilist size calculations to global scopeStephen Warren2014-07-02-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will allow functions other than ci_udc_probe() to make use of the constants in a future change. This in turn requires converting the const int variables to #defines, since the initialization of one global const int can't depend on the value of another const int; the compiler thinks it's non-constant if that dependency exists. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | usb: ci_udc: don't assume QTDs are adjacent when transmitting ZLPsStephen Warren2014-07-02-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix ci_ep_submit_next_request()'s ZLP transmission code to explicitly call ci_get_qtd() to find the address of the other QTD to use. This will allow us to correctly align each QTD individually in the future, which may involve leaving a gap between the QTDs. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | usb: ci_udc: fix ci_flush_{qh,qtd} calls in ci_udc_probe()Stephen Warren2014-07-02-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ci_udc_probe() initializes a pair of QHs and QTDs for each EP. After each pair has been initialized, the pair is cache-flushed. The conversion from QH/QTD index [0..2*NUM_END_POINTS) to EP index [0..NUM_ENDPOINTS] is incorrect; it simply subtracts 1 (which yields the QH/QTD index of the first entry in the pair) rather than dividing by two (which scales the range). Fix this. On my system, this avoids cache debug prints due to requests to flush unaligned ranges. This is caused because the flush calls happen before the items[] array entries are initialized for all but EP0. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | usb: eth: smsc95xx: add LAN9500A device IDIlya Ledvich2014-06-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add LAN9500A product ID (0x9e00) in order to support LAN9500A based dongles. Tested on cm_t335. Signed-off-by: Ilya Ledvich <ilya@compulab.co.il> Acked-by: Marek Vasut <marex@denx.de>
* | | | usb: fastboot: fix potential buffer overflowJeroen Hofstee2014-06-25-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cb_getvar tries to prevent overflowing the response buffer by using strncat. But strncat takes the number of data bytes copied as a limit not the total buffer length so it can still overflow. Pass the correct value instead. cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de> cc: Rob Herring <robh@kernel.org> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | | | usb: xhci: (likely) fix bracket in if conditionJeroen Hofstee2014-06-25-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because of the brackets the & and && is evaluated before the comparison. This is likely not the intention. Change it to test the first and second condition to both be true. cc: Marek Vasut <marex@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | | | usb:g_dnl:f_thor: remove memset before memcpyJeroen Hofstee2014-06-25-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | since ALLOC_CACHE_ALIGN_BUFFER defines a pointer and not a buffer, the memset with sizeof(rqt) likely does something else then intended. Since there is a memcpy directly after it with the full size, drop the memset completely. Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Acked-by: Lukasz Majewski <l.majewski@samsung.com>
generated by cgit v1.1 at 2024-11-01 22:19:37 +0000