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* i2c: mvtwsi: Make delay times frequency-dependentmario.six@gdsys.cc2016-07-26-42/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices using the MVTWSI driver have the option to run at speeds faster than Standard Mode (100kHZ). On the Armada 38x controllers, this is actually necessary, since due to erratum FE-8471889, a timing violation concerning repeated starts prevents the controller from working correctly in Standard Mode. One of the workarounds recommended in the erratum is to set the bus to Fast Mode (400kHZ) operation and ensure all connected devices are set to Fast Mode. In the current version of the driver, however, the delay times are hard-coded to 10ms, corresponding to Standard Mode operation. To take full advantage of the faster modes, we would need to either keep the currently configured I2C speed in a globally accessible variable, or pass it to the necessary functions as a parameter. For DM, the first option is not a problem, and we can simply keep the speed in the private data of the driver. For the legacy interface, however, we would need to introduce a static variable, which would cause problems with boots from NOR flashes; see commit d6b7757 "i2c: mvtwsi: Eliminate twsi_control_flags." As to not clutter the interface with yet another parameter, we therefore keep the default 10ms delays for the legacy functions. In DM mode, we make the delay time dependant on the frequency to allow taking full advantage of faster modes of operation (tested with up to 1MHZ frequency on Armada MV88F6820). Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Handle zero-length offsets properlymario.six@gdsys.cc2016-07-26-8/+13
| | | | | | | | | | | | | Zero-length offsets are not properly handled by the driver. When a read operation with a zero-length offset is started, a START condition is asserted, and since no offset bytes are transferred, a repeated START is issued immediately after, which confuses the controller. To fix this, we send the first START only if any address bytes need to be sent, and keep track of the expected start status accordingly. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Add compatibility to DMmario.six@gdsys.cc2016-07-26-1/+117
| | | | | | | | | | | | | | | | | This patch adds the necessary functions and Kconfig entry to make the MVTWSI I2C driver compatible with the driver model. A possible device tree entry might look like this: i2c@11100 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; clock-frequency = <100000>; u-boot,i2c-slave-addr = <0x0>; }; Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Make address length variablemario.six@gdsys.cc2016-07-26-9/+21
| | | | | | | | | | | | | The length of the address parameter of the __twsi_i2c_read and __twsi_i2c_write functions is fixed to four bytes. As a final step in the preparation of the DM conversion, we make the length of this parameter variable by turning it into an array of bytes, and convert the 32 bit value that's passed to the legacy functions into a four-byte-array on the fly. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Factor out adap parametermario.six@gdsys.cc2016-07-26-51/+46
| | | | | | | | | To be able to use the compatibility layer from the DM functions, we factor the adap parameter out of all functions, and pass the actual register base instead. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Add compatibility functionsmario.six@gdsys.cc2016-07-26-9/+38
| | | | | | | | To prepare for the DM conversion, we add a layer of compatibility functions to be used by both the legacy and the DM functions. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Use 'uint' instead of 'unsigned int'mario.six@gdsys.cc2016-07-26-5/+5
| | | | | | | | | | Since some additional parameters will be added in the course of this patch series (especially with the addition of DM support), we replace the longer "unsigned int" declarations with "uint" declarations to keep the parameter lists more readable. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Get rid of status parametermario.six@gdsys.cc2016-07-26-13/+13
| | | | | | | | | | | | | | | | | | | | The twsi_stop function contains a parameter "status," which is used to pass in the current exit status of the function calling twsi_stop, and either return this status unchanged if it indicates an error, or return twsi_stop's exit status if it does not indicate an error. While not massively complicated, this adds another purpose to the twsi_stop function, which should have the sole purpose of asserting a STOP condition on the bus (and not manage the exit status of its caller). Therefore, we move the exit status management into the caller functions by introducing a "stop_status" variable and returning either the status before the twsi_stop call (kept in the "status" variable), or the status from the twsi_stop call, depending on which indicates an error. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Eliminate flags parametermario.six@gdsys.cc2016-07-26-42/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to breaking boots from NOR flashes, commit d6b7757 ("i2c: mvtwsi: Eliminate twsi_control_flags") removed the static global twsi_control_flags variable, which kept a set of default flags that were always or'd to the control register when writing. It was replaced with a flags parameter, which was passed around between the functions that needed it. Since the twsi_control_flags variable was used just for the purposes of a) setting the MVTWSI_CONTROL_TWSIEN on every control register write, and b) setting the MVTWSI_CONTROL_ACK from twsi_i2c_read if needed, anyway, the added overhead of another variable being passed around is no longer justified, and we are better off implementing this flag setting logic locally in the functions that actually write to the control register. Therefore, this patch sets MVTWSI_CONTROL_TWSIEN on every control register write, replaces the twsi_i2c_read's flags parameter with a ack_flag parameter, which tells the function whether to acknowledge the read or not, and removes every other instance of the flags variable. This has the added benefit that now every notion of "global default flags" is gone, and it's much easier to see which control flags are actually set at which point in time. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Improve and fix commentsmario.six@gdsys.cc2016-07-26-67/+62
| | | | | | | | This patch fixes only comments/documentation: Streamline capitalization and improve grammar/punctuation. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Streamline code and add documentationmario.six@gdsys.cc2016-07-26-38/+75
| | | | | | | | | Convert groups of logically connected preprocessor defines into proper enums, one macro into an inline function, and add documentation to/extend existing documentation of these items. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Fix style violationsmario.six@gdsys.cc2016-07-26-8/+8
| | | | | | | | This patch fixes seven style violations: Six superfluous spaces after casts, and one logical continuation violation. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* drivers: i2c: omap24xx_i2c: adopt omap_i2c driver to driver modelMugunthan V N2016-07-26-0/+99
| | | | | | | Convert omap i2c driver to adopt i2c driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: i2c: omap24xx_i2c: prepare driver for DM conversionMugunthan V N2016-07-26-133/+175
| | | | | | | Prepare the driver for DM conversion. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: i2c: uclass: parse dt parameters only when CONFIG_OF_CONTROL is enableMugunthan V N2016-07-26-0/+14
| | | | | | | | parse dt parameter of i2c devices only when CONFIG_OF_CONTROL is enabled. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mtd: nand: fix bug writing 1 byte less than page sizeHector Palacios2016-07-24-1/+1
| | | | | | | | | | | | | | | | | | nand_do_write_ops() determines if it is writing a partial page with the formula: part_pagewr = (column || writelen < (mtd->writesize - 1)) When 'writelen' is exactly 1 byte less than the NAND page size the formula equates to zero, so the code doesn't process it as a partial write, although it should. As a consequence the function remains in the while(1) loop with 'writelen' becoming 0xffffffff and iterating until the watchdog timeout triggers. To reproduce the issue on a NAND with 2K page (0x800): => nand erase.part <partition> => nand write $loadaddr <partition> 7ff Signed-off-by: Hector Palacios <hector.palacios@digi.com>
* mtd: nand: Add a full-id entry for the H27QCG8T2E5R‐BCF NANDBoris Brezillon2016-07-24-0/+4
| | | | | | | Add a full-id entry for the H27QCG8T2E5R‐BCF NAND. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* mtd: nand: Add the sunxi NAND controller driverBoris Brezillon2016-07-24-3/+1851
| | | | | | | | | | | We already have an SPL driver for the sunxi NAND controller, now add the normal/standard one. The source has been copied from Linux 4.6 with a few changes to make it work in u-boot. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* mtd: nand: add common DT init codeBrian Norris2016-07-24-0/+70
| | | | | | | | | | | | | | | | | These are already-documented common bindings for NAND chips. Let's handle them in nand_base. If NAND controller drivers need to act on this data before bringing up the NAND chip (e.g., fill out ECC callback functions, change HW modes, etc.), then they can do so between calling nand_scan_ident() and nand_scan_tail(). The original commit has been slightly reworked to use the fdtdec_xxx() helpers (instead of the of_xxxx() ones). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* ARM: uniphier: use (devm_)ioremap() instead of map_sysmem()Masahiro Yamada2016-07-24-100/+42
| | | | | | | | This does not have much impact on behavior, but makes code look more more like Linux. The use of devm_ioremap() often helps to delete .remove callbacks entirely. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* mtd: OneNAND: initialize mtd->writebufsize to let UBI workLadislav Michl2016-07-22-0/+1
| | | | | | | io_init checks this value and fails with "bad write buffer size 0 for 2048 min. I/O unit" Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* mtd: OneNAND: allow board init function failLadislav Michl2016-07-22-15/+15
| | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* mtd: OneNAND: add timeout to wait ready loopsLadislav Michl2016-07-22-11/+19
| | | | | | | | Add timeout to onenand_wait ready loop as it hangs here indefinitely when chip not present. Once there, do the same for onenand_bbt_wait as well (note: recent Linux driver code does the same) Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* armv7: make gpmc_cfg constLadislav Michl2016-07-22-1/+2
| | | | | | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org> [trini: Adapt am33xx, duovero, omap_zoom1] Signed-off-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* spl: Lightweight UBI and UBI fastmap supportThomas Gleixner2016-07-22-0/+1170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting a payload out of NAND FLASH from the SPL is a crux today, as it requires hard partioned FLASH. Not a brilliant idea with the reliability of todays NAND FLASH chips. The upstream UBI + UBI fastmap implementation which is about to brought to u-boot is too heavy weight for SPLs as it provides way more functionality than needed for a SPL and does not even fit into the restricted SPL areas which are loaded from the SoC boot ROM. So this provides a fast and lightweight implementation of UBI scanning and UBI fastmap attach. The scan and logical to physical block mapping code is developed from scratch, while the fastmap implementation is lifted from the linux kernel source and stripped down to fit the SPL needs. The text foot print on the board which I used for development is: 6854 0 0 6854 1abd drivers/mtd/ubispl/built-in.o Attaching a NAND chip with 4096 physical eraseblocks (4 blocks are reserved for the SPL) takes: In full scan mode: 1172ms In fastmap mode: 95ms The code requires quite some storage. The largest and unknown part of it is the number of fastmap blocks to read. Therefor the data structure is not put into the BSS. The code requires a pointer to free memory handed in which is initialized by the UBI attach code itself. See doc/README.ubispl for further information on how to use it. This shares the ubi-media.h and crc32 implementation of drivers/mtd/ubi There is no way to share the fastmap code, as UBISPL only utilizes the slightly modified functions ubi_attach_fastmap() and ubi_scan_fastmap() from the original kernel ubi fastmap implementation. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* onenand_spl_simple: Add a simple OneNAND read functionLadislav Michl2016-07-22-0/+48
| | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* nand_spl_simple: Add a simple NAND read functionThomas Gleixner2016-07-22-0/+62
| | | | | | | | | | | To support UBI in SPL we need a simple NAND read function. Add one to nand_spl_simple and keep it as simple as it goes. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Acked-by: Scott Wood <oss@buserror.net> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* mtd: Sort subsystem directories aplhabeticaly in MakefileLadislav Michl2016-07-22-2/+2
| | | | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* i2c_eeprom: Add reading supportmario.six@gdsys.cc2016-07-22-8/+36
| | | | | | | | | | | | | | This patch implements the reading functionality for the generic I2C EEPROM driver, which was just a non-functional stub until now. Since the page size will be of importance for the writing support, we add suitable members to the private data structure to keep track of it. Compatibility strings for a range of at24c* chips are added. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-07-22-29/+36
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| * usb: Kconfig: Add Kconfigs entry USB_EHCI_ZYNQSiva Durga Prasad Paladugu2016-07-22-0/+7
| | | | | | | | | | | | | | | | | | Add Kconfig entry config option for USB_EHCI_ZYNQ and update the same to enable for all zynq boards which supports USB Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * dm: clk: Remove simple version of clk_get_by_index/name()Michal Simek2016-07-22-27/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simple version of clk_get_by_index() added by: "dm: clk: Add a simple version of clk_get_by_index()" (sha1: a4b10c088c4f6ef2e2bba33e8cfea369bcbbce44) is only working for #clock-cells=<1> but not for any other values. Fixed clocks is using #clock-cells=<0> which requires full implementation. Remove simplified versions of clk_get_by_index() and use full version. Also remove empty clk_get_by_name() which is failing when it is called which is useless. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * serial: zynq: Read information about clock from DTMichal Simek2016-07-22-1/+27
| | | | | | | | | | | | | | | | Read information about clock frequency from DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
| * mmc: sdhci: Disable internal clock enable bitSiva Durga Prasad Paladugu2016-07-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | Disable internal clock by clearing the internal clock enable bit. This bit needs to be cleared too when we stop the SDCLK for changing the frequency divisor. This bit should be set to zero when the device is not using the Host controller. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2016-07-21-0/+41
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| * powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPLSumit Garg2016-07-21-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2016-07-21-0/+31
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| * serial_sh: Add standrad SCI (w/o FIFO) supportYoshinori Sato2016-07-09-0/+3
| | | | | | | | | | | | | | Add support for standard type SCI (without FIFO) port. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * serial_sh: Device Tree supportYoshinori Sato2016-07-09-0/+28
| | | | | | | | | | | | | | Add Device Tree bindings. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | mtd: cfi_flash: fix polling for bit XSR.7 on Intel chipsDaniel Schwierzeck2016-07-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flash_full_status_check() checks bit XSR.7 on Intel chips. This should be done by only checking bit 7 and not by comparing the whole status byte or word with 0x80. This fixes the non-working block erase in the pflash emulation of Qemu when used with the MIPS Malta board. MIPS Malta uses x32 mode to access the pflash device. In x32 mode Qemu mirrors the lower 16 bits of the status word into the upper 16 bits. Thus the CFI driver gets a status word of 0x8080 in x32 mode. If flash_full_status_check() uses flash_isequal(), then it polls for XSR.7 by comparing 0x8080 with 0x80 which never becomes true. Reported-by: Alon Bar-Lev <alon.barlev@gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Various, unrelated tree-wide typo fixes.Robert P. J. Day2016-07-16-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-07-15-22/+1100
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| * | sunxi: Use BROM stored boot_media value to determine our boot-sourceHans de Goede2016-07-15-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we know that the BROM stores a value indicating the boot-source at the beginning of SRAM, use that instead of trying to recreate the BROM's boot probing. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | net: Add EMAC driver for H3/A83T/A64 SoCs.Amit Singh Tomar2016-07-15-0/+799
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: mmc: increase status register polling rate for data transfersTobias Doerffel2016-07-15-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With a recent bunch of SD3.0 cards in our A20-based board we experienced data transfer rates of about 250 KiB/s instead of 10 MiB/s with previous cards from the same vendor (both 4 GB/class 10). By increasing status register polling rate from 1 kHz to 1 MHz we were able to reach the original transfer rates again. With the old cards we now even reach about 16 MiB/s. Signed-off-by: Tobias Doerffel <tobias.doerffel@ed-chemnitz.de> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Support booting from SPI flashSiarhei Siamashka2016-07-15-0/+296
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner devices support SPI flash as one of the possible bootable media type. The SPI flash chip needs to be connected to SPI0 pins (port C) to make this work. More information is available at: https://linux-sunxi.org/Bootable_SPI_flash This patch adds the initial support for booting from SPI flash. The existing SPI frameworks are not used in order to reduce the SPL code size. Right now the SPL size grows by ~370 bytes when CONFIG_SPL_SPI_SUNXI option is enabled. While there are no popular Allwinner devices with SPI flash at the moment, testing can be done using a SPI flash module (it can be bought for ~2$ on ebay) and jumper wires with the boards, which expose relevant pins on the expansion header. The SPI flash chips themselves are very cheap (some prices are even listed as low as 4 cents) and should not cost much if somebody decides to design a development board with an SPI flash chip soldered on the PCB. Another nice feature of the SPI flash is that it can be safely accessed in a device-independent way (since we know that the boot ROM is already probing these pins during the boot time). And if, for example, Olimex boards opted to use SPI flash instead of EEPROM, then they would have been able to have U-Boot installed in the SPI flash now and boot the rest of the system from the SATA hard drive. Hopefully we may see new interesting Allwinner based development boards in the future, now that the software support for the SPI flash is in a better shape :-) Testing can be done by enabling the CONFIG_SPL_SPI_SUNXI option in a board defconfig, then building U-Boot and finally flashing the resulting u-boot-sunxi-with-spl.bin binary over USB OTG with a help of the sunxi-fel tool: sunxi-fel spiflash-write 0 u-boot-sunxi-with-spl.bin The device needs to be switched into FEL (USB recovery) mode first. The most suitable boards for testing are Orange Pi PC and Pine64. Because these boards are cheap, have no built-in NAND/eMMC and expose SPI0 pins on the Raspberry Pi compatible expansion header. The A13-OLinuXino-Micro board also can be used. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2016-07-15-63/+85
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| * | | mmc: exynos_dw_mmc: support the Driver mode for ExynosJaehoon Chung2016-07-12-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch support the driver mode for exynos dwmmc controller. To support the legacy model, maintained the existing code. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | mmc: exynos_dw_mmc: use the 4bit bus-width by defaultJaehoon Chung2016-07-12-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If there is not "samsung,bus-width" property, use the 4bit buswidth by default. Almost all Exnyos SoCs support at least 4bit buswidth. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | mmc: exynos_dw_mmc: clean the unused and unnecessary codesJaehoon Chung2016-07-12-22/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean the unused and unnecessary codse. This patch is one of them for preparing to use DM. Because it's easy to maintain and combine DM after cleaning codes. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
generated by cgit v1.1 at 2024-12-28 00:23:20 +0000