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* | Merge branch 'master' of http://git.denx.de/u-boot-sparcTom Rini2015-12-04-1/+1
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| * | sparc: Use microseconds instead of ticks for timeoutFrancois Retief2015-12-03-1/+1
| | | | | | | | | | | | | | | | | | | | | We now use the generic delay method which specifies the timeout as microseconds instead of ticks. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-12-04-3/+1
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| * video: ipu: simplify if else codePeng Fan2015-11-25-3/+1
| | | | | | | | | | | | | | | | | | | | Simplify if/else code, since if channel equals to MEM_BG_SYNC or MEM_FG_SYNC, we have value 5 for 'dc_chan'. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* | rockchip: mmc: get the fifo mode and fifo depth property from dtshuang lin2015-12-01-4/+17
| | | | | | | | | | | | | | | | rk3036 mmc do not have internal dma, so we use fifo mode when read and write data, we get the fifo mode and fifo depth property from dts, pass to dw_mmc driver. Signed-off-by: Lin Huang <hl@rock-chips.com>
* | rockchip: mmc: use non-removable property to distinguish emmc and sdcard ↵huang lin2015-12-01-2/+3
| | | | | | | | | | | | | | | | | | | | register emmc and sdcard have different register address, use non-removeable property to distinguish them. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | mmc: dw_mmc: support fifo mode in dwc mmc driverhuang lin2015-12-01-18/+67
| | | | | | | | | | | | | | | | some soc(rk3036 etc) use dw_mmc but do not have internal dma, so we implement fifo mode to read and write data. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | mmc: dw_mmc: move data transfer as a separate functionhuang lin2015-12-01-28/+37
| | | | | | | | | | | | | | | | the data transfer seem to long in the dwmci_send_cmd function, so move this block as a separate funciton. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3036: Add pinctrl driverhuang lin2015-12-01-0/+286
| | | | | | | | | | | | | | Add a driver which support pin multiplexing setup for rk3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3036: Add clock driverhuang lin2015-12-01-0/+415
| | | | | | | | | | | | | | | | Add a driver for setting up and modifying the various PLLs, peripheral clocks and mmc clocks on RK3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: serial driver support rk3036huang lin2015-12-01-0/+1
| | | | | | | | | | Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | dm: core: Add SPL Kconfig for REGMAP and SYSCONhuang lin2015-12-01-2/+21
| | | | | | | | | | | | | | | | Add SPL Kconfig for REGMAP and SYSCON, so REGMAP and SYSCON can remove from SPL stage. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | dm: pci: Disable PCI compatibility functions by defaultSimon Glass2015-12-01-1/+11
| | | | | | | | | | | | | | | | | | We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: pci: Move common auto-config functions to a common fileSimon Glass2015-12-01-117/+129
| | | | | | | | | | | | | | | | Some functions will be used by driver model and legacy PCI code. To avoid duplication, put these in a separate, shared file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: pci: Rename pci_auto.c to pci_auto_old.cSimon Glass2015-12-01-1/+1
| | | | | | | | | | | | | | | | This file should not be used with driver model as it has lots of legacy/ compatibility functions. Rename it to make this clear. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: tegra: pci: Convert tegra boards to driver model for PCISimon Glass2015-12-01-322/+155
| | | | | | | | | | | | | | | | | | Adjust the Tegra PCI driver to support driver model and move all boards over at the same time. This can make use of some generic driver model code, such as the range-decoding logic. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* | dm: pci: Add a function to find the regions for a PCI busSimon Glass2015-12-01-0/+30
| | | | | | | | | | | | | | | | | | This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* | dm: pci: Add a function to get the controller for a busSimon Glass2015-12-01-0/+8
| | | | | | | | | | | | | | | | | | A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* | dm: pci: Add functions to emulate 8- and 16-bit accessSimon Glass2015-12-01-0/+39
| | | | | | | | | | | | | | | | | | Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* | dm: pci: Support decoding ranges with duplicate entriesSimon Glass2015-12-01-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present we add a new resource entry for every range entry. But some range entries refer to configuration regions. To make this work, avoid adding two regions of the same type. The later ranges will overwrite the earlier (configuration) ones. There does not seem to be a way to distinguish the configuration ranges other than by ordering (as per the device tree binding). We could perhaps instead just store one region of each type in a simple array. Once we are sure that we don't need to support multiple regions, we could change this. It would be easier to do it when all drivers are converted to use driver model for PCI. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* | dm: pci: Set up the SDRAM mapping correctlySimon Glass2015-12-01-6/+9
| | | | | | | | | | | | | | | | | | | | SDRAM doesn't always start at 0. Adjust the region mapping so that it works on platforms where SDRAM is somewhere else. This needs testing on other platforms. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* | dm: tegra: pci: Move CONFIG_PCI_TEGRA to KconfigSimon Glass2015-12-01-0/+10
| | | | | | | | | | | | | | Move this option to Kconfig and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* | x86: tsc: Move tsc_timer.c to drivers/timerBin Meng2015-12-01-0/+397
| | | | | | | | | | | | | | | | To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | dm: timer: Support 64-bit counterBin Meng2015-12-01-6/+15
| | | | | | | | | | | | | | | | | | | | | | | | There are timers with a 64-bit counter value but current timer uclass driver assumes a 32-bit one. Modify timer_get_count() to ask timer driver to always return a 64-bit counter value, and provide an inline helper function timer_conv_64() to handle the 32-bit/64-bit conversion automatically. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | timer: sandbox: Use device tree to pass the clock frequencyBin Meng2015-12-01-4/+0
| | | | | | | | | | | | | | | | We should use device tree to pass the clock frequency of the timer instead of hardcoded in the driver codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | timer: altera: Remove the codes to get clock frequencyBin Meng2015-12-01-6/+0
| | | | | | | | | | | | | | | | | | Since we have timer uclass to get clock frequency for us, remove the custom version in the altera timer driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
* | dm: timer: Implement pre_probe()Bin Meng2015-12-01-0/+13
| | | | | | | | | | | | | | | | | | | | Every timer device needs to have a valid clock frequency and it can be specified in the device tree. Use pre_probe() to get this in the timer uclass driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
* | dm: timer: Fix several nitsBin Meng2015-12-01-8/+8
| | | | | | | | | | | | | | | | This changes 'Timer' to 'timer' at several places. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-11-30-0/+308
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| * | gpio: atmel: Add the PIO4 driver supportWenyou Yang2015-11-30-0/+308
| | | | | | | | | | | | | | | | | | | | | The PIO4 is introduced from SAMA5D2, as a new version for Atmel PIO controller. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-11-30-285/+1357
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| * | | net: phy: added aquantia PHY AQR405 supportShaohui Xie2015-11-30-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The phy can share driver with other aquantia PHYs, so we only add PHY ID. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | drivers/ddr/fsl: Fix typo in BIST test for DDR4York Sun2015-11-30-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BIST test code has a typo, resulting the binding registers not maintained as expected. This typo results BIST runs twice on the covered memory. Signed-off-by: York Sun <yorksun@freescale.com> Reported-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
| * | | drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3York Sun2015-11-30-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale LSCH3 platforms use two DDR controlers interleaving mode out of reset. It can be configured to disable one controller. To support this operation, the driver needs to detect and skip the disabled controller. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | pci/layerscape: add support for LS1043A PCIe LUT register accessMingkai Hu2015-11-30-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | armv8: ls2085a: Add support of LS2085A SoCPrabhakar Kushwaha2015-11-30-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's LS2085A is a another personality of LS2080A SoC with support of AIOP and DP-DDR. This Patch adds support of LS2085A Personality. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Updated MAINTAINERS files Dropped #ifdef in cpu.h Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun <yorksun@freescale.com>
| * | | armv8: LS2080A: Rename LS2085A to reflect LS2080APrabhakar Kushwaha2015-11-30-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver: net: ldpaa: Fix Rx buffer alignmentPrabhakar Kushwaha2015-11-30-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MC 0.7.1.2 enforces limitation i.e.: "Packets may be corrupted in several combinations of buffer size and frame offsets. Workaround: Use buffers that are of size that is a multiple of 256, and frame offset that is a multiple of 256" Updating the DPNI Eth driver to comply with the restriction. Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver: net: ldpaa: Add debug informationPrabhakar Kushwaha2015-11-30-0/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add following debug information in the driver - Get various DPNI counter values - Get link status of DPNI objects - Get information of both ends of connection (DPMAC - DPNI) Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver: net: ldpaa: Use DPMAC as net devicePrabhakar Kushwaha2015-11-30-44/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per current implementation of DPAA2 ethernet driver DPNI is used as net device. DPNI is tangible objects can be multiple connected to same physical lane. Use DPMAC as net device where it represents physical lane. Below modification done in driver - Use global DPNI object - Connect DPMAC to DPNI - Create and destroy DPMAC Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver: net: fsl-mc: Create DPAA2 object at run-timePrabhakar Kushwaha2015-11-30-36/+435
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's DPAA2 ethernet driver depends upon the static DPL for the DPRC, DPNI, DPBP, DPIO objects. Instead of static objects, Create DPNI, DPBP, DPIO objects at run-time. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver: net: fsl-mc: Add DPAA2 commands to manage MCPrabhakar Kushwaha2015-11-30-198/+184
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Management complex Firmware, DPL and DPC are depolyed during u-boot boot sequence. Add new DPAA2 commands to manage Management Complex (MC) i.e. start mc, aiop and apply DPL from u-boot command prompt. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver: net: fsl-mc: Increase MC command timeoutPrabhakar Kushwaha2015-11-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dpni_create API take takes more time as comapred to existing supported APIs of MC Flib. So increase MC command timeout. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver: ldpaa: Add api to return linked PHY ID of DPMACPrabhakar Kushwaha2015-11-30-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DPMAC represents physical line on the board. This physical line eventually asscociate with on-board PHY. So Add an api to return linked PHY ID of DPMAC object. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver: net: fsl-mc: Add APIs for DPMAC objects in FLIBPrabhakar Kushwaha2015-11-30-1/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DPMAC object of Management complex controls Physical MAC and MDIO controller. It provides APIs for MDIO and link state updates. It also provides APIs for PHY/link configuration. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver: net: fsl-mc: Add create, destroy APIs in flibsPrabhakar Kushwaha2015-11-30-0/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current Management Complex Flibs does not support APIs for adding and destroying the objects. Add APIs to create and destroy objects for DPBP, DPIO, DPNI and DPRC. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | armv8: lsch3: Fix lane protocol parsing logicPrabhakar Kushwaha2015-11-30-8/+7
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | Current implementation only consider SGMIIs for dpmac initialization. XFI serdes protocols also uses dpmac. Also, fix lane protocol parsing logic to consider both XFIs and SGMIIs. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge git://git.denx.de/u-boot-socfpgaTom Rini2015-11-30-8/+21
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| * | | mmc: socfpga_dw_mmc: Move drvsel and smplsel to dtsChin Liang See2015-11-30-8/+21
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | socfpga_dw_mmc driver will obtain the drvsel and smplsel value from device tree instead of definition in config header file. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Marek Vasut <marex@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2015-11-30-1/+2
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