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* power: axp818: Fix typo for fldo2 Kconfig descriptionChen-Yu Tsai2016-05-25-1/+1
| | | | | | | | | Description said eldo2 instead of fldo2, a copy-paste error. Fixes: 38491d9c6515 ("power: axp818: Add support for FLDOs") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* power: axp221: Remove switch case to simplify axp_set_eldoChen-Yu Tsai2016-05-25-20/+7
| | | | | | | | | | The ELDO enable bits and registers are contiguous for axp221. Instead of a switch case testing against the index, just use the index to shift the bit or register offset. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-05-24-156/+381
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| * driver/ddr/fsl: Add workaround for erratum A-010165Shengzhou Liu2016-05-18-1/+9
| | | | | | | | | | | | | | | | | | During DDR-2133 operation, the transmit data eye margins determined during the memory controller initialization may be sub-optimal, set DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * crypto/fsl: add support for multiple SEC engines initializationAlex Porosanu2016-05-18-115/+159
| | | | | | | | | | | | | | | | | | For SoCs that contain multiple SEC engines, each of them needs to be initialized (by means of initializing among others the random number generator). Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * sf: Disable 4-KB erase command for SPANSION S25FS-S familyYuan Yao2016-05-18-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The S25FS-S family physical sectors may be configured as a hybrid combination of eight 4-kB parameter sectors at the top or bottom of the address space with all but one of the remaining sectors being uniform size. The default status of the flash is in this hybrid architecture. The parameter sectors and the uniform sectors have different erase commands. This patch disable the hybrid sector architecture then the flash will has uniform sector size and uniform erase command. This configuration is temporary, the flash will revert to hybrid architecture after power on reset. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * spi: fsl_qspi: Enable Spansion S25FS-S family flashesYuan Yao2016-05-18-6/+57
| | | | | | | | | | | | | | | | | | | | The flash type of LS2085AQDS QSPI is S25FS256S. It has special write any device register command and read any device register command. This patch enable support for those commands. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * spi: fsl_qspi: Assign AMBA mem according CS num in dtsYuan Yao2016-05-18-12/+43
| | | | | | | | | | | | | | | | | | | | | | QSPI controller automatic enable the chipselect signal according the dest AMBA memory address. Now we distribute the AMBA memory zone averagely to every chipselect slave device according chipselect numbers got from dts node. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * spi: fsl_qspi: Fix issues on arm64Yuan Yao2016-05-18-19/+27
| | | | | | | | | | | | | | | | | | | | | | The address value and size value get from dts "reg" property have type of u64 on arm64. If we assign those values to "u32" variables, driver can't work correctly. Converting the type of those variables to fdt_xxx_t. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Add workaround for erratum A-009801Shengzhou Liu2016-05-17-0/+7
| | | | | | | | | | | | | | | | The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * drivers/ddr/fsl: update workaround for erratum A-008511Shengzhou Liu2016-05-17-3/+7
| | | | | | | | | | | | | | | | Per the latest erratum document, update step 4 and step 8, only DEBUG_29[21] is changed, all other bits should not be changed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-05-24-530/+1172
|\ \ | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: drivers/net/zynq_gem.c
| * | net: phy: dp83867: Add SGMII helper for configurationDan Murphy2016-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code assumed that if the interface is not RGMII configured then it must be SGMII configured. This device has the ability to support most of the MII interfaces. Therefore add the helper for SGMII and only configure the device if the interface is configured for SGMII. Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: Move is_rgmii helper to phy.hDan Murphy2016-05-24-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the phy_interface_is_rgmii to the phy.h file for all phy's to be able to use the API. This now aligns with the Linux kernel based on commit e463d88c36d42211aa72ed76d32fb8bf37820ef1 Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: ti: Allow the driver to be more configurableDan Murphy2016-05-24-10/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all devices use the same internal delay or fifo depth. Add the ability to set the internal delay for rx or tx and the fifo depth via the devicetree. If the value is not set in the devicetree then set the delay to the default. If devicetree is not used then use the default defines within the driver. Signed-off-by: Dan Murphy <dmurphy@ti.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: zynq_gem: Add the passing of the phy-handle nodeDan Murphy2016-05-24-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the ability to pass the phy-handle node offset to the phy driver. This allows the phy driver to access the DT subnode's data and parse accordingly. Signed-off-by: Dan Murphy <dmurphy@ti.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers: net: cpsw: Add reading of DT phy-handle nodeDan Murphy2016-05-24-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the ability to read the phy-handle node of the cpsw slave. Upon reading this handle the phy-id can be stored based on the reg node in the DT. The phy-handle also needs to be stored and passed to the phy to access any phy data that is available. Signed-off-by: Dan Murphy <dmurphy@ti.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers: net: cpsw: add support for reading mac address from efuseMugunthan V N2016-05-24-17/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Different TI platforms has to read with different combination to get the mac address from efuse. So add support to read mac address based on machine/device compatibles. The code is taken from Linux drivers/net/ethernet/ti/cpsw-common.c done by Tony Lindgren. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers: net: cpsw: fix get mdio base and gmii_sel reg from DTMugunthan V N2016-05-24-4/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since dra7x platforms address bus is define as 64 bits to support LAPE, fdtdec_get_addr() returns a invalid address for mdio based and gmii_sel register address. Fixing this by using fdtdec_get_addr_size_auto_noparent() which will derive address cell and size cell from its parent. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers: net: cpsw: fix cpsw dp parse when num slaves as 1Mugunthan V N2016-05-24-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some boards number of slaves can be 1 when only one port ethernet is pinned out. So do not break when slave_index and num slaves check fails, instead continue to parse the next child. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers: core: device: add support to check dt compatible for a device/machineMugunthan V N2016-05-24-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide an api to check whether the given device or machine is compatible with the given compat string which helps in making decisions in drivers based on device or machine compatible. Idea taken from Linux. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: Add PHY driver for mv88e61xx switchesKevin Smith2016-05-24-0/+1020
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous mv88e61xx driver was a driver for configuring the switch, but did not integrate with the PHY/networking system, so it could not be used as a PHY by U-boot. This is a complete rework to support this device as a PHY. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: Remove unused mv88e61xx switch driverKevin Smith2016-05-24-598/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No boards are using this driver. Remove in preparation for a new driver with integrated PHY support. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-05-24-73/+152
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| * | | phy: marvell: Do not reset phy after negotiationMichal Simek2016-05-24-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch "net: phy: do not read configuration register on reset" (sha1: a058052c358c3ecf5f394ff37def6a45eb26768c) was causing regression on zynq zc702 board where Marwell 88e1118 phy was resetted after negotiation was setup. Phy reset is done pretty early in phy_connect_dev() and doens't need to be called again in phy code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | phy: Wire return value from phy_config()Michal Simek2016-05-24-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | Fix zynq_gem driver to handle error from phy_config correctly. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | net: phy: Handle phy_startup() error codes properlyMichal Simek2016-05-24-56/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Propagate error code from genphy_update_link() to phy startup(). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | | phy: Return correct error code when timeout happensMichal Simek2016-05-24-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Return -ETIMEDOUT if timeout happens. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | | net: xilinx: Handle error value from phy_startup()Michal Simek2016-05-24-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Handle error returned by phy_startup() properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | | fpga: Fix typo in function commentMichal Simek2016-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Trivial patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | gpio: zynq: Add support for reading gpio pin stateMichal Simek2016-05-24-0/+22
| |/ / | | | | | | | | | | | | | | | | | | Add zynq_gpio_get_function() which return status on gpio pin. This function enables gpio status command. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-05-23-0/+393
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| * | cmd: qfw: bring ACPI generation code into qfw coreMiao Yan2016-05-23-0/+206
| | | | | | | | | | | | | | | | | | | | | | | | Loading ACPI table from QEMU's fw_cfg interface is not x86 specific (ARM64 may also make use of it). So move the code to common place. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h]Miao Yan2016-05-23-3/+3
| | | | | | | | | | | | | | | | | | | | | Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: qemu: move x86 specific operations out of qfw coreMiao Yan2016-05-23-17/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original implementation of qfw includes several x86 specific operations, like directly calling outb/inb and using some inline assembly code which prevents it being ported to other architectures. This patch adds callback functions and moves those to arch/x86/ Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: qemu: split qfw command interface and qfw coreMiao Yan2016-05-23-0/+191
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch splits qfw command interface and qfw core function into two files, and introduces a new Kconfig option (CONFIG_QFW) for qfw core. Now when qfw command interface is enabled, it will automatically select qfw core. This patch also makes the ACPI table generation select CONFIG_QFW. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-05-23-0/+1269
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| * | | ar933x: serial: Remove the explicit pinctrl settingWills Wang2016-05-21-14/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The correct pinctrl is handled automatically so we don't need to do it in the driver. Signed-off-by: Wills Wang <wills.wang@live.com>
| * | | ath79: spi: Remove the explicit pinctrl settingWills Wang2016-05-21-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The correct pinctrl is handled automatically so we don't need to do it in the driver. Signed-off-by: Wills Wang <wills.wang@live.com>
| * | | drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.Purna Chandra Mandal2016-05-21-0/+452
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PIC32 internal flash devices are parallel NOR flash divided into number of banks to allow erase-programming in one while fetch and execution continues on other. As the flash banks are memory mapped stored code can be executed directly from flash (XIP), also there is additional hardware logic to prefetch and cache contents to improve execution performance. These flash can also be used to store user data (like environment). Flash erase and programming are handled by on-chip NVM controller. Driver implemented driver model but MTD is not really support. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | drivers: spi: add spi support for QCA/Atheros ath79 SOCsWills Wang2016-05-21-0/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add a compatible spi driver for ath79 series SOC. Signed-off-by: Wills Wang <wills.wang@live.com> Reviewed-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | drivers: serial: add serial driver for ar933x SOCWills Wang2016-05-21-0/+274
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add support for ar933x serial. Signed-off-by: Wills Wang <wills.wang@live.com> Reviewed-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | drivers: pinctrl: Add simple pinctrl driver for Qualcomm/Atheros qca953x.Wills Wang2016-05-21-0/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a simple pinctrl driver, it just support uart and spi pin-mux now. Signed-off-by: Wills Wang <wills.wang@live.com> Reviewed-by: Simon Glass <sjg@chromium.org> [fixed typo in commit subject line] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | drivers: pinctrl: Add simple pinctrl driver for Qualcomm/Atheros ar933x.Wills Wang2016-05-21-0/+151
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | This is a simple pinctrl driver, it just support uart and spi pin-mux now. Signed-off-by: Wills Wang <wills.wang@live.com> Reviewed-by: Simon Glass <sjg@chromium.org> [fixed typo in commit subject line] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | omap3: Fix SPI registers on am33xx and am43xxMartin Hejnfelt2016-05-23-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the base registers are read from device tree the base is not 0x48030100 as the driver expects, but 0x48030000, resulting in non functioning SPI. To deal with this, use same idea as how this is done in the linux kernel (drivers/spi/spi-omap2-mcspi.c) and add a structure with a field that is used to shift the registers on these systems. v2: Fixed commit subject line to correct cpu Signed-off-by: Martin Hejnfelt <mh@newtec.dk>
* | | arm: mvebu: a38x: Weed out floating point useMarek Vasut2016-05-20-19/+10
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For reason unknown, recently, the DDR init code writers are really fond of hiding some small floating point operating deep in their creations. This patch removes one from the Marvell A38x code. Instead of returning size of chip as float from ddr3_get_device_size() in GiB units, return it as int in MiB units. Since this would interfere with the huge switch code in ddr3_calc_mem_cs_size(), rework the code to match the change. Before this patch, the cs_mem_size variable could have these values: ( { 16, 32 } x { 8, 16 } x { 0.01, 0.5, 1, 2, 4, 8 } ) / 8 = { 0.000000, 0.001250, 0.002500, 0.005000, 0.062500, 0.125000, 0.250000, 0.500000, 1.000000, 2.000000, 4.000000, } The switch code checked for a subset of the resulting RAM sizes, which is in range 128 MiB ... 2048 MiB. With this patch, the cs_mem_size variable can have these values: ( { 16, 32 } x { 8, 16 } x { 0, 512, 1024, 2048, 4096, 8192 } ) / 8 = { 0, 64, 128, 256, 512, 1024, 2048, 4096 } To retain previous behavior, filter out 0 MiB (invalid size), 64 MiB and 4096 MiB options. Removing the floating point stuff also saves 1.5k from text segment: clearfog : spl/u-boot-spl:all -1592 spl/u-boot-spl:text -1592 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-05-17-339/+2338
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| * | dm: mmc: sandbox: Add an SD-card emulationSimon Glass2016-05-17-2/+143
| | | | | | | | | | | | | | | | | | | | | | | | Add an emulation of an SD card to sandbox, allowing MMC to be used in tests. The emulation is very simple, supporting only card detection and reading test data. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: mmc: Add support for driver-model block devicesSimon Glass2016-05-17-12/+54
| | | | | | | | | | | | | | | | | | | | | Add support for enabling CONFIG_BLK with MMC. This involves changing a few functions to use struct udevice and adding a MMC block device driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: mmc: Add a way to bind MMC devices with driver modelSimon Glass2016-05-17-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Binding an MMC device when CONFIG_BLK is enabled requires that a block device be bound as a child of the MMC device. Add a function to do this. The mmc_create() method will be used only when DM_BLK is disabled. Add an unbind method also. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-12-28 18:17:54 +0000