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* | | | usb: gadget: allow ci_udc to build with new gadget frameworkStephen Warren2014-05-01-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow ci_udc.o to be built when using the new(?) USB gadget framework, as enabled by CONFIG_USB_GADGET. Note that this duplicates the Makefile entry for ci_udc.o, since it's also included inside #ifdef CONFIG_USB_ETHER. I'm not sure what that define means; perhaps an old style of Ethernet-specific USB gadget implementation? I wonder if the line that this patch adds shouldn't be outside all of the ifdefs, so it stands on its own, similar to how e.g. epautoconf.o is shared between the two? Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | usb: ums: use only 1 buffer for CI_UDCStephen Warren2014-04-30-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ci_udc.c allocates only a single buffer for each endpoint, which ci_ep_alloc_request() returns as a hard-coded value rather than dynamically allocating. Consequently, storage_common.c must limit itself to using a single buffer at a time. Add a special case to the definition of FSG_NUM_BUFFERS for this. Another option would be to fix ci_ep_alloc_request() to dynamically allocate the buffers like some/all(?) other device mode drivers do. However, I don't think that ci_ep_queue() supports queueing up multiple buffers either yet, and I'm not familiar enough with the controller yet to implement that. As such, any attempt to use multiple buffers simply results in data corruption and other errors. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | usb: ci_udc: support variants with hostpc registerStephen Warren2014-04-30-18/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's USB controller appears to be a variant of the ChipIdea controller; perhaps derived from it, or simply a different version of the IP core to what U-Boot supports today. In this variant, at least the following difference are present: - Some registers are moved about. - Setup transaction completion is reported in a separate 'epsetupstat' register, rather than in 'epstat' (which still exists, perhaps for other transaction types). - USB connection speed is reported in a separate 'hostpc1_devlc' register, rather than 'portsc'. - The registers used by ci_udc.c begin at offset 0x130 from the USB register base, rather than offset 0x140. However, this is handled by the associated EHCI controller driver, since the register address is stored in controller.ctrl->hcor. Introduce define CONFIG_CI_UDC_HAS_HOSTPC to indicate which variant of the controller should be supported. The "HAS_HOSTPC" part of this name mirrors the similar "has_hostpc" field used by the Linux EHCI controller core to represent the presence/absence of the hostpc1_devlc register. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | usb: ci_udc: make PHY initialization conditionalStephen Warren2014-04-30-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | usb_gadget_register_driver() currently unconditionally programs PORTSC to select a ULPI PHY. This is incorrect on at least the Tegra boards I am testing with, which use a UTMI PHY for the OTG ports. Make the PHY selection code conditional upon the specific EHCI controller that is in use. Ideally, I believe that the PHY initialization code should be part of ehci_hcd_init() in the relevant EHCI controller driver, or some board- specific function that ehci_hcd_init() calls. For MX6, I'm not sure this PHY initialization code is correct even before this patch, since ehci-mx6's ehci_hcd_init() already configures PORTSC to a board-specific value, and it seems likely that the code in ci_udc.c is incorrectly undoing this. Perhaps this is not an issue if the PHY selection register bits aren't implemented on this instance of the MX6 USB controller? ehci-mxs.c doens't appear to touch PORTSC, so this code is likely still required there. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | usb: ci_udc: set ep->req.actual after transferStephen Warren2014-04-30-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At least drivers/usb/gadget/storage_common.c expects that ep->req.actual contain the number of bytes actually transferred. (At least in practice, I observed it failing to work correctly unless this was the case). However, ci_udc.c modifies ep->req.length instead. I assume that .length is supposed to represent the allocated buffer size, whereas .actual is supposed to represent the actual number of bytes transferred. In the OUT transaction case, this may happen simply because the host sends a smaller packet than the max possible size, which is quite legal. In the IN case, transferring fewer bytes than requested could presumably happen as an error. Modify handle_ep_complete() to write to .actual rather than modifying .length. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | usb: ci_udc: Support larger packetsStephen Warren2014-04-30-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ci_ep_queue() currently only fills in the page0/page1 fields in the queue item. If the buffer is larger than 4KiB (unaligned) or 8KiB (page-aligned), then this prevents the HW from knowing where to write the balance of the data. Fix this by initializing all 5 pageN pointers, which allows up to 16KiB (potentially non-page-aligned) buffers. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | dfu:fix: Replace wrong return value with proper oneLukasz Majewski2014-04-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch remove always false (since we tested ret = 0) ternary operator with ret value returned. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
* | | | exynos: usb: Fix data abort on boards w/o vbus-gpio node in the DTandrey.konovalov@linaro.org2014-04-30-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4a271cb1b4ff doesn't take into account that fdtdec_setup_gpio() returns success when the gpio passed to it is FDT_GPIO_NONE (no gpio node found in the fdtdec_decode_gpio() call). This results in calling gpio_direction_output() on invalid gpio. For this reason executing "usb start" command on Arndale causes data abort in the ehci-exynos driver. Add the fdt_gpio_isvalid() check to fix that problem. Signed-off-by: Andrey Konovalov <andrey.konovalov@linaro.org> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | | | usb: musb: fill in usb_gadget_unregister_driverRob Herring2014-04-30-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing missing disconnect and unbind calls to the musb gadget driver's usb_gadget_unregister_driver function. Otherwise, any gadget drivers fail to uninitialize and run a 2nd time. Signed-off-by: Rob Herring <robh@kernel.org>
* | | | usb: handle NULL table in usb_gadget_get_stringRob Herring2014-04-30-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow a NULL table to be passed to usb_gadget_get_string for cases when a string table may not be populated. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com>
* | | | usb:gadget:f_thor: fix write to filesystem by add dfu_flush()Przemyslaw Marczak2014-04-30-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since dfu read/write operations needs to be flushed manually, writing to filesystem on MMC by thor was broken. MMC raw write actually is working fine because current dfu_flush() function writes filesystem only. This commit adds dfu_flush() to f_thor and now filesystem write is working. This change was tested on Trats2 board. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
* | | | usb:gadget:f_thor: code cleanup in function download_tail()Przemyslaw Marczak2014-04-30-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In thor's download_tail() function, dfu_get_entity() is called before each dfu_write() call and the returned entity pointers are the same. So dfu_get_entity() can be called just once and this patch changes this. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
* | | | usb: Add endian support macros to interrupt transfers in the EHCI driver.Adrian Cox2014-04-30-25/+31
| | | | | | | | | | | | | | | | | | | | | | | | Update the EHCI driver to support interrupt transfers on PowerPC. Signed-off-by: Adrian Cox <adrian@humboldt.co.uk>
* | | | usb: ehci: rmobile: Add support ehci host driver of rmobile SoCsNobuhiro Iwamatsu2014-04-30-0/+131
|/ / / | | | | | | | | | | | | | | | | | | | | | The rmobile SoC has usb host controller. This supports USB controllers listed in the R8A7790, R8A7791 and R8A7740. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Reviewed-by: Marek Vasut <marex@denx.de>
* | | drivers/i2c/fsl_i2c: modify i2c_read to handle multi-byte writeShaveta Leekha2014-04-29-7/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the I2C slaves support accesses in the typical style that is : read/write series of bytes at particular address offset. These transactions look like:" (1) START:Address:Tx:Offset:RESTART:Address[0..4]:Tx/Rx:data[0..n]:STOP" However there are certain devices which support accesses in terms of the transactions as follows: (2) "START:Address:Tx:Txdata[0..n1]:Clock_stretching: RESTART:Address:Rx:data[0..n2]" Here Txdata is typically a command and some associated data, similarly Rxdata could be command status plus some data received as a response to the command sent. Type (1) transactions are currently supportd in the i2c driver using i2c_read and i2c_write APIs. I2C EEPROMs, RTC, etc fall in this category. To handle type (2) along with type (1) transactions, i2c_read() function has been modified. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
* | | driver/mxc_i2c: Move static data structure to global_dataYork Sun2014-04-29-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | This driver needs a data structure in SRAM before SDRAM is available. This is not alway the case using .data section. Moving this data structure to global_data guarantees it is writable. Signed-off-by: York Sun <yorksun@freescale.com> CC: Troy Kisky <troy.kisky@boundarydevices.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-04-25-357/+2139
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| * | | ar8031: modify the config func of ar8031 to ar8021_configZhao Qiang2014-04-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ar8031 has the same config steps with ar8021, so change its config func to ar8021_config instead of genphy_config. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver: Add support of image load for MMC & SPI in SPLPrabhakar Kushwaha2014-04-22-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of loading image, binary for MMC and SPI during SPL boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver/mtd/spi:Read 8KB data chunk during u-boot load in SPLPrabhakar Kushwaha2014-04-22-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI driver perform its operation(read/write) on 64KB buffer chunk for data greater than 64KB. This buffer chunk is allocated from system heap. During SPL boot, 768KB of data is read from SPI flash. Here, heap size may not be sufficient enough to full-fill 64KB buffer requirement of SPI driver. So break down u-boot read operation at 8KB of chunk. Also, fix a warning i.e. "unused variable buf" during CONFIG_FSL_CORENET Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver/ifc: define nand_spl_load_image() for SPLPrabhakar Kushwaha2014-04-22-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | nand_spl_load_image() can also be used for non TPL framework. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | mpc85xx/t104x: Add deep sleep framework supportTang Yuantian2014-04-22-4/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When T104x soc wakes up from deep sleep, control is passed to the primary core that starts executing uboot. After re-initialized some IP blocks, like DDRC, kernel will take responsibility to continue to restore environment it leaves before. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | drivers/ddr: Fix possible out of bounds errorYork Sun2014-04-22-58/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a theoretical possible out of bounds error in DDR driver. Adding check before using array index. Also change some runtime conditions to pre-compiling conditions. Signed-off-by: York Sun <yorksun@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver/net/fm/memac_phy: Initialize mdio_clock for SoCs wih FMANv3Priyanka Jain2014-04-22-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MDIO clock needs to be initialized in u-boot code for SoCs having FMAN-v3(v3H or v3L) controller due to below reasons -On SoCs that have FMAN-v3H like B4860, default value of MDIO_CLK_DIV bits in mdio_stat(mdio_cfg) register generates mdio clock too high (much higher than 2.5MHz), violating the IEEE specs. -On SOCs that have FMAN-v3L like T1040, default value of MDIO_CLK_DIV bits is zero, so MDIO clock is disabled. So, for proper functioninig of MDIO, MDIO_CLK_DIV bits needs to be properly initialized. Also this type of initialization is generally done in PBI(pre-bootloader) phase using rcw.But for chips like T1040 which support deep-sleep, such type of initialization cannot be done in PBI phase due to the limitation that during deep-sleep resume, FMAN (MDIO) registers are not accessible in PBI phase. So, mdio clock initailization must be done as part of u-boot. This initialization code is implemented in memac_phy.c which gets compiled only for SoCs having FMANv3, so no extra compilation flag is required. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | fsl/usb: Increase TXFIFOTHRESH value for usb write in T4 Rev 2.0Nikhil Badola2014-04-22-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0. This decreases data burst rate with which data packets are posted from the TX latency FIFO to compensate for latencies in DDR pipeline during DMA. This avoids Tx buffer underruns and leads to successful usb writes Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver/mmc: fix compile warningsPrabhakar Kushwaha2014-04-22-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix following compile warnings fsl_esdhc_spl.c: In function 'mmc_boot': fsl_esdhc_spl.c:35:10: warning: unused variable 'byte_num' [-Wunused-variable] fsl_esdhc_spl.c:35:7: warning: unused variable 'i' [-Wunused-variable] fsl_esdhc_spl.c:34:8: warning: unused variable 'val' [-Wunused-variable] fsl_esdhc_spl.c:33:6: warning: unused variable 'blklen' [-Wunused-variable] fsl_esdhc_spl.c:105:7: warning: 'tmp_buf' may be used uninitialized in this function [-Wuninitialized] Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | fsl/usb: Workaround for USB erratum-A007075Nikhil Badola2014-04-22-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Put a delay of 5 millisecond after reset so that ULPI phy gets enough time to come out of reset. Erratum A007075 applies to following SOCs and their variants, if any P1010 rev 1.0 B4860 rev 1.0, 2.0 P4080 rev 2.0, 3.0 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver/ddr/fsl: Add DDR4 support to Freescale DDR driverYork Sun2014-04-22-269/+1906
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | net/phy: Fix PHY id for VSC8514Codrin Ciubotariu2014-04-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the current Datasheet for VSC8514 there is a mistake, saying that the PHY id is 0x70570. The real value in the identifier registers is 0x70670. Linux PHY driver uses 0x70670 also. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Cc: York Sun <yorksun@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver/fsl_ifc: Add a function to finalize CS0 address bindingYork Sun2014-04-22-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For fsl-lsch3 NOR flash boot, IFC CS0 needs to be binded with address within 32-bit at fist. After u-boot relocates to DDR, CS0 can be binded to higher address to support large space. Signed-off-by: York Sun <yorksun@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com>
| * | | QE/U-QE: Add U-QE supportZhao Qiang2014-04-22-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and ↵Zhao Qiang2014-04-22-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_QE_FW_ADDR CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | fsl/usb: Fix phy type for Second USB controllerNikhil Badola2014-04-22-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set correct phy_type value for second USB controller. This is required for supporting SOCs having 2 USB controllers working simultaneously, one with UTMI phy and other with ULPI phy Signed-off-by: Nikhil Badola <B46172@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | MIPS: drop incaip boardDaniel Schwierzeck2014-04-20-794/+0
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | This is dead hardware and no one is interested in making the necessary changes for upcoming features like generic board or driver model. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wolfgang Denk <wd@denx.de>
* | | e1000: remove redundant assignmentDavid Müller (ELSOFT AG)2014-04-18-1/+0
| | | | | | | | | | | | | | | Signed-off-by: David Mueller <d.mueller@elsoft.ch> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | pcnet: force ordering of descriptor accessesPaul Burton2014-04-18-18/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ordering of accesses to the rx & tx descriptors is important, yet the send & recv functions accessed them via regular structure accesses. This leaves the compiler with the opportunity to reorder those accesses or to hoist them outside of loops. Prevent that from happening by using readl & writel to access the descriptors. As a nice bonus, this removes the need for the driver to care about endianness. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* | | pcnet: align rx buffers for cache invalidationPaul Burton2014-04-18-9/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RX buffers are invalidated when a packet is received, however they were not suitably cache-line aligned. Allocate them seperately to the pcnet_priv structure and align to ARCH_DMA_MINALIGN in order to ensure suitable alignment for the cache invalidation, preventing anything else being placed in the same lines & lost. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* | | pcnet: access descriptor rings & init block uncachedPaul Burton2014-04-18-31/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The prior accesses to the descriptor rings & init block via cached memory had a few issues: - The memory needs cache flushes or invalidation at the appropriate times, but was not necessarily aligned on cache line boundaries. This could lead to data being incorrectly lost or written back to RAM at the wrong time. - There are points where ordering of writes to the memory is important, but because it's cached memory the pcnet controller would see cache lines written back ordered by address. This could occasionally lead to hardware seeing descriptors in an incorrect state. - Flushing the cache constantly is inefficient. So, to avoid all of those issues simply access the descriptors & init block via uncached memory. The MIPS-specific UNCACHED_SDRAM macro is used to do this (retrieving an address in kseg1) as I could see no existing generic solution. Since the MIPS Malta board is the only user of the pcnet driver, hopefully this doesn't matter. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* | | arm: remove lubbock board supportMasahiro Yamada2014-04-18-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enough time has passed since this board was moved to Orphan. Remove. - Remove board/lubbock/* - Remove include/configs/lubbock.h - Cleanup defined(CONFIG_LUBBOCK) - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | powerpc: remove RPXClassic, RPXlite boards supportMasahiro Yamada2014-04-18-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enough time has passed since these boards were moved to Orphan. Remove. - Remove board/RPXlite/* - Remove board/RPXClassic/* - Remove include/configs/RPXlite.h - Remove include/configs/RPXClassic.h - Clean-up defined(CONFIG_RPXCLASSIC) - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | mtd: delete unused filesMasahiro Yamada2014-04-17-1780/+0
|/ / | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com>
* | i2c: sh_i2c: bugfix: i2c probe command does not workTetsuyuki Kobayashi2014-04-14-1/+3
|/ | | | | | | | | | | | | | | | | | | | This is regression of commit 2035d77d i2c: sh_i2c: Update to new CONFIG_SYS_I2C framework Before commit 2035d77d, i2c probe command works properly on kzm9g board. KZM-A9-GT# i2c probe Valid chip addresses: 0C 12 1D 32 39 3D 40 60 After commit 2035d77d, i2c probe command does not work. KZM-A9-GT# i2c probe Valid chip addresses: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F sh_i2c_probe() calls sh_i2c_read(), but read length is 0. So acutally it does not read device at all. This patch prepares dummy buffer and read data into it. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-04-08-938/+787
|\ | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/arm926ejs/mxs/Makefile include/configs/trats.h include/configs/trats2.h include/mmc.h
| * ahci: Fix data abort on multiple scsi resets.Roger Quadros2014-04-02-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 2faf5fb82ed6 introduced a regression that causes a data abort when running scsi init followed by scsi reset. There are 2 problems with the original commit 1) ALLOC_CACHE_ALIGN_BUFFER() allocates memory on the stack but is assigned to ataid[port] and used by other functions. 2) The function ata_scsiop_inquiry() tries to free memory which was never allocated on the heap. Fix these problems by using tmpid as a temporary cache aligned buffer. Allocate memory separately for ataid[port] and re-use it if required. Fixes: 2faf5fb82ed6 (ahci: Fix cache align error messages) Reported-by: Eli Nidam <elini@marvell.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
| * mmc:eSDHC: Workaround for data timeout issue on Txxx SoCHaijun.Zhang2014-04-02-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. The Data timeout counter value in eSDHC_SYSCTL register is not working as it should be, so add quirks to enable this workaround to fix it to the max value 0xE. 2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround. * Update of patch for change mmc interface by Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * mmc: fsl_esdhc: add controller reset in case of data related errors tooAndrew Gabbasov2014-04-02-27/+36
| | | | | | | | | | | | | | | | The controller reset is performed now if command error occurs. This commit adds the reset for the case of data related errors too. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * mmc: fsl_esdhc: fix calculation of timeout for data transactionsAndrew Gabbasov2014-04-02-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Calculation of the timeout value should be based on actual clock value, written to controller registers. Since mmc->tran_speed is either the maximum allowed speed, or the preliminary value, that is be not yet set to registers, the actual timeout, taken by the controller, based on its clock settings, may be much longer than expected, based on mmc->tran_speed value. In particular it happens at early initialization stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while actual clock setting, configured in the controller, is 400kHz. It's more correct to use mmc->clock value for timeout calculation instead. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * mmc: Add 'mmc rst-function' sub-commandTom Rini2014-04-02-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Some eMMC chips may need the RST_n_FUNCTION bit set to a non-zero value in order for warm reset of the system to work. Details on this being required will be part of the eMMC datasheet. Also add using this command to the dra7xx README. * Whitespace fix by panto Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * mmc: sh_mmcif: Fix warning by unused variableNobuhiro Iwamatsu2014-04-02-2/+1
| | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * mmc: sh_mmcif: Fix compile errorNobuhiro Iwamatsu2014-04-02-1/+1
| | | | | | | | | | | | | | | | | | | | BY commit "mmc: Split mmc struct, rework mmc initialization (v2)", sh_mmcif has compile error. This fixes compile error. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> CC: Pantelis Antoniou <panto@antoniou-consulting.com> Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
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