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| * | | i2c: switch from AT91 legacy to ATMEL legacyAndreas Bießmann2013-11-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the required API is gpio which is enclosed with CONFIG_ATMEL_LEGACY use that switch here. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Heiko Schocher <hs@denx.de>
| * | | video: remove AT91 legacy API from bus_vcxkAndreas Bießmann2013-11-13-15/+0
| |/ / | | | | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de> Acked-by: Anatolij Gustschin <agust@denx.de>
| * | usb, g_dnl: make bcdDevice value configurableHeiko Schocher2013-11-12-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add the possibility to set the bcdDevice number board specific. Therefore the weak function g_dnl_get_board_bcd_device_number() is introduced. Used on the siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Kyungmin Park <kyungmin.park@samsung.com>
| * | am33xx: Make SoC bootcount driver have its own symbolTom Rini2013-11-11-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some am33xx boards may not use the RTC block for bootcount (as it may not be wired up for the board) and use some other facility. So add another symbol for the bootcount driver for the IP block. Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@ti.com>
| * | bootcount: store bootcount var in environmentHeiko Schocher2013-11-11-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If no softreset save registers are found on the hardware "bootcount" is stored in the environment. To prevent a saveenv on all reboots, the environment variable "upgrade_available" is introduced. If "upgrade_available" is 0, "bootcount" is always 0 therefore no need to save the environment on u-boot boot, if "upgrade_available" is 1 "bootcount" is incremented in the environment and environment gets written on u-boot start. So the Userspace Applikation must set the "upgrade_available" and "bootcount" variable to 0 (for example with fw_setenv), if a boot was successfully. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | Merge branch 'spi' of git://git.denx.de/u-boot-x86Tom Rini2013-12-10-12/+738
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| * | | sandbox: spi: Add new SPI flash driverMike Frysinger2013-12-09-1/+487
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a SPI flash driver which simulates SPI flash clients. Currently supports the bare min that U-Boot requires: you can probe, read, erase, and write. Should be easy to extend to make it behave more exactly like a real SPI flash, but this is good enough to merge now. sjg@chromium.org added a README and tidied up code a little. Added a required map_sysmem() for sandbox. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: spi: Add SPI emulation busMike Frysinger2013-12-09-0/+205
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a SPI framework for people to hook up simulated SPI clients. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | spi_flash: Add spi_flash_probe_fdt() to locate SPI by FDT nodeSimon Glass2013-12-09-11/+46
| | |/ | |/| | | | | | | | | | | | | | | | This allows us to put the SPI flash chip inside the SPI interface node, with U-Boot finding the correct bus and chip select automatically. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2013-12-10-18/+58
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| * | | mmc: add Faraday FTSDC021 SDHCI controller supportKuo-Jung Su2013-12-08-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Faraday FTSDC021 is a controller which is compliant with SDHCI v3.0, SDIO v2.0 and MMC v4.3. However this driver is only verified with SD memory cards. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> CC: Andy Fleming <afleming@gmail.com>
| * | | powerpc: mmc: Add corenet devices support in esdhc splPriyanka Jain2013-12-08-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Existing eSDHC SPL framework assumes booting from sd-image with boot_format header which contains final u-boot Image offset and size. No such header is present in case of corenet devices like T1040 as corenet deivces use PBI-RCW based intialization. So, for corenet deives, SPL bootloader use values provided at compilation time. These values can be defined in board specific config file. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | | mmc/dwmmc: modify FIFO threshold only if value explicitly setAlexey Brodkin2013-12-08-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If platform provides "host->fifoth_val" it will be used for initialization of DWMCI_FIFOTH register. Otherwise default value will be used. This implementation allows: * escape unclear and recursive calculations that are currently in use * use whatever custom value for DWMCI_FIFOTH initialization if any particular SoC requires it Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Alim Akhtar <alim.akhtar@samsung.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Amar <amarendra.xt@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Andy Fleming <afleming@freescale.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | | mmc: dw_mmc: remove the exynos specific code in dw-mmc.cJaehoon Chung2013-12-08-10/+16
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dw-mmc.c is the general driver file. So, remove the exynos specific code at dw-mmc.c. Instead, exynos specific cod can be move into exynos-dw_mmc.c. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-12-10-251/+393
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| * | | i2c: samsung: register i2c busses for Exynso5420 and Exynos5250Naveen Krishna Ch2013-12-06-48/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the U_BOOT_I2C_ADAP_COMPLETE defines for channels on Exynos5420 and Exynos5250 and also adds support for init function for hsi2c channels Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
| * | | arm: omap: i2c: don't zero cnt in i2c_writeNikita Kiryanov2013-12-05-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Writing zero into I2Ci.I2C_CNT register causes random I2C failures in OMAP3 based devices. This seems to be related to the following advisory which apears in multiple erratas for OMAP3 SoCs (OMAP35xx, DM37xx), as well as OMAP4430 TRM: Advisory: I2C Module Does Not Allow 0-Byte Data Requests Details: When configured as the master, the I2C module does not allow 0-byte data transfers. Note: Programming I2Ci.I2C_CNT[15:0]: DCOUNT = 0 will cause undefined behavior. Workaround(s): No workaround. Do not use 0-byte data requests. The writes in question are unnecessary from a functional point of view. Most of them are done after I/O has finished, and the only one that preceds I/O (in i2c_probe()) is also unnecessary because a stop bit is sent before actual data transmission takes place. Therefore, remove all writes that zero the cnt register. Cc: Heiko Schocher <hs@denx.de> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Tom Rini <trini@ti.com> Cc: Lubomir Popov <lpopov@mm-sol.com> Cc: Enric Balletbo Serra <eballetbo@gmail.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Lubomir Popov <lpopov@mm-sol.com>
| * | | i2c: fti2c010: serial out r/w address in MSB orderKuo-Jung Su2013-12-05-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For a eeprom with a 2-bytes address (e.g., Ateml AT24C1024B), the r/w address should be serial out in MSB order. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Heiko Schocher <hs@denx.de>
| * | | i2c: fti2c010: migrate to new i2c modelKuo-Jung Su2013-12-05-166/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the legacy i2c model with the new one. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Heiko Schocher <hs@denx.de>
| * | | i2c: fti2c010: cosmetic: coding style cleanupKuo-Jung Su2013-12-05-15/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Coding style cleanup Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Heiko Schocher <hs@denx.de>
| * | | driver:i2c:s3c24x0: fix clock init for hsi2cPiotr Wilczek2013-12-05-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix clock value initialisation for Exynos other than Exynos5 for hsi2c. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Heiko Schocher <hs@denx.de>
| * | | driver:i2c:s3c24x0: adapt driver to new i2cPiotr Wilczek2013-12-05-57/+97
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adapts the s3c24x0 driver to the new i2c framework. Config file is modified for all the boards that use the driver. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com> CC: Heiko Schocher <hs@denx.de> CC: Inderpal Singh <inderpal.singh@linaro.org> CC: David Müller <d.mueller@elsoft.ch> CC: Chander Kashyap <k.chander@samsung.com> CC: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Reviewed-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-blackfinTom Rini2013-12-06-12/+10
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| * | | spi: bfin_spi6xx: Remove unnecessary test for bus and pins[bus]Axel Lin2013-12-06-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For invalid bus number, current code returns NULL in the default case of switch-case statements. In additional, pins[bus] is always not NULL because it is the address of specific row of the two-dimensional array. Thus this patch removes these unnecessary test. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| * | | spi: bfin_spi: Remove unnecessary test for bus and pins[bus]Axel Lin2013-12-06-8/+9
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For invalid bus number, current code returns NULL in the default case of switch-case statements. In additional, pins[bus] is always not NULL because it is the address of specific row of the two-dimensional array. Thus this patch removes these unnecessary test. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* | | powerpc: spiflash:Add corenet devices support in eSPI SPLPriyanka Jain2013-12-04-0/+5
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | Existing eSPI SPL framework assumes booting from spi-image with boot_format header which contains final u-boot Image offset and size. No such header is present in case of corenet devices like T1040 as corenet deivces use PBI-RCW based intialization. So, for corenet deives, SPL bootloader use values provided at compilation time. These values can be defined in board specific config file. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | Merge branch 'serial' of git://git.denx.de/u-boot-microblazeTom Rini2013-12-02-4/+0
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| * | serial: zynq: Remove unused #definesSoren Brinkmann2013-12-02-4/+0
| | | | | | | | | | | | | | | | | | Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Series-to: trini, uboot
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-12-02-8/+8496
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| * | powerpc/mpc85xx: Add T2080/T2081 SoC supportShengzhou Liu2013-11-25-0/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | net/fman: Add support for 10GEC3 and 10GEC4Shengzhou Liu2013-11-25-6/+26
| | | | | | | | | | | | | | | | | | | | | There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080). This patch adds support for 10GEC3 and 10GEC4. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
| * | Driver/IFC: Move Freescale IFC driver to a common driverYork Sun2013-11-25-2/+143
| | | | | | | | | | | | | | | | | | | | | | | | Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com>
| * | Driver/DDR: Update DDR driver to allow non-zero base addressYork Sun2013-11-25-3/+3
| | | | | | | | | | | | | | | | | | | | | The DRAM base has been zero for Power SoCs. It could be non-zero for ARM SoCs. Use a macro instead of hard-coding to zero. Signed-off-by: York Sun <yorksun@freescale.com>
| * | powerpc/mpc8xxx: Extend DDR registers' fieldsYork Sun2013-11-25-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some DDR registers' fields have expanded to accommodate larger values. These changes are backward compatible. Some fields are removed for newer DDR controllers. Writing to those fields are safely ignored. TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE automatically. It was a misunderstanding in commit c360ceac. Signed-off-by: York Sun <yorksun@freescale.com>
| * | Driver/DDR: Add Freescale DDR driver for ARMYork Sun2013-11-25-4/+227
| | | | | | | | | | | | | | | | | | | | | Make PowerPC specific code conditional so ARM SoCs can reuse this driver. Add DDR3 driver for ARM. Signed-off-by: York Sun <yorksun@freescale.com>
| * | Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xxYork Sun2013-11-25-8/+14
| | | | | | | | | | | | | | | | | | | | | Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com>
| * | Driver/DDR: Moving Freescale DDR driver to a common driverYork Sun2013-11-25-0/+7977
| | | | | | | | | | | | | | | | | | | | | Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2013-11-25-193/+473
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| * | | net: rtl8169: Add support for RTL8168d/8111dThierry Reding2013-11-22-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This chip is compatible with the existing driver, except that it uses BAR2 instead of BAR1 for the I/O memory region. Using this patch I can use the PCIe ethernet interface on the CompuLab Trimslice to boot from the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Patch: 276477
| * | | net: rtl8169: Improve cache maintenanceThierry Reding2013-11-22-8/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of directly calling the low-level invalidate_dcache_range() and flush_cache() functions, provide thin wrappers that take into account alignment requirements. While at it, fix a case where the cache was flushed but should have been invalidated, two cases where the buffer data was flushed instead of the descriptor and a missing cache invalidation before reading the packet data that the NIC just wrote to memory. Signed-off-by: Thierry Reding <treding@nvidia.com> Patch: 276474
| * | | net: zynq_gem: Add d-cache supportSrikanth Thokala2013-11-22-29/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added d-cache support for zynq_gem.c, Observed a difference of +0.8 MiB/s when downloading a file of size of 3007944Bytes. With d-cache OFF: ---------------- Filename 'uImage'. Load address: 0x800 Loading: ################################################################# ################################################################# ################################################################# ########## 1.3 MiB/s done Bytes transferred = 3007944 (2de5c8 hex) With d-cache ON: --------------- Filename 'uImage'. Load address: 0x800 Loading: ################################################################# ################################################################# ################################################################# ########## 2.1 MiB/s done Bytes transferred = 3007944 (2de5c8 hex) Changes on zynq_gem for d-cache support: - Tx and Rx buffers are cache-aligned - Updated logic for invalidating Rx buffers and flushing Tx buffers. - Tx and Rx BD's are allocated from non-cacheable region. (When BDs are cached, we don't see a consistent link) - Use TX BD status intead of txsr status checks. Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | phy: Use general phy code for smsc lan8720aDavid Dueck2013-11-22-1/+2
| | | | | | | | | | | | | | | | Signed-off-by: David Dueck <davidcdueck@googlemail.com>
| * | | phy: Use supported field during autonegotiationDavid Dueck2013-11-22-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code incorrectly detects gigabit capabilities for some 100Mbit/s phys. (lan8720a) Signed-off-by: David Dueck <davidcdueck@googlemail.com>
| * | | net: dm9000: random mac address supportAndrew Ruder2013-11-22-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an unprogrammed EEPROM is attached to a dm9000, the dm9000 will come up with a invalid MAC address of ff:ff:ff:ff:ff:ff. Add code that gets enabled if CONFIG_RANDOM_MACADDR is enabled that generates a random (and valid) locally administered MAC address that allows the system to network boot until a real MAC address can be configured. Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
| * | | drivers/net/e1000: Introduce CONFIG_E1000_NO_NVMRojhalat Ibrahim2013-11-22-5/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The e1000 driver expects to always have some kind of non-volatile memory attached directly to the ethernet controller chip. This means that I would have to add an additional separate flash chip to my custom board just to store essentially the MAC address. Since I don't want to do that, this patch introduces a new config option CONFIG_E1000_NO_NVM. If defined it disables all accesses to the NVM. I have tested the patch with a 82574 controller. Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
| * | | net: phy: atheros: Fix masks for AR8035 and AR8021Fabio Estevam2013-11-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The masks were ignoring the last 4 bits which didn't allow detection differences between the ar8031 and ar8035. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Patch: 288018
| * | | net/phy: Fix the phy id mask of AR8031Chunhe Lan2013-11-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The both AR8031 and AR8035 belong to Atheros 803x serial PHY. So the phy id mask of AR8031 is the same to the phy id mask of AR8035. The right mask value is 0x4fffff. This patch has been tested on the P1010 and P1023. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 287748
| * | | net: tsec: Fix mac addr setup portability, cleanupClaudiu Manoil2013-11-22-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the 32-bit memory access that is not "endianess safe", i.e. not giving the desired byte layout for LE cpus: tempval = *((uint *) (tmpbuf + 4)), where 'char tmpbuf[]'. Free the stack from rendundant local vars: tmpbuf[] and i. Use a portable type (u32) for the 32bit tsec register value holder: tempval. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
| * | | net: tsec: Use portable regs type (uint->u32)Claudiu Manoil2013-11-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use cross arch portable u32 instead of uint for the tsec registers. Remove the typedefs for the register struct definitions in the process. Fix long lines. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
| * | | net: tsec: Use portable types and accessors for BDsClaudiu Manoil2013-11-22-42/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the buffer descriptor (BD) fields cannot be correctly accessed by a little endian processor. This patch fixes the issue by making the access of BDs to be portable among different cpu architectures. Use portable data types for the Rx/Tx buffer descriptor fields. Use portable I/O accessors to insure that the big endian BDs are correctly accessed by little endian cpus too, and to insure proper sync with the H/W. Removed the redundant RTXBD "volatile" type, as proper synchronization around BD data accesses is provided by the I/O accessors now. The "sparse" tool was also used to verify the correctness of these changes. Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
generated by cgit v1.1 at 2024-11-07 02:48:03 +0000