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* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-02-04-2/+2
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| * usb: gadget: dwc2_udc_otg: modified the check condition for max packet size ↵Frank Wang2016-02-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | of ep_in in high speed In current high speed fastboot, fs_ep_in.wMaxPacketSize is configured 64 bytes as default, as a result, it failed to match the size at initialization stage in usb controller. Actually, hardware can support less than or equal to 512 bytes in high speed mode, so I changed the condition from '!=' to '>' to fix this issue. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Tested-by: Steve Rae <srae@broadcom.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-02-04-1/+1
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| * | Revert "arm: socfpga: set the fpga global bit to disable HPS to FPGA signals"Dinh Nguyen2016-02-04-1/+1
| |/ | | | | | | | | | | | | | | Apparently, the logic for the FPGA global bit is not universal between Gen5 and Gen10 devices is not the same. Disabling this bit, while applicable to Gen10 devices, will break FPGA programming on Gen5 devices. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | dm: vybrid_gpio: Drop legacy codeBhuvanchandra DV2016-02-02-18/+0
| | | | | | | | | | | | | | | | All boards using this driver are with device tree support, hence drop the legacy code in driver to have a pure DT solution. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: lpuart: Drop the legacy codeBhuvanchandra DV2016-02-02-99/+2
|/ | | | | | | | All boards using this driver are with device tree support, hence drop the legacy code in driver to have a pure DT solution. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-02-02-50/+82
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| * atmel_nand: Add 32 bit ecc support for sama5d2 chipJosh Wu2016-02-02-1/+9
| | | | | | | | | | | | | | | | | | | | Also if minimum ecc requirment is bigger then what we support, then just use our maxium pmecc support. But it is not safe, so we'll output a warning about this. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * atmel_nand_ecc: update pmecc registers according to sama5d2 chipJosh Wu2016-02-02-4/+32
| | | | | | | | | | | | | | | | | | | | 1. add the pmecc register mapping for sama5d2. 2. add the pmecc error location register mapping for sama5d2. 3. add some new field that is different from old ip. 4. add sama5d2 pmecc ip version number. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * atmel_nand: use the definition: PMECC_OOB_RESERVED_BYTES instead magic numberJosh Wu2016-01-27-1/+1
| | | | | | | | | | | | | | | | | | As atmel_nand_ecc.h is sync with v4.1 kernel, which adds the PMECC_OOB_RESERVED_BYTES. So use it in the driver. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * atmel_nand: add '\n' in the end of error message for better displayJosh Wu2016-01-27-2/+2
| | | | | | | | | | | | | | | | Also align the open parenthesis. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * atmel_nand: use nand ecc_{strength, step}_ds instead of our own functionJosh Wu2016-01-27-37/+7
| | | | | | | | | | | | | | | | | | | | Since ecc_{strength,step}_ds is introduced in nand_chip structure for minimum ecc requirements. So we can use them directly and remove our own get_onfi_ecc_param function. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * net: macb: Not all the GEM are gigabit capableGregory CLEMENT2016-01-27-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the initialization of PHY the gigabit bit capable is set if the controller is a GEM. However, for sama5d2 and sama5d4, the GEM is configured to support only 10/100. Improperly setting the GBE capability leads to an unresponsive MAC controller. This patch fixes this behavior allowing using the gmac with these SoCs. Suggested-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> [fixed minor checkpatch warning] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * mmc: atmel: Properly fix clock configurationGregory CLEMENT2016-01-27-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Timing issue occurs on eMMC not only when modifying the frequency but also for all the switch command(CMD6). According to the MMC spec waiting 8 clocks after a switch command would be the thing to do. This patch allows fixing CPU hang observed when trying to changing the bus width on a eMMC on SAMA5D4. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Marek Vasut <marex@denx.de> # on DENX MA5D4EV Acked-by: Marek Vasut <marex@denx.de> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com> # on atngw100 Acked-by: Andreas Bießmann <andreas.devel@googlemail.com> [fixed minor checkpatch warning] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-02-02-1/+2
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| * | driver: net: fsl-mc: Update print to reflect correct stringPrabhakar Kushwaha2016-02-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Update printf with dpbp_exit to match with previous function call. Signed-off-by: Itai Katz <itai.katz@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | driver: net: fsl-mc: Memset dprc_cfg before configuringPrabhakar Kushwaha2016-02-01-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All fields of struct dprc_cfg are not being configured while creating child container. "Not" configured fields are assumed to be 0. So memset dprc_cfg before configuring the fields. Signed-off-by: Itai Katz <itai.katz@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | drivers: net: Add ethernet driver for Microchip PIC32.Purna Chandra Mandal2016-02-01-0/+899
| | | | | | | | | | | | | | | | | | | | | | | | This driver implements MAC and MII layer of the ethernet controller. Network data transfer is handled by controller internal DMA engine. Ethernet controller is configurable through device-tree file. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
* | | drivers: net: phy: add SMSC LAN8740 Phy support.Purna Chandra Mandal2016-02-01-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add SMSC LAN8740 Phy support required for PIC32MZDA devices. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | drivers: mmc: add driver for Microchip PIC32 SDHCI controller.Andrei Pistirica2016-02-01-1/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver implements platform specific glue and fixups for PIC32 internal SDHCI controller. Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com> Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.Purna Chandra Mandal2016-02-01-0/+498
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module. DDR2 controller operates in half-rate mode (upto 533MHZ frequency). Signed-off-by: Paul Thacker <paul.thacker@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | drivers: serial: add driver for Microchip PIC32 UART controller.Paul Thacker2016-02-01-0/+214
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds PIC32 UART controller support based on driver model. Signed-off-by: Paul Thacker <paul.thacker@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | drivers: gpio: add driver for Microchip PIC32 GPIO controller.Purna Chandra Mandal2016-02-01-1/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In PIC32 GPIO controller is part of PIC32 pin controller. PIC32 has ten independently programmable ports and each with multiple pins. Each of these pins can be configured and used as GPIO, provided they are not in use for other peripherals. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | drivers: pinctrl: Add pinctrl driver for Microchip PIC32.Purna Chandra Mandal2016-02-01-0/+374
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In PIC32 pin-controller is a combined gpio-controller, pin-mux and pin-config module. Remappable peripherals are assigned pins through per-pin based muxing logic. And pin configuration are performed on specific port registers which are shared along with gpio controller. Note, non-remappable peripherals have default pins assigned thus require no muxing. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.Purna Chandra Mandal2016-02-01-0/+434
|/ / | | | | | | | | | | | | | | | | | | PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers and dividers capable of supplying clock to various controllers on or off-chip. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | video: sandbox: Allow selection of font size and console nameSimon Glass2016-01-30-0/+2
| | | | | | | | | | | | | | | | For testing it is useful to be able to select the font size and the console driver for sandbox. Add this information to platform data and copy it to the video device when needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* | video: Allow selection of the driver and font sizeSimon Glass2016-01-30-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | Provide a way for the video console driver to be selected. This is controlled by the video driver's private data. This can be set up when the driver is probed so that it is ready for the video_post_probe() method. The font size is provided as well. The console driver may or may not support this depending on its capability. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | video: Add the Cantoraone decorative fontSimon Glass2016-01-30-0/+15
| | | | | | | | | | | | | | This font is a little more ornate than normal. Example uses are on security screens where a feeling of formality is required. Signed-off-by: Simon Glass <sjg@chromium.org>
* | video: Add the Rufscript handwriting fontSimon Glass2016-01-30-0/+14
| | | | | | | | | | | | | | This can be used when a a friendly 'hand-writing' font is needed. It helps to make the device feel familiar. Signed-off-by: Simon Glass <sjg@chromium.org>
* | video: Add the AnkaCoder mono-spaced fontSimon Glass2016-01-30-0/+17
| | | | | | | | | | | | | | This can be used when a mono-space font is needed, but the console font is too small (such as with high-DPI displays). Signed-off-by: Simon Glass <sjg@chromium.org>
* | video: Add the Nimbus sans fontSimon Glass2016-01-30-0/+20
| | | | | | | | | | | | This provides a good-looking font for user prompts. Signed-off-by: Simon Glass <sjg@chromium.org>
* | video: Add a console driver that uses TrueType fontsSimon Glass2016-01-30-2/+580
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing 8x16 font is adequate for most purposes. It is small and fast. However for boot screens where information must be presented to the user, the console font is not ideal. Common requirements are larger and better-looking fonts. This console driver can use TrueType fonts built into U-Boot, and render them at any size. This can be used in scripts to place text as needed on the display. This driver is not really designed to operate with the command line. Much of U-Boot expects a fixed-width font. But to keep things working correctly, rudimentary support for the console is provided. The main missing feature is support for command-line editing. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | video: Provide a backspace methodSimon Glass2016-01-30-1/+11
| | | | | | | | | | | | | | | | With proportional fonts the vidconsole uclass cannot itself erase the previous character. Provide an optional method so that the driver can handle this operation. Signed-off-by: Simon Glass <sjg@chromium.org>
* | video: Provide a signal when a new console line is startedSimon Glass2016-01-30-0/+14
| | | | | | | | | | | | | | When we start a new line (due to the user pressing return), signal this to the driver so that it can flush its buffer of character positions. Signed-off-by: Simon Glass <sjg@chromium.org>
* | video: Provide a left margin for the text consoleSimon Glass2016-01-30-3/+3
| | | | | | | | | | | | | | Allow the left margin to be set so that text does not have to be right up against the left side. On some panels this makes it hard to read. Signed-off-by: Simon Glass <sjg@chromium.org>
* | video: Handle the 'bell' characterSimon Glass2016-01-30-0/+3
| | | | | | | | | | | | | | This can be sent when to many characters are entered. Make sure it is ignored and does not cause a character to be displayed. Signed-off-by: Simon Glass <sjg@chromium.org>
* | video: Use fractional units for X coordinatesSimon Glass2016-01-30-42/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With anti-aliased fonts we need a more fine-grained horizontal position than a single pixel. Characters can be positioned to start part-way through a pixel, with anti-aliasing (greyscale edges) taking care of the visual effect. To cope with this, use fractional units (1/256 pixel) for horizontal positions in the text console. Signed-off-by: Simon Glass <sjg@chromium.org> [agust: rebased] Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | video kconfig console_normalSimon Glass2016-01-30-3/+14
| | | | | | | | | | | | Signed-off-by: Simon Glass <sjg@chromium.org> [agust: rebased on current master] Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | video: Add stb TrueType font rendererSimon Glass2016-01-30-0/+3240
| | | | | | | | | | | | | | | | | | | | | | | | This is a header file which provides a fairly light-weight TrueType rendering implementation. It is pulled from http://nothings.org/. The code style does not comply with U-Boot but I think it is best to leave alone to permit the source to be synced later if needed. The only change is to fix a reference to fabs() which should route through a macro to allow U-Boot to provide its own version. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-01-29-26/+1269
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| * | Implement "pci enum" command for CONFIG_DM_PCIStephen Warren2016-01-28-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With CONFIG_DM_PCI enabled, PCI buses are not enumerated at boot, as they are without that config option enabled. No command exists to enumerate the PCI buses. Hence, unless some board-specific code causes PCI enumeration, PCI-based Ethernet devices are not detected, and network access is not available. This patch implements "pci enum" in the CONFIG_DM_PCI case, thus giving a mechanism whereby PCI can be enumerated. do_pci()'s handling of case 'e' is moved into a single location before the dev variable is assigned, in order to skip calculation of dev. The enum sub-command doesn't need the dev value, and skipping its calculation avoids an irrelevant error being printed. Using a command to initialize PCI like this has a disadvantage relative to enumerating PCI at boot. In particular, Ethernet devices are not probed during PCI enumeration, but only when used. This defers setting variables such as ethact, ethaddr, etc. until the first network-related command is executed. Hopefully this will not cause further issues. Perhaps in the long term, we need a "net start/enum" command too? Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | dm: Remove device_probe_child()Simon Glass2016-01-28-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This function is not used as the use case for it did not eventuate. Remove it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | tpm: st33zp24: Add tpm st33zp24 spi supportChristophe Ricard2016-01-28-0/+682
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for TPM ST33ZP24 spi. The ST33ZP24 does have a spi interface. The transport protocol is proprietary. For spi we are relying only on DM_SPI. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
| * | tpm: st33zp24: Add tpm st33zp24 support with i2cChristophe Ricard2016-01-28-0/+553
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for TPM ST33ZP24 family with i2c. For i2c we are relying only on DM_I2C. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
| * | tpm: Rename tpm_tis_infineon.h to tpm_tis.h and move infineon specific stuff ↵Christophe Ricard2016-01-28-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | in tpm_infineon.c I2C protocol is not standardize for TPM 1.2. TIS prococol is define by the Trusted Computing Group and potentially available on several TPMs. tpm_tis_infineon.h header is not generic enough. Rename tpm_tis_infineon.h to tpm_tis.h and move infineon specific defines/variables to tpm_tis_infineon.c Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
| * | tpm: tpm_tis_lpc: fix typoChristophe Ricard2016-01-28-1/+1
| | | | | | | | | | | | | | | | | | | | | TPM_TIS_LPC is connected to the LPC bus, not I2C. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-01-28-214/+837
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| * | net: phy: implements probe for Cortina phyShaohui Xie2016-01-28-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Cortina phy cannot support soft reset, this commit implements probe for Cortina PHY to tell phylib to skip phy soft reset by setting PHY_FLAG_BROKEN_RESET in flags. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: introduce a quirk PHY_FLAG_BROKEN_RESETShaohui Xie2016-01-28-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current driver always performs a phy soft reset when connecting the phy device, but soft reset is not always supported by a phy device, so introduce a quirk PHY_FLAG_BROKEN_RESET to let such a phy device to skip soft reset. This commit uses 'flags' of phy device structure to store the quirk. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: micrel: fix divisor value for KSZ9031 phy skewDinh Nguyen2016-01-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The picoseconds to register value divisor(ps_to_regval) should be 60 and not 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct divisor because the 4-bit skew values are defined from 0x0000(-420ps) to 0xffff(480ps), increments of 60. For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7. With the previous divisor of 200, it would result in 0x2, which represents a -300ps delay. With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with 1Gb ethernet. References: http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26 Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
generated by cgit v1.1 at 2024-11-10 00:33:54 +0000