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* | ddr: altera: sdram: Clean up set_sdr_mp_pacing()Marek Vasut2015-08-08-21/+16
* | ddr: altera: sdram: Clean up set_sdr_mp_weight()Marek Vasut2015-08-08-21/+16
* | ddr: altera: sdram: Clean up set_sdr_fifo_cfg()Marek Vasut2015-08-08-7/+7
* | ddr: altera: sdram: Clean up set_sdr_static_cfg()Marek Vasut2015-08-08-8/+7
* | ddr: altera: sdram: Clean up set_sdr_addr_rw()Marek Vasut2015-08-08-20/+10
* | ddr: altera: sdram: Clean up set_sdr_dram_timing*()Marek Vasut2015-08-08-93/+53
* | ddr: altera: sdram: Clean up set_sdr_ctrlcfg()Marek Vasut2015-08-08-38/+24
* | ddr: altera: sdram: Clean up compute_errata_rows() part 2Marek Vasut2015-08-08-15/+20
* | ddr: altera: sdram: Clean up compute_errata_rows() part 1Marek Vasut2015-08-08-7/+7
* | ddr: altera: sdram: Switch to generic_hweight32()Marek Vasut2015-08-08-1/+1
* | ddr: altera: Clean up of delay_for_n_mem_clocks() part 5Marek Vasut2015-08-08-3/+5
* | ddr: altera: Clean up of delay_for_n_mem_clocks() part 4Marek Vasut2015-08-08-12/+5
* | ddr: altera: Clean up of delay_for_n_mem_clocks() part 3Marek Vasut2015-08-08-18/+6
* | ddr: altera: Clean up of delay_for_n_mem_clocks() part 2Marek Vasut2015-08-08-8/+10
* | ddr: altera: Clean up of delay_for_n_mem_clocks() part 1Marek Vasut2015-08-08-14/+13
* | ddr: altera: Minor clean up of rw_mgr_mem_handoff()Marek Vasut2015-08-08-7/+8
* | ddr: altera: Clean up rw_mgr_mem_calibrate_lfifo()Marek Vasut2015-08-08-22/+27
* | ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_end()Marek Vasut2015-08-08-38/+21
* | ddr: altera: Clean up rw_mgr_mem_calibrate_write_test_issue()Marek Vasut2015-08-08-13/+18
* | ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 3Marek Vasut2015-08-08-1/+11
* | ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 2Marek Vasut2015-08-08-39/+36
* | ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 1Marek Vasut2015-08-08-205/+201
* | ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 5Marek Vasut2015-08-08-1/+6
* | ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4Marek Vasut2015-08-08-6/+7
* | ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3Marek Vasut2015-08-08-3/+2
* | ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 2Marek Vasut2015-08-08-79/+88
* | ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1Marek Vasut2015-08-08-61/+63
* | ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 11Marek Vasut2015-08-08-1/+10
* | ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 10Marek Vasut2015-08-08-4/+7
* | ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 9Marek Vasut2015-08-08-18/+17
* | ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 8Marek Vasut2015-08-08-18/+15
* | ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 7Marek Vasut2015-08-08-12/+9
* | ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 6Marek Vasut2015-08-08-89/+88
* | ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 5Marek Vasut2015-08-08-46/+44
* | ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 4Marek Vasut2015-08-08-17/+23
* | ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 3Marek Vasut2015-08-08-66/+60
* | ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 2Marek Vasut2015-08-08-170/+146
* | ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 1Marek Vasut2015-08-08-221/+197
* | ddr: altera: Clean up rw_mgr_mem_calibrate_writes()Marek Vasut2015-08-08-12/+24
* | ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 5Marek Vasut2015-08-08-4/+13
* | ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 4Marek Vasut2015-08-08-9/+11
* | ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 3Marek Vasut2015-08-08-4/+3
* | ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 2Marek Vasut2015-08-08-15/+15
* | ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 1Marek Vasut2015-08-08-13/+16
* | ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_all_ranks()Marek Vasut2015-08-08-15/+25
* | ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 7Marek Vasut2015-08-08-0/+6
* | ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 6Marek Vasut2015-08-08-17/+14
* | ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 5Marek Vasut2015-08-08-6/+6
* | ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 4Marek Vasut2015-08-08-54/+49
* | ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 3Marek Vasut2015-08-08-2/+3
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