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| * | pinctrl: uniphier: fix NAND and SD pin-mux settings for PH1-LD11/LD20Masahiro Yamada2016-04-24-4/+4
| | | | | | | | | | | | | | | | | | | | | I found many mistakes in the initial version. Fixes: 8a3328c209d0 ("pinctrl: uniphier: support UniPhier PH1-LD20 pinctrl driver") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: rename function/array namesMasahiro Yamada2016-04-24-102/+102
| |/ | | | | | | | | | | Make function/array names match the file names for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-usbTom Rini2016-04-25-50/+81
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| * | dfu: ram: fix number base of RAM entity parametersStephen Warren2016-04-25-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot typically interprets unprefixed numbers as base 16, and DFU RAM entity parsing has historically done so. Reverse the change to default to base 10, so that values in previously working command-lines aren't mis-parsed, causing RAM corruption, crashes, hangs, etc. Fixes: 6aeb877afef0 ("drivers: dfu: ram: fix a crash with dfu ram with invalid dfu_alt_info env") Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> [Test HW: AM335x BBB]
| * | drivers: dfu: ram: fix a crash with dfu ram with invalid dfu_alt_info envMugunthan V N2016-04-25-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot crashes when an invalid dfu_alt_info is set and tried using dfu command. Fixing this as it is handled in dfu-mmc. => dfu 0 ram 0 data abort pc : [<9ff893d6>] lr : [<9ff6edb9>] reloc pc : [<808323d6>] lr : [<80817db9>] sp : 9ef36cf0 ip : 00000158 fp : 9ffbc0b8 r10: 9ffbc0b8 r9 : 9ef36ed8 r8 : 00000000 r7 : 00000000 r6 : 9ffbc0c8 r5 : 9ef36cfc r4 : 9ef392c8 r3 : 00000004 r2 : 00000000 r1 : 9ff9a985 r0 : ffffffff Flags: Nzcv IRQs off FIQs on Mode SVC_32 Resetting CPU ... resetting ... Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | usb: s3c-otg: Fix remaining bytes in debug messagesRoger Quadros2016-04-25-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remaining bytes means bytes that are not yet transferred and not the bytes that were transferred in the last transfer. Reported-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Tested-by: Steve Rae <srae@broadcom.com> [Test HW: bcm28155_ap board]
| * | usb: s3c-otg: Fix short packet for request size > ep.maxpacketRoger Quadros2016-04-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Request size can be greater than ep.packet and still end in a short packet. We need to tackle this case as end of transfer (if short_not_ok is not set) as indicated in USB 2.0 Specification [1], else we get stuck up on certain protocols like fastboot. [1] - USB2.0 Specification, Section 5.3.2 Pipes Reported-by: Steve Rae <steve.rae@broadcom.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Tested-by: Steve Rae <steve.rae@broadcom.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com>
| * | fastboot: Clean up bulk-out logicRoger Quadros2016-04-25-27/+23
| | | | | | | | | | | | | | | | | | | | | | | | Just use ep->maxpacket to get the maxpacket size and simplify the bulk-out maxpacket alignment. Signed-off-by: Roger Quadros <rogerq@ti.com> Tested-by: Steve Rae <srae@broadcom.com>
| * | fastboot: Enable the respective speed endpoints at runtimeRoger Quadros2016-04-25-7/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In a dual speed configuration we need to check at runtime if we want to enable the Full-Speed or High-Speed endpoint. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Steve Rae <srae@broadcom.com> [Test HW: bcm235xx board]
| * | fastboot: Fix wMaxPacketSize for High-Speed IN endpointRoger Quadros2016-04-25-9/+27
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | wMaxPacketSize for IN endpoing in High-Speed must be 512 and not 64. While fixing that we do some clean ups like - use cpu_to_le16(decimal_length) instead of hexadecimal length. - No need to initialize bInterval to 0. Static variables are 0 initialized. - Move descriptor setting from fastboot_add to to fastboot_bind. - check for dual speed configuration before setting the high speed descriptors. Signed-off-by: Roger Quadros <rogerq@ti.com> Tested-by: Steve Rae <srae@broadcom.com> Tested-by: Steve Rae <srae@broadcom.com> [Test HW: bcm235xx board]
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2016-04-25-160/+361
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| * | i2c: designware_i2c: Add support for PCI(e) based I2C cores (x86)Stefan Roese2016-04-25-12/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the PCI(e) based I2C cores. Which can be found for example on the Intel Bay Trail SoC. It has 7 I2C controllers implemented as PCI devices. This patch also adds the fixed values for the timing registers for BayTrail which are taken from the Linux designware I2C driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | i2c: designware_i2c: Add DM supportStefan Roese2016-04-25-26/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds DM support to the designware I2C driver. It currently supports DM and the legacy I2C support. The legacy support should be removed, once all platforms using it have DM enabled. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de>
| * | i2c: designware_i2c: Prepare for DM driver conversionStefan Roese2016-04-25-83/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch prepares the designware I2C driver for the DM conversion. This is mainly done by removing struct i2c_adapter from the functions that shall be used by the DM driver version as well. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de>
| * | i2c: designware_i2c: Integrate set_speed() into dw_i2c_set_bus_speed()Stefan Roese2016-04-25-24/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Integrating set_speed() into dw_i2c_set_bus_speed() will make the conversion to DM easier for this driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de>
| * | i2c: designware_i2c: Add dw_i2c_enable() helper functionStefan Roese2016-04-25-20/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dw_i2c_enable() is used to dis-/en-able the I2C controller. It makes sense to add such a function, as the controller is dis-/en-abled multiple times in the code. Additionally, this function now checks, if the controller is really dis-/en-abled. This code is copied from the Linux I2C driver version. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | i2c: designware_i2c: Add ic_enable_status to ic_regs structStefan Roese2016-04-25-33/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the ic_enable_status register to the i2c_regs struct. Additionally the register offsets are added, to better check, if the offset matches the register description in the datasheet. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de>
| * | dm: core: Add dev_get_addr_ptr() to return a pointer to the reg addressStefan Roese2016-04-25-0/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some platforms (e.g. x86), the return value of dev_get_addr() can't be assigned to a pointer type variable directly. As there might be a difference between the size of fdt_addr_t and the pointer type. On x86 for example, "fdt_addr_t" is 64bit but "void *" only 32bit. So assigning the register base directly in dev_get_addr() results in this compilation warning: warning: cast to pointer from integer of different size This patch introduces the new function dev_get_addr_ptr() that returns a pointer to the 'reg' address that can be used by drivers in this case. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | mtd, ubi: set free_count to zero before walking through erase listHeiko Schocher2016-04-22-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | Set free_count to zero before walking through ai->erase list in wl_init(). As U-Boot has no workqueue/threads, it immediately calls erase_worker(), which increase for each erased block free_count. Without this patch, free_count gets after this initialized to zero in wl_init(), so the free_count variable always has the maybe wrong value 0. Detected this behaviour on the dxr2 board, where the UBI fastmap gets not written when attaching/dettaching on an empty NAND. It drops instead the error message: could not find any anchor PEB With this patch, fastmap gets written on dettach. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-04-20-3/+130
|\ | | | | | | | | | | | | | | | | | | Conflicts: configs/bcm28155_ap_defconfig configs/dra72_evm_defconfig configs/dra74_evm_defconfig configs/ma5d4evk_defconfig Signed-off-by: Tom Rini <trini@konsulko.com>
| * usb: gadget Move: CONFIG_G_DNL_* to KconfigSam Protsenko2016-04-20-1/+14
| | | | | | | | | | | | And also reformat defconfigs using "make savedefconfig" rule. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
| * usb: dwc3: Move CONFIG_USB_DWC3_PHY_* to KconfigSam Protsenko2016-04-20-0/+17
| | | | | | | | Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
| * usb: dwc3: Move CONFIG_USB_DWC3_OMAP to KconfigSam Protsenko2016-04-20-0/+10
| | | | | | | | Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
| * usb: dwc3: Move CONFIG_USB_DWC3_GADGET/HOST to KconfigSam Protsenko2016-04-20-0/+23
| | | | | | | | | | | | Description was borrowed from kernel dwc3 Kconfig. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
| * usb: gadget: Move CONFIG_USB_GADGET_DOWNLOAD to KconfigSam Protsenko2016-04-20-0/+6
| | | | | | | | | | | | | | While at it, remove obsolete CONFIG_USBDOWNLOAD_GADGET option from some config headers. This is also probably fixes am335x_baltos board. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
| * usb: gadget: Move CONFIG_USB_GADGET_DUALSPEED to KconfigSam Protsenko2016-04-20-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move CONFIG_USB_GADGET_DUALSPEED option to Kconfig and make all UDC controllers select USB_GADGET_DUALSPEED: - add next options to Kconfig selecting USB_GADGET_DUALSPEED: - USB_GADGET_ATMEL_USBA - USB_GADGET_DWC2_OTG - USB_DWC3 - CI_UDC - make USB_MUSB_GADGET select USB_GADGET_DUALSPEED While at it, make some related fixes: - remove DUALSPEED from configs that don't enable gadget support: - kwb.h - tseries.h - add missing USB_GADGET option to next configs: - novena_defconfig - pcm051_rev*_defconfig - xfi3_defconfig Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
| * usb: gadget: Move CONFIG_USB_GADGET_VBUS_DRAW to KconfigSam Protsenko2016-04-20-0/+21
| | | | | | | | | | | | | | | | | | | | | | The description was borrowed from kernel. Definitions were added to defconfig files in a way that "make savedefconfig" generates exactly the same file as used defconfig. Boards using 0 mA as CONFIG_USB_GADGET_VBUS_DRAW value were moved to use 2 mA (as minimal allowed by Kconfig). Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
| * USB: g_dnl: Change device classJohn Tobias2016-04-20-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB Mass Storage (ums) works in Windows, Linux and OS X (EL Capitan). But, not in OS X (Yosemite). By applying the said patch, it extends the ums support. Signed-off-by: John Tobias <john.tobias.ph@gmail.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Test HW: Odroid XU3 (./test/py UMS + DFU tests) Tested-by: John Tobias <john.tobias.ph@gmail.com> Linux: - Run ums to expose all my eMMC partition - shows all correctly - Run ums to expose only 1 partition of my eMMC - show correctly Windows: - Run ums to expose all my eMMC partition - it detects but it prompts, if I want to format it (due to a non windows partition) - Run ums to expose only the FAT32 partition - it show the partition correctly.
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-04-20-87/+97
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| * | ddr: altera: Repair DQ window centering codeMarek Vasut2016-04-20-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code uses a lot of signed numbers, which ended up in variables of unsigned type, which resulted in all sorts of underflows. This in turn caused incorrect calibration on certain boards. Moreover, repair the readout of the DQ delay, which was being pulled from wrong register. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
| * | ddr: altera: Staticize global variablesMarek Vasut2016-04-20-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Just staticize global variables in sequencer, since there is no point in having these symbols available outside of the DDR code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
| * | ddr: altera: Make DLEVEL behavior inclusiveMarek Vasut2016-04-20-66/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Originally, the DLEVEL selects the debug level within the sequencer code, but only displays the messages on that particular debug level. Tweak the handling such that for particular debug level, debug messages on that level and lower are displayed. This allows better regulation of debug message verbosity. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
| * | ddr: altera: Zero DM IN delay in scc_mgr_zero_group()Marek Vasut2016-04-20-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | This one last set of delay configuration registers was not properly zeroed out originally, fix it and zero them out. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
| * | ddr: altera: Remove unnecessary ODT mode configMarek Vasut2016-04-20-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no point in resetting the ODT setting if the write test failed, since the code will always retry the calibration and thus reconfigure the ODT anyway OR the code will fail calibration and halt. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
| * | ddr: altera: Remove unnecessary update of the SCCMarek Vasut2016-04-20-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Every invocation of the scc_mgr_set_dqs_en_delay_all_ranks() is followed by SCC manager update. Moreover, only this function triggers the SCC manager update internally. Thus, remove the internal invocation to avoid triggering the update twice. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
| * | ddr: altera: Fix DRAM end value in protection ruleMarek Vasut2016-04-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hi address bitfield in the protection rule must be set to the last address in the region which the rule represents. The behavior is now in-line with code generated by Quartus 15.1 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
| * | ddr: altera: Fix scc_mgr_set() argument orderMarek Vasut2016-04-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code should be setting registers to zero, not one register to value. Swap the order of arguments to correct the behavior. The behavior is now in-line with code generated by Quartus 15.1 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
| * | ddr: altera: Tweak DQS tracking enable handlingMarek Vasut2016-04-20-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the most unlikely case the DQS tracking was to be disabled, make sure we do not errornously re-enable it. Note that DQS tracking is enabled on all systems observed thus far. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
| * | ddr: altera: Replace ad-hoc constant with macroMarek Vasut2016-04-20-2/+2
| |/ | | | | | | | | | | | | | | | | The bit 22 is in fact DQS tracking enable bit (dqstrken) and there is a macro for this bit already, so use it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* | ahci: flush dcache before issuing commandTang Yuantian2016-04-18-0/+1
| | | | | | | | | | | | | | Ensure data the following sata command used is flushed out of dcache and written to physical memory or timeout error may happen. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
* | serial: bcm283x_mu: make pending values more explicitStephen Warren2016-04-18-2/+2
| | | | | | | | | | | | | | | | | | | | dm_serial_ops.pending should return the number of characters, not just a valid C Boolean integer value. The existing code does already does this, but only as an accident since BCM283X_MU_LSR_RX_READY happens to be BIT(0). Enhance the code to be more explicit about the values it returns. Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | memory: Move TI_AEMIF config to KCONFIGLokesh Vutla2016-04-18-0/+20
| | | | | | | | | | | | | | | | | | | | Not all Keystone2 devices has AEMIF NAND controller. So adding Kconfig entry for CONFIG_TI_AEMIF and enabling it in respective defconfigs on platforms with AEMIF controller. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | drivers/power/pmic/pm8916.c: Make usid be uint32_tTom Rini2016-04-18-1/+1
| | | | | | | | | | | | | | | | | | If get_dev_addr fails it will return FDT_ADDR_T_NONE and: >>> "priv->usid == 4294967295U" is always false regardless of the values of its operands. This occurs as the logical operand of if. Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reported-by: Coverity (CID: 143914) Signed-off-by: Tom Rini <trini@konsulko.com>
* | drivers/gpio/pm8916_gpio.c: Make pid be uint32_tTom Rini2016-04-18-1/+1
| | | | | | | | | | | | | | | | | | If get_dev_addr fails it will return FDT_ADDR_T_NONE and: >>> "priv->pid == 4294967295U" is always false regardless of the values of its operands. This occurs as the logical operand of if. Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reported-by: Coverity (CID: 143913) Signed-off-by: Tom Rini <trini@konsulko.com>
* | drivers: mmc: omap_hsmmc: request cd and wp gpios when DM_MMC is definedMugunthan V N2016-04-18-0/+5
| | | | | | | | | | | | | | | | Add request gpio for CD and WP gpios, so that the gpio can be used for the respective purposes. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | drivers: mmc: omap_hsmmc: Fix conversion of address to a pointerMugunthan V N2016-04-18-1/+2
|/ | | | | | | | | | | | | | | | | omap_hsmmc driver directly typecasts fdt_addr_t to a pointer. This is not strictly correct, as it gives a build warning when fdt_addr_t is u64. So, use map_physmem for a proper typecasts. This is inspired by commit 167efe01bc5a9 ("dm: ns16550: Use an address instead of a pointer for the uart base") drivers/mmc/omap_hsmmc.c: In function ‘omap_hsmmc_ofdata_to_platdata’: drivers/mmc/omap_hsmmc.c:776:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] priv->base_addr = (struct hsmmc *)dev_get_addr(dev); ^ Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* drivers/tpm/tpm_tis_sandbox.c: Fix uninitialized variable useTom Rini2016-04-15-1/+1
| | | | | | | | | | In rollback_space_kernel we were not initializing the reserved fields which should be for safety sake, and doing memset here means we don't need to set the version field specifically either. Reported-by: Coverity (CID: 143917) Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* fdt: implement dev_get_addr_name()Stephen Warren2016-04-15-0/+16
| | | | | | | | | This function parses the reg property based on an index found in the reg-names property. This is required for bindings that are written using reg-names rather than hard-coding indices in reg. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: device.c: Minor coding-style fixStefan Roese2016-04-14-6/+6
| | | | | | | | Fix multi-line comment indentation in device_bind() Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: core: device: set pinctrl state for pinctrl devicePeng Fan2016-04-14-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We may have pinmux settings for pinctrl device, like the following example: " &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog_1>; imx6ul-evk { pinctrl_hog_1: hoggrp-1 { fsl,pins = < MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 >; }; [......] }; " We should not only select pinctrl state for non pinctrl devices, we need also to handle pin mux settings such as pinctrl_log for pinctrl devices. So at the end of probing process of pinctrl device, select the default state of pinctrl device. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit v1.1 at 2024-11-09 20:19:25 +0000