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* Merge git://git.denx.de/u-boot-mpc85xxTom Rini2016-07-21-0/+41
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| * powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPLSumit Garg2016-07-21-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2016-07-21-0/+31
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| * serial_sh: Add standrad SCI (w/o FIFO) supportYoshinori Sato2016-07-09-0/+3
| | | | | | | | | | | | | | Add support for standard type SCI (without FIFO) port. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * serial_sh: Device Tree supportYoshinori Sato2016-07-09-0/+28
| | | | | | | | | | | | | | Add Device Tree bindings. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | mtd: cfi_flash: fix polling for bit XSR.7 on Intel chipsDaniel Schwierzeck2016-07-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flash_full_status_check() checks bit XSR.7 on Intel chips. This should be done by only checking bit 7 and not by comparing the whole status byte or word with 0x80. This fixes the non-working block erase in the pflash emulation of Qemu when used with the MIPS Malta board. MIPS Malta uses x32 mode to access the pflash device. In x32 mode Qemu mirrors the lower 16 bits of the status word into the upper 16 bits. Thus the CFI driver gets a status word of 0x8080 in x32 mode. If flash_full_status_check() uses flash_isequal(), then it polls for XSR.7 by comparing 0x8080 with 0x80 which never becomes true. Reported-by: Alon Bar-Lev <alon.barlev@gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Various, unrelated tree-wide typo fixes.Robert P. J. Day2016-07-16-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-07-15-22/+1100
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| * | sunxi: Use BROM stored boot_media value to determine our boot-sourceHans de Goede2016-07-15-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we know that the BROM stores a value indicating the boot-source at the beginning of SRAM, use that instead of trying to recreate the BROM's boot probing. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | net: Add EMAC driver for H3/A83T/A64 SoCs.Amit Singh Tomar2016-07-15-0/+799
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: mmc: increase status register polling rate for data transfersTobias Doerffel2016-07-15-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With a recent bunch of SD3.0 cards in our A20-based board we experienced data transfer rates of about 250 KiB/s instead of 10 MiB/s with previous cards from the same vendor (both 4 GB/class 10). By increasing status register polling rate from 1 kHz to 1 MHz we were able to reach the original transfer rates again. With the old cards we now even reach about 16 MiB/s. Signed-off-by: Tobias Doerffel <tobias.doerffel@ed-chemnitz.de> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Support booting from SPI flashSiarhei Siamashka2016-07-15-0/+296
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner devices support SPI flash as one of the possible bootable media type. The SPI flash chip needs to be connected to SPI0 pins (port C) to make this work. More information is available at: https://linux-sunxi.org/Bootable_SPI_flash This patch adds the initial support for booting from SPI flash. The existing SPI frameworks are not used in order to reduce the SPL code size. Right now the SPL size grows by ~370 bytes when CONFIG_SPL_SPI_SUNXI option is enabled. While there are no popular Allwinner devices with SPI flash at the moment, testing can be done using a SPI flash module (it can be bought for ~2$ on ebay) and jumper wires with the boards, which expose relevant pins on the expansion header. The SPI flash chips themselves are very cheap (some prices are even listed as low as 4 cents) and should not cost much if somebody decides to design a development board with an SPI flash chip soldered on the PCB. Another nice feature of the SPI flash is that it can be safely accessed in a device-independent way (since we know that the boot ROM is already probing these pins during the boot time). And if, for example, Olimex boards opted to use SPI flash instead of EEPROM, then they would have been able to have U-Boot installed in the SPI flash now and boot the rest of the system from the SATA hard drive. Hopefully we may see new interesting Allwinner based development boards in the future, now that the software support for the SPI flash is in a better shape :-) Testing can be done by enabling the CONFIG_SPL_SPI_SUNXI option in a board defconfig, then building U-Boot and finally flashing the resulting u-boot-sunxi-with-spl.bin binary over USB OTG with a help of the sunxi-fel tool: sunxi-fel spiflash-write 0 u-boot-sunxi-with-spl.bin The device needs to be switched into FEL (USB recovery) mode first. The most suitable boards for testing are Orange Pi PC and Pine64. Because these boards are cheap, have no built-in NAND/eMMC and expose SPI0 pins on the Raspberry Pi compatible expansion header. The A13-OLinuXino-Micro board also can be used. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2016-07-15-63/+85
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| * | | mmc: exynos_dw_mmc: support the Driver mode for ExynosJaehoon Chung2016-07-12-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch support the driver mode for exynos dwmmc controller. To support the legacy model, maintained the existing code. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | mmc: exynos_dw_mmc: use the 4bit bus-width by defaultJaehoon Chung2016-07-12-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If there is not "samsung,bus-width" property, use the 4bit buswidth by default. Almost all Exnyos SoCs support at least 4bit buswidth. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | mmc: exynos_dw_mmc: clean the unused and unnecessary codesJaehoon Chung2016-07-12-22/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean the unused and unnecessary codse. This patch is one of them for preparing to use DM. Because it's easy to maintain and combine DM after cleaning codes. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | mmc: exynos_dw_mmc: add the error control for checking indexJaehoon Chung2016-07-12-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PERIPH_ID_SDMMC4(131) is not continous value with PERIPH_ID_SDMMC0(75). If there is no 'index' property in fdt, then dev_index should be assigned to dev_id(Peripheral ID). At this time, dev_index should be "56". It means Exynos SoC has "56" numbers of DWMMC IP. To prevent this behavior, it needs to check the maximum device index. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | mmc: exynos_dw_mmc: remove #ifdef for OF_CONTROLJaehoon Chung2016-07-12-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removed #ifdef for OF_CONTROL. It might use 'OF_CONTROL' by default. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | mmc: exynos_dw_mmc: remove the unused functionJaehoon Chung2016-07-12-36/+0
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | This function have maintained for supporting Non-FDT. Now, Almost all SoC are changed to fdt style. So there are no that this function is called anywhere. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | Merge git://git.denx.de/u-boot-dmTom Rini2016-07-15-54/+324
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| * | | rockchip: pinctrl: Update the rk3288 driver to support of-platdataSimon Glass2016-07-14-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for of-platdata with rk3288. This requires disabling access to the device tree and renaming the driver to match the string that of-platdata will search for. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | rockchip: clk: Update the rk3288 driver to support of-platdataSimon Glass2016-07-14-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for of-platdata with rk3288. This requires decoding the of-platdata struct and setting up the devices from that. Also the driver needs to be renamed to match the string that of-platdata will search for. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | rockchip: clk: Move all DT decoding to ofdata_to_platdata()Simon Glass2016-07-14-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is more correct to avoid touching the device tree in the probe() method. Update the driver to work this way. Also add an error check on grf since if that fails then we should not use it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | rockchip: mmc: Update the driver to support of-platdataSimon Glass2016-07-14-3/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for of-platdata with rk3288. This requires decoding the of-platdata struct and setting up the device from that. Also the driver needs to be renamed to match the string that of-platdata will search for. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | rockchip: mmc: Move all DT decoding to ofdata_to_platdata()Simon Glass2016-07-14-15/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It is more correct to avoid touching the device tree in the probe() method. Update the driver to work this way. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | rockchip: serial: Add an of-platdata driver for rockchipSimon Glass2016-07-14-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver that works with of-platdata. It sets up the platform data and calls the standard ns16550 driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: serial: ns16550: Update to support of-platdataSimon Glass2016-07-14-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With of-platdata this driver cannot know the format of the of-platdata struct, so we cannot use generic code for accessing the of-platdata. Each SoC that uses this driver will need to set up ns16550's platdata for it. So don't compile in the generic code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Add an implementation of regmap_init_mem_platdata()Simon Glass2016-07-14-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an implementation of this function which mirrors the functions of the automatic device-tree implementation. This can be used with of-platdata to create regmaps. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Move regmap allocation into a separate functionSimon Glass2016-07-14-12/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We plan to add a new way of creating a regmap for of-platdata. Move the allocation code into a separate function so that it can be shared. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: Don't bring in the eeprom emulator in SPLSimon Glass2016-07-14-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver should not be used in SPL since we do not have I2C support enabled in SPL on sandbox. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Expand platdata for of-platdata devicesSimon Glass2016-07-14-11/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Devices which use of-platdata have their own platdata. However, in many cases the driver will have its own auto-alloced platdata, for use with the device tree. The ofdata_to_platdata() method converts the device tree settings to platdata. With of-platdata we would not normally allocate the platdata since it is provided by the U_BOOT_DEVICE() declaration. However this is inconvenient since the of-platdata struct is closely tied to the device tree properties. It is unlikely to exactly match the platdata needed by the driver. In fact a useful approach is to declare platdata in the driver like this: struct r3288_mmc_platdata { struct dtd_rockchip_rk3288_dw_mshc of_platdata; /* the 'normal' fields go here */ }; In this case we have dt_platadata available, but the normal fields are not present, since ofdata_to_platdata() is never called. In fact driver model doesn't allocate any space for the 'normal' fields, since it sees that there is already platform data attached to the device. To make this easier, adjust driver model to allocate the full size of the struct (i.e. platdata_auto_alloc_size from the driver) and copy in the of-platdata. This means that when the driver's bind() method is called, the of-platdata will be present, followed by zero bytes for the empty 'normal field' portion. A new DM_FLAG_OF_PLATDATA flag is available that indicates that the platdata came from of-platdata. When the allocation/copy happens, the DM_FLAG_ALLOC_PDATA flag will be set as well. The dtoc tool is updated to output the platdata_size field, since U-Boot has no other way of knowing the size of the of-platdata struct. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Rename DM_NAME_ALLOCED to DM_FLAG_NAME_ALLOCEDSimon Glass2016-07-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This is a flag. Adjust the name to be consistent with the other flags. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: serial: Add support for of-platdataSimon Glass2016-07-14-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When this feature is enabled, we cannot access the device tree to find out which serial device to use. Just use the first serial driver we find. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: clk: Add support for of-platdataSimon Glass2016-07-14-2/+22
| | | | | | | | | | | | | | | | | | | | | | | | Add support for this feature in the core clock code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: sandbox: Add a simple driver to test of-platdataSimon Glass2016-07-14-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver which uses of-platdata to obtain its platform data. This can be used to test the feature in sandbox. It displays the contents of its platform data. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: syscon: Add support for of-platdataSimon Glass2016-07-14-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a new function which can cope with obtaining information from of-platdata instead of the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: regmap: Add a dummy implementation for of-platdataSimon Glass2016-07-14-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a placeholder for now so that this code will compile. It currently does nothing. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Don't use device tree with of-platdataSimon Glass2016-07-14-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_SPL_OF_PLATDATA is enabled we should not access the device tree. Remove all references to this in the core driver-model code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: serial: Don't sync video in SPLSimon Glass2016-07-14-0/+2
| | |/ | |/| | | | | | | | | | | | | | | | SPL does not support an LCD display so there is no need to sync the video when there is serial output. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | rtc: Tidy up the code styleSimon Glass2016-07-14-39/+32
| | | | | | | | | | | | | | | | | | | | | This code generates lots of checkpatch errors. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | stm32: clk: Add 200MHz clock configuration for stm32f746 discovery boardToshifumi NISHINAGA2016-07-14-1/+15
|/ / | | | | | | | | | | | | | | | | This patch adds 200MHz clock configuration for stm32f746 discovery board. This patch is based on STM32F4 and emcraft's[1]. [1]: https://github.com/EmcraftSystems/u-boot Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-07-12-8/+3
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| * | pci: Add board_ prefix to should_load_oprom() and make it weakBin Meng2016-07-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | For consistency with board_should_run_oprom(), do the same to should_load_oprom(). Board support codes can provide this one to override the default weak one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | pci: Make load_oprom and run_oprom independentBin Meng2016-07-12-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | At present should_load_oprom() calls board_should_run_oprom() to determine whether oprom should be loaded. But sometimes we just want to load oprom without running. Make them independent. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | pci: Remove CONFIG_ALWAYS_LOAD_OPROMBin Meng2016-07-12-2/+0
| |/ | | | | | | | | | | | | This option is defined at nowhere. Remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2016-07-11-102/+268
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| * | dm: spi: Read default speed and mode values from DTVignesh R2016-07-09-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of DT boot, don't read default speed and mode for SPI from CONFIG_*, instead read from DT node. This will make sure that boards with multiple SPI/QSPI controllers can be probed at different bus frequencies and SPI modes. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | spi: cadence_quadspi: Enable QUAD mode based on DT dataVignesh R2016-07-09-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD mode, make use of mode_rx field of dm_spi_slave_platdata to determine whether to enable or disable QUAD mode. This is necessary to support muliple SPI controllers where one of them may not support QUAD mode. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | spi: cadence_qspi_apb: Support 32 bit AHB addressVignesh R2016-07-09-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AHB address can be as long as 32 bit, hence remove the CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT and read as u32 value, it anyway does not make sense to mask upper bits. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | spi: davinci_spi: Convert to driver to adapt to DMVignesh R2016-07-09-89/+240
| | | | | | | | | | | | | | | | | | | | | | | | Convert davinci_spi driver so that it complies with SPI DM framework. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
generated by cgit v1.1 at 2024-08-24 13:23:13 +0000