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* dm: core: Don't use pinctrl for the root deviceSimon Glass2015-10-05-2/+6
| | | | | | | | | | | | | | | | | | | | | Currently when driver model starts up it finds the root uclass and the pinctrl uclass. This is because even the root node handles pinctrl processing. But this is not useful. The root node is not a real hardware device so cannot require any particular pinmux settings. Also it means that the memory leak tests fails, since they end up freeing more memory than they allocate: the marker it set after the root device and pinctrl uclass are allocated, and later once the pinctrl uclass is freed the memory used by driver model is less than when the marker was set. If a platform needs 'core' pin mulitplex settings it can do this with a driver that is probed on start-up. It would be an abuse of the root node to use this for pinctrl. To avoid this problem, only process pinctrl settings for non-root nodes. Signed-off-by: Simon Glass <sjg@chromium.org>
* gpio: s5p: call: dev_get_addr() instead of fdtdec_get_addr()Przemyslaw Marczak2015-10-03-7/+11
| | | | | | | | | | | | | | | | | | | | | | After rework in lib/fdtdec.c, the function fdtdec_get_addr() doesn't work for nodes with #size-cells property set to 0. To get GPIO's 'reg' property, the code should use one of: fdtdec_get_addr_size_auto_no/parent() function. Fortunately dm core provides a function to get the property. This commit reworks function gpio_exynos_bind(), to properly use dev_get_addr() for GPIO device. This prevents setting a wrong base register for Exynos GPIOs. Tested on: Odroid U3/X2, Trats, Trats2, Odroid XU3, Snow (by Simon). Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-10-02-32/+26
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| * gpio: tegra: use named constantsStephen Warren2015-10-02-14/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to make it clear what the parameters to set_config() and set_direction() mean, and similarly for the return values from the respective get_*(), define named constants for these values. Disassembly shows no diff in the generated code, except that the order of the code in the branches of tegra_gpio_get_function() gets modified without affecting behaviour. Suggested-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * gpio: tegra: remove unused typeStephen Warren2015-10-02-7/+0
| | | | | | | | | | | | | | | | These enum values aren't used anywhere. Remove them. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: don't enable GPIOs until direction is setStephen Warren2015-10-02-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's GPIO driver currently enables pins as GPIO as soon as they're requested. This is not safe, since the desired direction and output value are not yet known. This could cause a glitch on the output pins between gpio_request() and gpio_direction_*(), depending on what values happen to be in the GPIO controller's in/out and out-value registers vs. the final desired configuration. To solve this, defer enabling pins as GPIOs until some gpio_direction_*() is invoked, and the desired configuration is explicitly programmed. In theory this change could cause regressions, if code exists that claims a GPIO, never explicitly sets a direction, and then gets/sets the GPIO value based on that assumption. However, I've read through all the Tegra- related board files and device drivers that touch GPIOs and I do not see such buggy code anywhere. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: fix GPIO init table programmingStephen Warren2015-10-02-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's gpio_config_table() currently uses common GPIO APIs. These used to work without requesting the GPIO, but since commit 2fccd2d96bad "tegra: Convert tegra GPIO driver to use driver model" no longer do so. This prevents any of the GPIO initialization table from being applied to HW. Fix gpio_config_table() to directly program the HW to solve this. Fixes: 2fccd2d96bad ("tegra: Convert tegra GPIO driver to use driver model") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-10-02-0/+6
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| * | I2C: mxc_i2c: make I2C1 and I2C2 optionalAlbert ARIBAUD \\(3ADEV\\)2015-10-02-0/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver assumed that I2C1 and I2C2 were always enabled, and if they were not, then an asynchronous abort was (silently) raised, to be caught much later on in the Linux kernel. Fix this by making I2C1 and I2C2 optional just like I2C3 and I2C4 are. To make the change binary-invariant, declare I2C1 and I2C2 in every include/configs/ file which defines CONFIG_SYS_I2C_MXC. Also, while updating README about CONFIG_SYS_I2C_MXC_I2C1 and CONFIG_SYS_I2C_MXC_I2C2, add missing descriptions for I2C4 speed (CONFIG_SYS_MXC_I2C4_SPEED) and slave (CONFIG_SYS_MXC_I2C4_SLAVE) config options. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2015-09-30-4/+12
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| * | net: fix netconsole when CONFIG_DM_ETH is setBernhard Nortmann2015-09-29-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | This patch uses the eth_is_active() function to work around issues that prevented compilation with the newer driver model. Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: on phy device create do not initialize link to 1Mugunthan V N2015-09-29-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently when phy device is created the link variable is initialized to 1 which denoted phy link is already up. On a power reset there is no issue as phy status register link status will not be set, so phy auto negotiate will be started. But when a cpu reset is issued (ex: dra72x-evm) phy's link status bit is already set which leads to assume that link is already setup in genphy_update_link() initial check which results in ehternet not working. So do not assume that link is already up and on phy device create set link to zero. This is verified on dra72x-evm. Reported-by: Franklin S Cooper Jr <fcooper@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | sunxi: mmc: Fix clk-delay settingsHans de Goede2015-09-29-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In recent allwinner kernel sources the mmc/sdio clk-delay settings have been slightly tweaked, and for sun9i they are completely different then what we are using. This commit brings us in sync with what allwinner does, fixing problems accessing sdcards on some A33 devices (and likely others). For pre sun9i hardware this makes the following changes: -At 400Khz change the sample delay from 7 to 0 (first introduced in A31 sdk) -At 50 Mhz change the sample delay from 5 to 4 (first introduced in A23 sdk) -Above 50 MHz change the out delay from 2 to 1 (first introduced in A20 sdk) Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi_nand_spl: Be smarter about where to look for backup u-boot.binHans de Goede2015-09-29-6/+20
|/ | | | | | | | | | | | | | | | | | We know when u-boot is written to its own partition, in this case the layout always is: eb 0 spl eb 1 spl-backup eb 2 u-boot eb 3 u-boot-backup eb: erase-block So if we cannot load u-boot from its primary offset we know exactly where to look for it. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* mmc: dw_mmc: Increase timeout to 4 minutes (as in Linux kernel)Łukasz Majewski2015-09-28-1/+1
| | | | | | | | | | | | | | | | | | | | The commit: d9dbb97be0e4a550457aec5f11afefb446169c90 "mmc: dw_mmc: Zap endless timeout" removed endless loop waiting for end of dw mmc transfer. For some workloads - dfu test @ Odroid XU3 (sending 8MiB file) - and SD cards (e.g. MicroSD Kingston 4GiB, Adata 4GiB) the default timeout is to short. The new value - 4 minutes (240 seconds) - is the same as the one used in Linux kernel driver. Such fix should be good enough until we come up with better fix for this issue. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-09-24-2/+10
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| * mtd: nand: mxs check maximum ecc that platfrom supportsPeng Fan2015-09-20-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | Check maximum ecc strength for each platfrom to avoid the calculated ecc exceed the limitation. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Han Xu <b45815@freescale.com> Tested-By: Tim Harvey <tharvey at gateworks.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: wdog: correct wcr register settingsPeng Fan2015-09-20-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | We should not simple use "writew(WCR_WDE, &wdog->wcr)" to set wcr, since this will override bits set before reset_cpu. Use clrsetbits_le16 instead of writew to fix this issue. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Sebastian Siewior <bigeasy@linutronix.de> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2015-09-24-0/+1142
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| * | ARM: uniphier: rename CONFIG_MACH_* to CONFIG_ARCH_UNIPHIER_*Masahiro Yamada2015-09-25-6/+6
| | | | | | | | | | | | | | | | | | | | | I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify they belong to UniPhier SoC family. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: add UniPhier PH1-LD6b pinctrl driverMasahiro Yamada2015-09-25-0/+140
| | | | | | | | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD6b SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: add UniPhier ProXstream2 pinctrl driverMasahiro Yamada2015-09-25-0/+147
| | | | | | | | | | | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier ProXstream2 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: add UniPhier PH1-Pro5 pinctrl driverMasahiro Yamada2015-09-25-0/+151
| | | | | | | | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier PH1-Pro5 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: add UniPhier PH1-sLD8 pinctrl driverMasahiro Yamada2015-09-25-0/+148
| | | | | | | | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier PH1-sLD8 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: add UniPhier PH1-Pro4 pinctrl driverMasahiro Yamada2015-09-25-0/+137
| | | | | | | | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier PH1-Pro4 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: add UniPhier PH1-LD4 pinctrl driverMasahiro Yamada2015-09-25-0/+141
| | | | | | | | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD4 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: add UniPhier pinctrl core supportMasahiro Yamada2015-09-23-0/+278
| | | | | | | | | | | | | | | | | | | | | The core support for the pinctrl drivers for all the UniPhier SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-09-22-234/+1998
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| * | drivers/net/vsc9953: Add GPL-2.0+ SPDX-License-IdentifierCodrin Ciubotariu2015-09-21-1/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Add commands for VLAN ingress filteringCodrin Ciubotariu2015-09-21-0/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The command: ethsw [port <port_no>] ingress filtering { [help] | show | enable | disable } - enable/disable VLAN ingress filtering on port can be used to enable/disable/show VLAN ingress filtering on a port. This command has also been added to the ethsw generic parser from common/cmd_ethsw.c Signed-off-by: Johnson Leung <johnson.leung@freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Add command for shared/private VLAN learningCodrin Ciubotariu2015-09-21-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The command: ethsw vlan fdb { [help] | show | shared | private } - make VLAN learning shared or private" configures the FDB to share the FDB entries learned on multiple VLANs or to keep them separated. By default, the FBD uses private VLAN learning. This command has also been added to the ethsw generic parser from common/cmd_ethsw.c Signed-off-by: Johnson Leung <johnson.leung@freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Add VLAN commands for VSC9953Codrin Ciubotariu2015-09-21-0/+478
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new added commands can be used to configure VLANs for a port on both ingress and egress. The new commands are: ethsw [port <port_no>] pvid { [help] | show | <pvid> } - set/show PVID (ingress and egress VLAN tagging) for a port; ethsw [port <port_no>] vlan { [help] | show | add <vid> | del <vid> } - add a VLAN to a port (VLAN members); ethsw [port <port_no>] untagged { [help] | show | all | none | pvid } - set egress tagging mod for a port" ethsw [port <port_no>] egress tag { [help] | show | pvid | classified } - Configure VID source for egress tag. Tag's VID could be the frame's classified VID or the PVID of the port These commands have also been added to the ethsw generic parser from common/cmd_ethsw.c Signed-off-by: Johnson Leung <johnson.leung@freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Add commands to manipulate the FDB for VSC9953Codrin Ciubotariu2015-09-21-0/+472
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new command: ethsw [port <port_no>] [vlan <vid>] fdb { [help] | show | flush | { add | del } <mac> } Can be used to add and delete FDB entries. Also, the command can be used to show entries from the FDB tables. When used with [port <port_no>] and [vlan <vid>], only the matching the FDB entries can be seen or flushed. The command has also been added to the generic ethsw parser from cmd_ethsw.c. Signed-off-by: Johnson Leung <johnson.leung@freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Add commands to enable/disable HW learningCodrin Ciubotariu2015-09-21-0/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The command: ethsw [port <port_no>] learning { [help] | show | auto | disable } can be used to enable/disable HW learning on a port. This patch also adds this command to the generic ethsw parser from cmd_ethsw. Signed-off-by: Johnson Leung <johnson.leung@freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Add command to show/clear port countersCodrin Ciubotariu2015-09-21-0/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new added command: ethsw [port <port_no>] statistics { [help] | [clear] } will print counters like the number of Rx/Tx frames, number of Rx/Tx bytes, number of Rx/Tx unicast frames, etc. This patch also adds this commnd in the genereric ethsw parser from cmd_ethsw.c Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Use the generic Ethernet Switch parserCodrin Ciubotariu2015-09-21-184/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch replaces the parser used by VSC9953 L2 Switch driver with the generic one. Also, the config macro that enables the VSC9953 commands has been replaced in all the platforms that use this driver with the config macro that corresponds to the generic parser. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Add default configuration for VSC9953 L2 SwitchCodrin Ciubotariu2015-09-21-0/+253
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At startup, the default configuration should be: - enable HW learning on all ports (HW default); - all ports are VLAN aware; - all ports are members of VLAN 1; - all ports have Port-based VLAN 1; - on all ports, the switch is allowed to remove maximum one VLAN tag, - on egress, the switch should add a VLAN tag if the frame is classified to a different VLAN than the port's Port-based VLAN; Signed-off-by: Johnson Leung <johnson.leung@freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Fix bug when enabling a portCodrin Ciubotariu2015-09-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a port is enabled at init time, the initializing function touches more bits than necessary to enable a port (also touches reserved bits and default bit values). This patch fixes this issue by changing the value of the define used to enable the port and assures that no other bits are changes by replacing out_le32() with setbits_le32(). Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Cleanup patchCodrin Ciubotariu2015-09-21-71/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch groups some macros defined for registers and replaces some magic numbers from vsc9953 with macros. Also, "port" and "port_nr" words are replaced with "port_no", puts each variable declaration on a line and removes unnecessary tabs. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Remove 'CONFIG_' from macros' nameCodrin Ciubotariu2015-09-21-19/+19
| |/ | | | | | | | | | | Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | pinctrl: move dm_scan_fdt_node() out of pinctrl uclassMasahiro Yamada2015-09-19-6/+17
|/ | | | | | | | | | | | | | | | | | | | | Commit c5acf4a2b3c6 ("pinctrl: Add the concept of peripheral IDs") added some additional change that was not mentioned in the git-log. That commit added dm_scan_fdt_node() in the pinctrl uclass binding. It should be handled by the simple-bus driver or the low-level driver, not by the pinctrl framework. I guess Simon's motivation was to bind GPIO banks located under the Rockchip pinctrl device. It is true some chips have sub-devices under their pinctrl devices, but it is basically SoC-specific matter. This commit partly reverts commit c5acf4a2b3c6 to keep the only pinctrl-generic features in the uclass. The dm_scan_fdt_node() should be called from the rk3288_pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* net: designware: Add support to PCI designware devicesBin Meng2015-09-16-0/+42
| | | | | | | | The Designware ethernet controller is also seen on PCI bus, e.g. on Intel Quark SoC. Add this support in the DM version driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Add an inline API to test if a device is on a PCI busBin Meng2015-09-16-2/+2
| | | | | | | | Introduce device_is_on_pci_bus() which can be utilized by driver to test if a device is on a PCI bus. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-fdtTom Rini2015-09-16-1/+4
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| * fdt: add new fdt address parsing functionsStephen Warren2015-09-15-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fdtdec_get_addr_size() hard-codes the number of cells used to represent an address or size in DT. This is incorrect in many cases depending on the DT binding for a particular node or property (e.g. it is incorrect for the "reg" property). In most cases, DT parsing code must use the properties #address-cells and #size-cells to parse addres properties. This change splits up the implementation of fdtdec_get_addr_size() so that the core logic can be used for both hard-coded and non-hard-coded cases. Various wrapper functions are implemented that support cases where hard-coded cell counts should or should not be used, and where the client does and doesn't know the parent node ID that contains the properties #address-cells and #size-cells. dev_get_addr() is updated to use the new functions. Core functionality in fdtdec_get_addr_size_fixed() is widely tested via fdtdec_get_addr_size(). I tested fdtdec_get_addr_size_auto_noparent() and dev_get_addr() by manually modifying the Tegra I2C driver to invoke them. Much of the core implementation of fdtdec_get_addr_size_fixed(), fdtdec_get_addr_size_auto_parent(), and fdtdec_get_addr_size_auto_noparent() comes from Thierry Reding's previous commit "fdt: Fix fdtdec_get_addr_size() for 64-bit". Based-on-work-by: Thierry Reding <treding@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Simon Glass <sjg@chromium.org> Cc: Michal Suchanek <hramrach@gmail.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Dropped #define DEBUG at the top of fdtdec.c: Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove unused ST-Ericsson u8500 archStefan Roese2015-09-15-803/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This arch does not seem to be supported / used at all in the current U-Boot mainline source tree any more. So lets remove the core u8500 code and code that was only referenced by this platform. Please note that this patch also removes these config options: - CONFIG_PL011_SERIAL_RLCR - CONFIG_PL011_SERIAL_FLUSH_ON_INIT As they only seem to be referenced by u8500 based boards. Without any such board in the current code, these config option don't make sense any more. Lets remove them as well. If someone still wants to use this platform, then please send patches to re-enable support by adding at least one board that references this code. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: John Rigby <john.rigby@linaro.org> Cc: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Tom Rini <trini@konsulko.com> Cc: Heiko Schocher <hs@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | mtd: nand: fsmc: Fixes and cleanup for fsmc_nand_switch_ecc()Stefan Roese2015-09-15-6/+15
|/ | | | | | | | | | | | | | | | | | | This patch addresses some comments raised by Scott in the last versions. Here the changes in detail: - Removed __maybe_unused as its not needed - Added check for strength == 4 and error out for the unsupported ECC strength values - Don't set .caclulate, .correct, and .bytes for NAND_ECC_SOFT_BCH as this will be done in nand_scan_tail() - Set .caclulate back to fsmc_read_hwecc() in the HW case - Added comment that this function will only be called on SPEAr platforms, not supporting the BCH8 HW ECC (FSMC_VER8) Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Cc: Tom Rini <trini@konsulko.com> Acked-by: Scott Wood <scottwood@freescale.com>
* Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2015-09-13-10/+36
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| * serial: serial-sh: SCIFA interface for R-Car Gen2 SoCsVladimir Barinov2015-08-31-9/+34
| | | | | | | | | | | | | | | | | | Add SCIFA console interface for R-Car Gen2 SoCs. SCIFA has different registers offsets and sizes then SCI. Hence it needs to put it's macro definitions separately. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * gpio: sh-pfc: fix gpio input readVladimir Barinov2015-08-31-1/+2
| | | | | | | | | | | | | | | | Fix gpio_read: gpio input (INDT) and gpio output (OUTDT) registers have different offset. gpio_read must be performed from INDT. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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