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* | gpio: dwapb: Add support for port BPhil Edworthy2016-11-21-10/+10
|/ | | | | | | | | | The IP supports two ports, A and B, each providing up to 32 gpios. The driver already creates a 2nd gpio bank by reading the 2nd node from DT, so this is quite a simple change to support the 2nd bank. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of http://git.denx.de/u-boot-mmcTom Rini2016-11-17-5/+12
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| * mmc: sunxi: Enable 8bits bus width for sun8iMaxime Ripard2016-11-16-1/+1
| | | | | | | | | | | | | | | | | | The sun8i SoCs also have a 8 bits capable MMC2 controller. Enable the support for those too. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
| * mmc: Retry the switch commandMaxime Ripard2016-11-16-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | Some eMMC will fail at the first switch, but would succeed in a subsequent one. Make sure we try several times to cover those cases. The number of retries (and the behaviour) is currently what is being used in Linux. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge tag 'signed-efi-next' of git://github.com/agraf/u-bootTom Rini2016-11-17-2/+22
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch queue for efi - 2016-11-17 Highlights this time around: - x86 efi_loader support - hello world efi test case - network device name is now representative - terminal output reports modes correctly - fix psci reset for ls1043/ls1046 - fix efi_add_runtime_mmio definition for x86 - efi_loader support for ls2080
| * | ls2080: Exit dpaa only right before exiting U-BootAlexander Graf2016-11-17-2/+22
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ls2080 we have a separate network fabric component which we need to shut down before we enter Linux (or any other OS). Along with that also comes configuration of the fabric using a description file. Today we always stop and configure the fabric in the boot script and (again) exit it on device tree generation. This works ok for the normal booti case, but with bootefi the payload we're running may still want to access the network. So let's add a new fsl_mc command that defers configuration and stopping the hardware to when we actually exit U-Boot, so that we can still use the fabric from an EFI payload. For existing boot scripts, nothing should change with this patch. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> [agraf: Fix x86 build]
* | net: zynq_gem: Correct SGMII enable bit settingSiva Durga Prasad Paladugu2016-11-15-1/+1
| | | | | | | | | | | | | | | | | | Correct the SGMII enable bit position to 27 instead of 31. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: zynq_gem: Modify the nwcfg bit definitionsSiva Durga Prasad Paladugu2016-11-15-8/+8
| | | | | | | | | | | | | | | | | | Modify the nwcfg bit definitions to have 32-bit by removing the extra nibble. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | nand: arasan_nfc: Clear ecc on bit while sending read commandSiva Durga Prasad Paladugu2016-11-15-0/+2
| | | | | | | | | | | | | | | | | | | | Clear ecc ON bit while sending read command as all types of read command(like reading spare) doesnt need ECC to be enabled. It has been anyway taken care in other places whereever required using arasan_nand_enable_ecc(). Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | mtd: nand: zynq_nand: Add nand driver support for zynqSiva Durga Prasad Paladugu2016-11-15-0/+1194
|/ | | | | | | Add nand flash controller driver support for zynq SoC. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* video: bmp: Fix compilation errors with CONFIG_BMP_xxBPP enabledStefan Roese2016-11-13-3/+3
| | | | | | | | | | | | | | | | | | | | | Compiling the 'bmp' command with DM and having one of the following macros enabled: CONFIG_BMP_16BPP, CONFIG_BMP_24BPP ONFIG_BMP_32BPP generates this error: drivers/video/video_bmp.c: In function ‘video_bmp_display’: drivers/video/video_bmp.c:315:22: error: ‘lcd_line_length’ undeclared (first use in this function) fb -= width * 2 + lcd_line_length; ^ This patch moves to using the correct variable instead and enables the 'bmp' command for DM again. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Anatolij Gustschin <agust@denx.de>
* spi: ti_qspi: Fix baudrate divider calculationVignesh R2016-11-13-9/+7
| | | | | | | | | Fix the divider calculation logic to choose a value so that the resulting baudrate is either equal to or closest possible baudrate less than the requested value. While at that, cleanup ti_spi_set_speed(). Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* net: mvgbe: Fix build error with CONFIG_PHYLIBChris Packham2016-11-07-22/+3
| | | | | | | | | | | | | | Commit 5a49f17481bb ("net: mii: Use spatch to update miiphy_register") updated the mvgbe implementation of smi_reg_read/smi_reg_write. Prior to that change mvgbe_phy_read and mvgbe_phy_write where used as wrappers to satisfy the phylib APIs. Because these functions weren't updated in that commit build errors where triggered when CONFIG_PHYLIB was enabled. Fix these build errors by removing mvgbe_phy_read and mvgbe_phy_write and using smi_reg_read/smi_reg_write directly. Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: micrel: center FLP burst timing at 16msAsh Charles2016-11-07-0/+23
| | | | | | | | | | | | | Like [1], reset the FLP burst timing for the KSZ9031 to the 16ms specified by the IEEE802.3 standard from the chip's default of 8ms. For more details, see the "Auto-Negotiation Timing" section of the KSZ9031RNX datasheet. [1] https://patchwork.kernel.org/patch/6558371/ Signed-off-by: Ash Charles <ash.charles@savoirfairelinux.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: add driver for Synopsys Ethernet QoS deviceStephen Warren2016-11-07-0/+1564
| | | | | | | | | | | | | | This driver supports the Synopsys Designware Ethernet QoS (Quality of Service) a/k/a eqos IP block, which is a different design than the HW supported by the existing designware.c driver. The IP supports many options for bus type, clocking/reset structure, and feature list. This driver currently supports the specific configuration used in NVIDIA's Tegra186 chip, but should be extensible to other combinations quite easily, as explained in the source. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> # V1 Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-11-03-1/+1
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| * dfu: align array in dfu_get_dev_type with enum dfu_device_typePatrick Delaunay2016-11-03-1/+1
| | | | | | | | Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2016-11-02-67/+2
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| * rockchip: rk3288: Move rockchip_get_cru() out of the driverSimon Glass2016-10-30-21/+0
| | | | | | | | | | | | | | | | This function is called from outside the driver. It should be placed into common SoC code. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3399: Move rockchip_get_cru() out of the driverSimon Glass2016-10-30-25/+1
| | | | | | | | | | | | | | | | | | | | | | This function is called from outside the driver. It should be placed into common SoC code. Move it. Also rename the driver symbol to be more consistent with the other rockchip clock drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3036: Move rockchip_get_cru() out of the driverSimon Glass2016-10-30-23/+1
| | | | | | | | | | | | | | | | | | | | | | This function is called from outside the driver. It should be placed into common SoC code. Move it. Also rename the driver symbol to be more consistent with the other rockchip clock drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * clk: rk3399: fix rockchip_get_cruJacob Chen2016-10-30-1/+3
| | | | | | | | | | | | | | clk_rk3399 is driver name, not device name Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Fix spelling of "resetting".Vagrant Cascadian2016-10-31-3/+3
|/ | | | | | | | Cover-Letter: Fixes several spelling errors for the words "resetting", "extended", "occur", and "multiple". Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-10-30-6/+8
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| * sunxi: A64: enable USB supportAmit Singh Tomar2016-10-30-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mostly by adding MACH_SUN50I to some existing #ifdefs enable support for the the HCI0 USB host controller on the A64. Fix up some minor 64-bit hiccups on the way. Add the bare minimum DT bits to the A64 .dtsi and enable the controllers and the PHY on the Pine64. This is limited to the first USB controller at the moment, which is connected to the lower USB socket on the Pine64 board. [Andre: remove unneeded defines, enable OHCI, add commit message] Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Rename CONFIG_SUNXI to CONFIG_ARCH_SUNXIJagan Teki2016-10-30-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SUNXI -> CONFIG_ARCH_SUNXI and removed CONFIG_SUNIX from config_whitelist.txt Cc: Simon Glass <sjg@chromium.org> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-10-29-0/+3
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| * | dm: mmc: socfpga: fix MMC_OPS supportSylvain Lesne2016-10-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that CONFIG_BLK and CONFIG_MMC_OPS are enabled by default with CONFIG_DM_MMC, the DWMMC driver on the socfpga platform fails at runtime. This adds the missing fields in the driver declaration. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | ddr: altera: Configuring SDRAM extra cycles timing parametersChin Liang See2016-10-27-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-10-29-33/+21
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| * | drivers: USB: OHCI: allow compilation for 64-bit targetsAndre Przywara2016-10-29-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OHCI has a known limitation of allowing only 32-bit DMA buffer addresses, so we have a lot of u32 variables around, which are assigned to pointers and vice versa. This obviously creates issues with 64-bit systems, so the compiler complains here and there. To allow compilation for 64-bit boards which use only memory below 4GB anyway (and to avoid more invasive fixes), adjust some casts and types and assume that the EDs and TDs are all located in the lower 4GB. This fixes compilation of the OHCI driver for the Pine64. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
| * | usb: xhci-mvebu: use xhci_deregister() for .remove callbackMasahiro Yamada2016-10-27-6/+1
| | | | | | | | | | | | | | | | | | No need to use a wrapper that is equivalent to xhci_deregister(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | usb: ehci-vf: use ehci_deregister() for .remove callbackMasahiro Yamada2016-10-27-12/+1
| |/ | | | | | | | | | | | | | | This driver was recently converted to Driver Model, so missed the subsystem-wide cleanups by commit 405273427366 ("usb: replace ehci_*_remove() with usb_deregister()"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-10-28-178/+540
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| * | dm: at91: Add driver model support for the spi driverWenyou Yang2016-10-28-0/+296
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver model support while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | serial: atmel_usart: Support enable an early debug UARTWenyou Yang2016-10-28-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | Add support to enable an early debug UART for debugging. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | serial: Kconfig: Add ATMEL_USART optionWenyou Yang2016-10-28-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Add ATMEL_USART option to support to enable the Atmel usart driver from Kconfig. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | mmc: atmel_sdhci: Remove unnecessary clock callingWenyou Yang2016-10-28-25/+2
| | | | | | | | | | | | | | | | | | | | | | | | Due to the peripheral and generated clock driver improvement, remove the unnecessary clock calling. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | usb: ehci-atmel: Remove unnecessary clock callingWenyou Yang2016-10-28-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | Due to the peripheral clock driver improvement, remove the unnecessary clock calling. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | i2c: at91_i2c: Change error return -ENODEV to -EINVALWenyou Yang2016-10-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Change the error return value -ENODEV from to -EINVAL for more reasonable. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | i2c: at91_i2c: Remove unnecessary clock callingWenyou Yang2016-10-28-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | Due to the peripheral clock driver improvement, remove the unnecessary clock calling. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | gpio: atmel_pio4: Remove unnecessary clock callingWenyou Yang2016-10-28-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | Due to the peripheral clock driver improvement, remove the unnecessary clock calling. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | clk: at91: Improve the clock implementationWenyou Yang2016-10-28-89/+195
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the peripheral clock, provide the clock ops for the clock provider, such as spi0_clk. The .of_xlate is to get the clk->id, the .enable is to enable the spi0 peripheral clock, the .get_rate is to get the clock frequency. The driver for periph32ck node is responsible for recursively binding its children as clk devices, not provide the clock ops. So do the generated clock and system clock. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | clk: clk-uclass: Assign clk->dev before call .of_xlateWenyou Yang2016-10-28-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to make clk->dev available in ops->of_xlate() to get the clock ID from the 'reg' property of the clock node, assign the clk->dev before calling ops->of_xlate(). Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | clk: at91: Fix at91-pmc and at91-sckc's class IDWenyou Yang2016-10-28-20/+7
| |/ | | | | | | | | | | | | | | | | | | | | The at91-pmc and at91-sckc aren't the clock providers, change their class ID from UCLASS_CLK to UCLASS_SIMPLE_BUS, they also don't need to bind the child nodes explicitly, the .post_bind callback of simple_bus uclass will do it for them. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-10-28-0/+34
|\ \ | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: common/Kconfig configs/dms-ba16_defconfig
| * | mtd: nand: Kconfig: Add NAND_MXS entryJagan Teki2016-10-26-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added kconfig for NAND_MXS driver. Cc: Scott Wood <oss@buserror.net> Cc: Simon Glass <sjg@chromium.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | net: Kconfig: Add FEC_MXC entryJagan Teki2016-10-26-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added kconfig for FEC_MXC driver. Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | thermal: Kconfig: Add IMX_THERMAL entryJagan Teki2016-10-26-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added kconfig for IMX_THERMAL driver. Cc: Simon Glass <sjg@chromium.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | serial: Kconfig: Add MXC_UART entryJagan Teki2016-10-26-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added kconfig for MXC_UART driver. Cc: Simon Glass <sjg@chromium.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
generated by cgit v1.1 at 2024-11-09 06:42:42 +0000