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* net: zynq: Fix MDC setting for zynqMichal Simek2015-11-19-1/+1
| | | | | | | | | | | | | Based on spec: "MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations)" Zynq is running on 111MHz. Current setting is 32 which is 111/32=3.47 which is above of 2.5MHz. Using 48 divider will give us correct setting according spec (111/48=2.31). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Remove unused MDCCLKDIV2 macroMichal Simek2015-11-19-1/+0
| | | | | | | Driver cleanup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Fix mdc clock division setting for 100Mbit/sMichal Simek2015-11-19-2/+2
| | | | | | | | | | | Using set and clear macro is incorrect because it is not overwritting origin mdc clock division setup. For example origin setup is 8(0b001) and new setup is 64(0b100) which means 0b101 is setup which is 96 divider. Using writel to rewrite all setting like for 1000Mbit/s case. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Wait till packet is sentMichal Simek2015-11-19-1/+32
| | | | | | Wait till BD is processed to ensure that packet was sent successfully. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq: Disable secondary queuesEdgar E. Iglesias2015-11-19-0/+26
| | | | | | | | | | | | Zynq has no priority queues. ZynqMP has one priority queue and this change is required to get ethernet working. This patch was not needed on ep108 for uknown reason even it should be used. Tested on Zynq and ZynqMP. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq: Add dummy packet to fix packet duplication issueMichal Simek2015-11-19-2/+8
| | | | | | | | | Target is duplicating packets. IP prefetches another BD and process it when the first one is sent. Adding one dummy BD to the chain fix the problem with packet duplication. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Do not report TX underrunMichal Simek2015-11-19-2/+0
| | | | | Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Setup BD when structures are filledMichal Simek2015-11-19-3/+3
| | | | | | | Fix incorrect sequence in BD handling. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Allocate BD_SPACE in connection to RX_BUFMichal Simek2015-11-19-1/+1
| | | | | | | | | BD_SEPRN_SPACE should not have hard coded value and it will be calculated based on the number of buffer descriptors that we would like to use. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Fix clearing statisticMichal Simek2015-11-19-4/+3
| | | | | | | | Previous loop was completely bogus. Iterration should go just over statistic counters. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Extend register description with offsetsMichal Simek2015-11-19-15/+15
| | | | | | | Extend comments with register offset to help with debuggging. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Add support for different PHY interface typesMichal Simek2015-11-19-1/+8
| | | | | | | | | | | | | MII is setup by default for all cases. The most of boards are using RGMII but PHY drivers are not doing any specific setting that's why MII setting was working fine. With TI DP83867 is necessary to setup paramaters based on interface type. Use one setting per board for it which is something what will be removed when driver is moved to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Add debug message to phyread/phywriteMichal Simek2015-11-19-1/+12
| | | | | | | Add debug messages to phyread/write to help with PHY debug. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: Add support for Texas Instruments DP83867Edgar E. Iglesias2015-11-19-0/+204
| | | | | | | | | Code is taken from Linux kernel driver (v4.2). Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* spl: change return values of spl_*_load_image()Nikita Kiryanov2015-11-18-5/+12
| | | | | | | | | | | | | | | | | | | | | | | Make spl_*_load_image() functions return a value instead of hanging if a problem is encountered. This enables main spl code to make the decision whether to hang or not, thus preparing it to support alternative boot devices. Some boot devices (namely nand and spi) do not hang on error. Instead, they return normally and SPL proceeds to boot the contents of the load address. This is considered a bug and is rectified by hanging on error for these devices as well. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans De Goede <hdegoede@redhat.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Jagan Teki <jteki@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* altera_pio: change ioremap to map_physmemThomas Chou2015-11-18-2/+3
| | | | | | | Change ioremap() to map_physmem(), as it is more used in u-boot. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
* altera_qspi: change ioremap to map_physmemThomas Chou2015-11-18-1/+1
| | | | | | | Change ioremap() to map_physmem(), as it is more used in u-boot. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
* altera_tse: change ioremap to map_physmemThomas Chou2015-11-18-1/+1
| | | | | | | Change ioremap() to map_physmem(), as it is more used in u-boot. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
* altera_sysid: change ioremap to map_physmemThomas Chou2015-11-18-2/+3
| | | | | | | Change ioremap() to map_physmem(), as it is more used in u-boot. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
* altera_spi: change ioremap to map_physmemThomas Chou2015-11-18-2/+3
| | | | | | | Change ioremap() to map_physmem(), as it is more used in u-boot. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
* altera_timer: change ioremap to map_physmemThomas Chou2015-11-18-2/+3
| | | | | | | Change ioremap() to map_physmem(), as it is more used in u-boot. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
* altera_uart: change ioremap to map_physmemThomas Chou2015-11-18-2/+3
| | | | | | | Change ioremap() to map_physmem(), as it is more used in u-boot. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
* altera_jtag_uart: change ioremap to map_physmemThomas Chou2015-11-18-2/+3
| | | | | | | Change ioremap() to map_physmem(), as it is more used in u-boot. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
* arm: mvebu: Fix SAR1_CPU_CORE_MASKDirk Eibach2015-11-17-5/+2
| | | | | | | | SAR1_CPU_CORE_MASK was wrong, probably copy/paste from another architecture. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* arm: mvebu: a38x: Remove unsupported topologiesKevin Smith2015-11-17-77/+0
| | | | | | | | | | | | | | A lot of extra configuration information was left over in the Marvell serdes and DDR3 initialization code for boards that U-boot does not support. Remove this extra config information, and the concept of fixing up board topologies with information loaded from an EEPROM. If this needs to be done, it should be handled in the board file, not in core code. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-11-16-1/+25
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| * video: mxsfb: introduce lcdif_power_downPeng Fan2015-11-12-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introudce a new function lcdif_power_down. 1. Waits for a VSYNC interrupt to guarantee the reset is done at the VSYNC edge, which somehow makes the LCDIF consume the display FIFO(?) and helps the LCDIF work normally at the kernel stage. 2. Add power down function to stop lcdif. The reason to introduce lcdif_power_down is that we want lcdif to be in initial state when doing uboot reset or before kernel boot to make system stable, otherwise system may hang. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
| * mxs: add parameter base_addr for mxs_set_lcdclkPeng Fan2015-11-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | Change mxs_set_lcdclk prototype to add a new parameter base_addr. There are two LCD interfaces for i.MX6SX, we may support LCDIF1 or LCDIF2. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
| * Merge git://git.denx.de/u-bootStefano Babic2015-11-12-576/+2638
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| * | driver: misc: add MXC_OCOTP Kconfig entryPeng Fan2015-10-30-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add MXC_OCOTP Kconfig entry. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* | | Merge branch 'series1_v2' of git://git.denx.de/u-boot-sparcTom Rini2015-11-13-3/+22
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| * | | sparc: leon3: Add debug_uart support to LEON3 serial driver.Francois Retief2015-11-13-0/+8
| | | | | | | | | | | | | | | | Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * | | sparc: leon3: Moved GRLIB core header files to common include/grlib directoryDaniel Hellstrom2015-11-13-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | | sparc: leon3: Reimplemented AMBA Plug&Play scanning routines.Daniel Hellstrom2015-11-13-2/+13
| | | | | | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
* | | | sf: Fix NULL pointer exception for flashes without lock methodsBin Meng2015-11-13-6/+12
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit c3c016c "sf: Add SPI NOR protection mechanism" introduced flash_lock()/flash_unlock()/flash_is_locked() methods for SPI flash, but not every flash driver supplies these. We should test these methods against NULL before actually calling them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-11-12-6/+502
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| * | | Tegra: T210: Add QSPI driverTom Warren2015-11-12-0/+425
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the normal Tegra SPI driver modified to work with the QSPI controller in Tegra210. It does not do 2x/4x transfers or any other QSPI protocol. Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | | pci: tegra: add/enable support for Tegra210Stephen Warren2015-11-12-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This needs a separate compatible value from Tegra124 since the new HW version has bugs that would prevent a driver for previous HW versions from operating at all. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | pci: tegra: call tegra_pcie_board_init() earlierStephen Warren2015-11-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board PCI setup code may control regulators that are required simply to bring up the PCI controller itself (or PLLs, IOs, ... it uses). Move the call to this function earlier so that all board-provided resources are ready early enough for everything to work. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | pci: tegra: implement PCA enable workaroundStephen Warren2015-11-12-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra210's PCIe controller has a bug that requires the PCA (performance counter) feature to be enabled. If this isn't done, accesses to device configuration space will hang the chip for tens of seconds. Implement the workaround. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | pci: tegra: use #address-/size-cells from DTStephen Warren2015-11-12-3/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The number of cells used by each entry in the DT ranges property is determined by the #address-cells/#size-cells properties. Fix the code to respect this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | pci: tegra: clip RAM size to 32-bitsStephen Warren2015-11-12-1/+9
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | Tegra peripherals can generally access a 32-bit physical address space, and I believe this applies to PCIe. Clip the PCI region that refers to DRAM so it fits into 32-bits to avoid issues. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | pengwyn: nand and ethernet fixesVincent BENOIT2015-11-12-2/+43
| | | | | | | | | | | | | | | | | | -> Add National instrument ethernet transceiver configuration used (DP83848) -> Change cpsw slave phy address -> modify nand configuration to use the correct ECC and correct nand features
* | | block: ahci: Remove dead codeFabio Estevam2015-11-12-36/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_AHCI_SETFEATURES_XFER is not selected by any user, so delete the dead code. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | i2c: Fix pca953x endianess issueDirk Eibach2015-11-12-1/+3
| | | | | | | | | | | | | | | | | | | | | By reading 2 consecutive bytes from i2c to an u16 value we have an endianess issue. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | | i2c: soft_i2c: Fix bus indizesDirk Eibach2015-11-12-10/+10
| | | | | | | | | | | | | | | | | | | | | Since busses are sorted in alphabetical order, introducing more than nine busses led to unexpected behaviour. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | | hrcon: Add fan controllersDirk Eibach2015-11-12-0/+28
| | | | | | | | | | | | Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | | hrcon: Add support for the DH variantDirk Eibach2015-11-12-0/+28
| | | | | | | | | | | | | | | | | | hrcon DH(dual head) has two video outputs per FPGA. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | | i2c: ihs_i2c: Fix hold_bus controlDirk Eibach2015-11-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Bus has to be held for repeated start regardless of read/write access. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Acked-by: Heiko Schocher <hs@denx.de>
* | | i2c: ihs_i2c: Use macro bestpracticesDirk Eibach2015-11-12-10/+14
| | | | | | | | | | | | | | | | | | | | | Reinhard Pfau complained that macros in ihs_i2c do not follow best practices. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Acked-by: Heiko Schocher <hs@denx.de>
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