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* drivers/ddr/fsl: Update DDR driver for DDR4York Sun2015-04-23-10/+88
| | | | | | | | | | Add/update registers for DDR4, including DQ mappings. Allow raw timing method used for all controllers. Update mode_9 register to 0x500 for improved stability. Check DDR controller version number individually in case a SoC has multiple DDR controllers of different versions. Increase read-write turnaround for DDR4 high speeds. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/i2c/mxc: Enable I2C bus 3 and 4York Sun2015-04-23-3/+14
| | | | | | | | | Some SoCs have more than two I2C busses. Instead of adding ifdef to the driver, macros are put into board header file where CONFIG_SYS_I2C_MXC is defined. Signed-off-by: York Sun <yorksun@freescale.com> CC: Heiko Schocher <hs@denx.de>
* nand/fsl_ifc: Increase eccstat[] for IFC 2.0Scott Wood2015-04-23-2/+9
| | | | | | | | IFC 2.0 doubled the SRAM size, which means double the number of ECCSTAT registers. Fix the resulting array overflow. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/fsl_ifc: Add support to finalize CS1, CS3 address bindingPrabhakar Kushwaha2015-04-23-0/+9
| | | | | | | | | For fsl-lsch3, IFC is binded with address within 32-bit at fist. After u-boot relocates to DDR, CS1, CS3 can be binded to higher address to support large space. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ldpaa_eth: Add LDPAA Ethernet driverPrabhakar Kushwaha2015-04-23-3/+871
| | | | | | | | | | | | | | | LDPAA Ethernet driver is a freescale's new ethernet driver based on Layerscape architecture. Every ethernet driver controls on DPNI object. Where all DPNIs share one common DPBP and DPIO object to support Rx and Tx flows. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Cristian Sovaiala <cristian.sovaiala@freescale.com> CC: Bogdan Hamciuc <bogdan.hamciuc@freescale.com> CC: J. German Rivera <German.Rivera@freescale.com> [York Sun: s/NetReceive/net_process_received_packet] Reviewed-by: York Sun <yorksun@freescale.com>
* driver/fsl-mc: Add support of MC FlibsPrabhakar Kushwaha2015-04-21-106/+2444
| | | | | | | | | | | | | | | | | | | | | | Freescale's Layerscape Management Complex (MC) provide support various objects like DPRC, DPNI, DPBP and DPIO. Where: DPRC: Place holdes for other MC objectes like DPNI, DPBP, DPIO DPBP: Management of buffer pool DPIO: Used for used to QBMan portal DPNI: Represents standard network interface These objects are used for DPAA ethernet drivers. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com> Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: Add Freescale Debug Server driverBhupesh Sharma2015-04-21-0/+251
| | | | | | | | | | | | | The Debug Server driver is responsible for loading the Debug server FW on the Service Processor (Cortex-A5 core) on LS2085A like SoCs and then polling for the successful initialization of the same. TOP MEM HIDE is adjusted to ensure the space required by Debug Server FW is accounted for. MC uses the DDR area which is calculated as: MC DDR region start = Top of DDR - area reserved by Debug Server FW Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* QE/DeepSleep: add QE deepsleep support for mpc85xxZhao Qiang2015-04-21-0/+88
| | | | | | | | Muram will power off during deepsleep, and the microcode of qe in muram will be lost, it should be reload when resume. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* drivers:usb: Check if USB Erratum A005697 is applicable on BSC913xNikhil Badola2015-04-21-0/+9
| | | | | | | | | Check if USB Erratum A005697 is applicable on BSC913x and add corresponding property in the device tree via device tree fixup which is used by linux driver Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* pci/layerscape: fix link and class issues to support ls2085aMinghuan Lian2015-04-21-14/+33
| | | | | | | | | | | | | | 1. LS2085a provides PCIE_LUT_DBG register rather than PCIE_LDBG to show the link status, so the patch fixes it. 2. Increase the delay time to make sure that link training has finished. 3. Return invalid value when accessing multi-function device 4. For LS2085a DBI_RO_WR_EN bit is cleared as default, so we must set this bit before change DBI register value. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* pci/layerscape: remove unnecessary pcie_layerscape.hMinghuan Lian2015-04-21-3/+2
| | | | | | | | | | The patch uses the common function name ft_pci_setup to replace ft_pcie_setup, then removes unnecessary pcie_layerscape.h because all the functions have been declared in common.h. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <yorksun@freescale.com>
* drivers:usb: Add device-tree fixup to identify socs having dual phyNikhil Badola2015-04-21-1/+6
| | | | | | | | | | Identify soc(s) having dual phy so as to add "utmi_dual" as phy_mode for all these socs. This is required for supporting deel-sleep feature in linux for usb driver Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* serial: pl01x: fix PL010 regressionLinus Walleij2015-04-21-2/+11
| | | | | | | | | | | | | | | | | | | | commit aed2fbef5e9a0ab5a7cd01e742039a962f0b24ef "dm: serial: Tidy up the pl01x driver" caused a regression on (real hardware) PL010 by omitting to update the line control register when switching baudrate. Fix this by inlining the missing write to the baud control register. Also renaming the set_line_control() function to pl011_set_line_control() since this function is clearly PL011-specific, and it won't suffice to call that to set up line control. Tested on the Integrator/AP hardware. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2015-04-20-15/+45
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| * net: pch_gbe: Fix pch_gbe device nameBin Meng2015-04-20-1/+1
| | | | | | | | | | | | | | The name "pch_gbe.%x" exceeds the limit of the name in the 'struct eth_device'. Rename it as just "pch_gbe". Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * net: gem: Use correct type for castingMichal Simek2015-04-20-1/+2
| | | | | | | | | | | | | | Use phys_addr_t which is used in function prototype in system.h. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net/phy: fixup for get_phy_idShengzhou Liu2015-04-20-1/+1
| | | | | | | | | | | | | | | | commit 3c6928fd7b0f84 "net: phy: fix warnings with W=1" caused some PHYs(e.g. CS4315/CS4340) not working. This patch fixes the warning and make those special PHYs working as well. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
| * net: phy: micrel: add support for KSZ8081MNXLuca Ellero2015-04-20-0/+11
| | | | | | | | | | | | | | This patch adds a support for KSZ8081MNX in MII mode. Signed-off-by: Luca Ellero <luca.ellero@brickedbrain.com> Acked-by: Pavel Machek <pavel@denx.de>
| * net: rtl8169: Build warning fixes for 64-bitThierry Reding2015-04-20-11/+13
| | | | | | | | | | | | | | | | | | | | | | Turn ioaddr into an unsigned long rather than a sized 32-bit variable. While at it, fix a couple of pointer to integer cast size mismatch warnings by casting through unsigned long going from pointers to integers and vice versa. Cc: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: phy: realtek: Disable interrupt on Realtek Ethernet PHY driversCodrin Ciubotariu2015-04-20-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Realtek Ethernet PHYs, like RTL8211D(G/N) and RTL8211E(G), have interrupts enabled by default. If the interrupt is not treated later by the OS and the PHY's interrupt line is enabled and shared with other interrupts, the system will get an interrupt storm. This patch disables the interrupt for PHY devices that use one of the current Realtek Ethernet PHY drivers. Some of Realtek Ethernet PHYs, such as RTL8211B(L) have the interrupt masked. In this case, the functionality of the PHY should not be afected since this patch brings INER and INSR registers to their default values. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-04-20-1/+9
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| * MPC8541/MPC8555: Enable SS_EN in DDR_SDRAM_CLK_CNLT registerCurt Brune2015-04-20-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the MPC8555/MPC8541 reference manual the SS_EN (source synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set during initialization. >From section 9.4.1.8 of that manual: Source synchronous enable. This bit field must be set during initialization. See Section 9.6.1, "DDR SDRAM Initialization Sequence," details. 0 - Reserved 1 - The address and command are sent to the DDR SDRAMs source synchronously. In addition, Freescale application note AN2805 is also very clear that this bit must be set. This patch reverts a change introduced by commit 457caecdbca3df21a93abff19eab12dbc61b7897. Testing Done: Compiled targets CONFIG_TARGET_MPC8555CDS and CONFIG_TARGET_MPC8541CDS and inspected the generated assembly code to verify the SS_EN bit was being set. There is one extra instruction emitted: fff9b774: 65 29 80 00 oris r9,r9,32768 Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no additional instructions were emitted related to this patch. Booted an image on a MPC8541 based board successfully. Signed-off-by: Curt Brune <curt@cumulusnetworks.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2015-04-20-2/+245
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| * video, lg4573: add support for the lg4573 displayHeiko Schocher2015-04-20-0/+232
| | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| * video, ipu: make ldb clock frequency overwritable through board codeHeiko Schocher2015-04-20-1/+8
| | | | | | | | | | | | | | | | | | | | the ldb clock can be setup in board code (for example set through PLL5). Update the ldb_clock rate also through board code. This should be removed, if a clock framework is availiable. Signed-off-by: Heiko Schocher <hs@denx.de> Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * video, ipu: make ldb_clock configurableHeiko Schocher2015-04-20-1/+5
| | | | | | | | | | | | | | | | | | | | make the ldb_clock configurable through the new define CONFIG_SYS_LDB_CLOCK. This is needed as the ldb clock is not always 650000000, for example on the aristainetos2 board, where the ldb clock derives from PLL5 clock. Signed-off-by: Heiko Schocher <hs@denx.de> Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | ahci: mmio_base is a virtual addressScott Wood2015-04-18-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't store it in a u32. Don't dereference the bus address as if it were a virtual address (fixes 284231e49a2b4 ("ahci: Support splitting of read transactions into multiple chunks")). Fixes crash on boot in MPC8641HPCN_36BIT target. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Vadim Bendebury <vbendeb@chromium.org> Acked-by: York Sun <yorksun@freescale.com>
* | sandbox: exynos: Move CONFIG_SOUND_SANDBOX to KconfigSimon Glass2015-04-18-0/+9
| | | | | | | | | | | | Move this over to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | sandbox: exynos: Move CONFIG_SOUND_WM8994 to KconfigSimon Glass2015-04-18-0/+8
| | | | | | | | | | | | Move this over to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | sandbox: exynos: Move CONFIG_SOUND_MAX98095 to KconfigSimon Glass2015-04-18-0/+8
| | | | | | | | | | | | Move this over to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | sandbox: exynos: Move CONFIG_I2S_SAMSUNG to KconfigSimon Glass2015-04-18-0/+10
| | | | | | | | | | | | Move this over to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | sandbox: exynos: Move CONFIG_I2S to KconfigSimon Glass2015-04-18-0/+9
| | | | | | | | | | | | Move this over to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | sandbox: exynos: Move CONFIG_SOUND to KconfigSimon Glass2015-04-18-0/+11
| | | | | | | | | | | | Move this over to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | sandbox: Move CONFIG_TPM_TIS_SANDBOX to KconfigSimon Glass2015-04-18-0/+7
| | | | | | | | | | | | Move this over to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | sandbox: Move CONFIG_SPI_FLASH_SANDBOX to KconfigSimon Glass2015-04-18-0/+10
| | | | | | | | | | | | Move this over to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | sandbox: Move CONFIG_SANDBOX_SPI to KconfigSimon Glass2015-04-18-0/+25
| | | | | | | | | | | | Move this over to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | sandbox: Move CONFIG_SYS_I2C_SANDBOX to KconfigSimon Glass2015-04-18-0/+30
| | | | | | | | | | | | | | Move this over to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher<hs@denx.de>
* | sandbox: Move GPIO CONFIGs to KconfigSimon Glass2015-04-18-0/+21
| | | | | | | | | | | | Move these over to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: net: Adjust designware driver to support driver modelSimon Glass2015-04-18-17/+153
| | | | | | | | | | | | | | | | Add driver model support to the designware driver. This reuses most of the existing code except for some duplication in the probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | dm: net: Tidy up designware driver ready for driver modelSimon Glass2015-04-18-34/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust the error handling to use errno.h instead of returning -1. Change leaf functions to pass in the arguments they require rather than struct eth_device. Apart from simplifying the code it makes is easier to reuse these functions for driver model, since mostly they actually only use struct dw_eth_priv (which we can keep). Create a stub for each Ethernet operation function. This will allow use to share code with the driver model versions. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | dm: net: Adjust PHY interface to work with CONFIG_DM_ETHSimon Glass2015-04-18-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | When driver model is used for Ethernet a few functions are passed a udevice instead of an eth_device. Also add a function to find a PHY type given its name. This will be used to decode the device tree node. Finally, put a phy_interface field in struct eth_pdata since this is an important part of the platform data for Ethernet. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Kconfig: Move CONFIG_DESIGNWARE_ETH to KconfigSimon Glass2015-04-18-1/+8
| | | | | | | | | | | | | | | | | | | | Move this to Kconfig and clean up board config files that use it. Also rename it to CONFIG_ETH_DESIGNWARE to fit with the naming that exists in drivers/net/Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org> Version 1: Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: cosmetic: Fix checkpatch.pl failures in net.cJoe Hershberger2015-04-18-6/+6
| | | | | | | | | | | | | | Finish eliminating CamelCase from net.c and other failures Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* | net: cosmetic: Clean up netconsole variables and functionsJoe Hershberger2015-04-18-15/+17
| | | | | | | | | | | | | | | | Make a thorough pass through all variables and function names contained within netconsole.c and remove CamelCase and improve naming. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* | net: cosmetic: Fix var naming net <-> eth driversJoe Hershberger2015-04-18-166/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the naming convention used in the network stack functions and variables that Ethernet drivers use to interact with it. This cleans up the temporary hacks that were added to this interface along with the DM support. This patch has a few remaining checkpatch.pl failures that would be out of the scope of this patch to fix (drivers that are in gross violation of checkpatch.pl). Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* | net: cosmetic: Cleanup internal packet buffer namesJoe Hershberger2015-04-18-6/+7
| | | | | | | | | | | | | | This patch cleans up the names of internal packet buffer names that are used within the network stack and the functions that use them. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: cosmetic: Name ethaddr variables consistentlyJoe Hershberger2015-04-18-19/+20
| | | | | | | | | | | | | | | | Use "_ethaddr" at the end of variables and drop CamelCase. Make constant values actually 'const'. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* | net: cosmetic: Change IPaddr_t to struct in_addrJoe Hershberger2015-04-18-29/+30
| | | | | | | | | | | | | | | | | | This patch is simply clean-up to make the IPv4 type that is used match what Linux uses. It also attempts to move all variables that are IP addresses use good naming instead of CamelCase. No functional change. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* | dm: spi_flash: fix wrong dependencyMasahiro Yamada2015-04-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SPI does not exist in Kconfig in the first place, so the dependency "depends on DM && SPI" is never met, i.e., DM_SPI_FLASH can never be enabled (unless you ignore the dependency in an illegal way. See below.) Actually, some defconfigs such as socfpga_*_defconfig define CONFIG_DM_SPI_FLASH=y, but it never appears in the .config file because of this wrong dependency. On the other hand, all the Tegra boards enable DM_SPI_FLASH because config DM_SPI_FLASH default y silently ignores the dependency. Unfortunately, this style of CONFIG definition is abused everywhere in U-Boot, so we easily miss such a wrong dependency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* | dm: usb: exynos: Adjust XHCI driver to support driver modelSimon Glass2015-04-18-1/+119
| | | | | | | | | | | | | | Support driver model in the exynos XHCI driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marek Vasut <marex@denx.de>
generated by cgit v1.1 at 2024-11-07 19:50:55 +0000