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* dm: pci: Enable VGA address forwarding on bridgesBin Meng2015-10-21-0/+18
| | | | | | | | | To support graphics card behind a PCI bridge, the bridge control register (offset 0x3e) in the configuration space must turn on VGA address forwarding. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Fix pci_last_busno() to return the real last bus noBin Meng2015-10-21-24/+1
| | | | | | | | | Currently pci_last_busno() only checks the last bridge device under the first UCLASS_PCI device. This is not the case when there are multiple bridge devices. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* video: vesa_fb: Fix wrong return value check of pci_find_class()Bin Meng2015-10-21-1/+1
| | | | | | | | | When pci_find_class() fails to find a device, it returns -ENODEV. But now we check the return value against -1. Fix it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* pci: Set PCI_COMMAND_IO bit for VGA deviceBin Meng2015-10-21-0/+6
| | | | | | | | PCI_COMMAND_IO bit must be set for VGA device as it needs to respond to legacy VGA IO address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Adjust pci_find_and_bind_driver() to return -EPERMSimon Glass2015-10-21-12/+19
| | | | | | | | | | | | | | The current code returns 0 even if it failed to find or bind a driver. The caller then has to check the returned device to see if it is NULL. It is better to return an error code in this case so that it is clear what happened. Adjust the code to return -EPERM, indicating that the device was not bound because it is not needed for pre-relocation use. Add comments so that the return value is clear. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Correct a few debug() statementsSimon Glass2015-10-21-2/+2
| | | | | | | | One debug() statement is missing a newline. The other has a repeated word. Fix these. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Tidy up auto-config error handlingSimon Glass2015-10-21-3/+12
| | | | | | | | | | | When the auto-configuration process fails for a device (generally due to lack of memory) we should return the error correctly so that we don't continue to try memory allocations which will fail. Adjust the code to check for errors and abort if something goes wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dfu: dfu_sf: Take the start address into accountFabio Estevam2015-10-19-2/+10
| | | | | | | | | | | | | | | | | | | | The dfu_alt_info_spl variable allows passing a starting point for the binary to be flashed in the SPI NOR. For example, if we have 'dfu_alt_info_spl=spl raw 0x400', this means that we want to flash the binary starting at address 0x400. In order to do so we need to erase the entire sector and write to the the subsequent SPI NOR sectors taking such start address into account for the address calculations. Tested by succesfully writing SPL binary into 0x400 offset and the u-boot.img at offset 64 kiB of a SPL NOR. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Use lldiv for the math] Signed-off-by: Tom Rini <trini@konsulko.com>
* dfu: dfu_sf: Use the erase sector size for erase operationsFabio Estevam2015-10-19-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI NOR flashes need to erase the entire sector size and we cannot pass any arbitrary length for the erase operation. To illustrate the problem: Copying data from PC to DFU device Download [=========================] 100% 478208 bytes Download done. state(7) = dfuMANIFEST, status(0) = No error condition is present state(10) = dfuERROR, status(14) = Something went wrong, but the device does not know what it was Done! In this case, the binary has 478208 bytes and the M25P32 SPI NOR has an erase sector of 64kB. 478208 = 7 entire sectors of 64kiB + 19456 bytes. Erasing the first seven 64 kB sectors works fine, but when trying to erase the remainding 19456 causes problem and the board hangs. Fix the issue by always erasing with the erase sector size. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com>
* Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2015-10-16-20/+30
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| * exynos: more debug and cleanup in do_sdhci_init()Tobias Jakobi2015-10-13-9/+11
| | | | | | | | | | | | | | | | | | Add more debug printfs in do_sdhci_init() for calls that can potentially fail. Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * exynos: be more verbose in process_nodes()Tobias Jakobi2015-10-13-5/+7
| | | | | | | | | | | | | | | | | | In case sdhci_get_config() or do_sdhci_init() fail, show the error code that was returned. Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * exynos: Fix passing of errors in exynos_mmc_init()Tobias Jakobi2015-10-13-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | exynos_mmc_init() always returns zero, so for the caller it looks like it never fails. Correct this by returning the error code of process_nodes(). For process_nodes() do something similar and return early when do_sdhci_init() fails. v2: Only fail in process_nodes() if we fail on all available nodes. Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * exynos: Properly zero initialize host in s5p_sdhci_init()Tobias Jakobi2015-10-13-2/+2
| | | | | | | | | | | | | | | | | | This makes sure that setting the host_caps in s5p_sdhci_core_init() doesn't operate on potentially uninitialized memory. Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | pci: pcie_imx: Fix hang on mx6qpFabio Estevam2015-10-15-0/+8
| | | | | | | | | | | | | | | | | | | | | | PCI driver currently hangs on mx6qp. Toggle the reset bit with the appropriate timings to fix the issue. Based on the FSL kernel driver implementation. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-10-15-109/+138
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| * mtd: nand: vf610_nfc: resync with upstream Linux versionStefan Agner2015-10-15-109/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This resyncs the driver changes with the Linux version of the driver. The driver received some feedback in the LKML and got recently acceppted, the latest version can be found here: https://lkml.org/lkml/2015/9/2/678 Notable changes are: - On ECC error, reread OOB and count bit flips in OOB too. If flipped bits are below threshold, also return an empty OOB buffer. - Return the amount of bit flips in vf610_nfc_read_page. - Use endianness aware vf610_nfc_read to read ECC status. - Do not enable IDLE IRQ (since we do not operate with an interrupt service routine). - Use type safe struct for buffer variants (vf610_nfc_alt_buf). - Renamed variables in struct vf610_nfc (column and page_sz) to reflect better what they really representing. The U-Boot version currently does not support RAW NAND write when using the HW ECC engine. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> Tested-by: Stefan Agner <stefan@agner.ch> Acked-by: Scott Wood <scottwood@freescale.com>
* | ls102xa: Fix reset hangFabio Estevam2015-10-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 623d96e89aca6("imx: wdog: correct wcr register settings") issuing a 'reset' command causes the system to hang. Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian. This means that the watchdog on LS1021 has been working by accident as it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c. Commit 623d96e89aca6("imx: wdog: correct wcr register settings") only revelead the endianness problem on LS102x. In order to fix the reset hang, introduce a reset_cpu() implementation that is specific for ls102x, which accesses the watchdog WCR register in big-endian format. All that is required to reset LS102x is to clear the SRS bit. This approach is a temporary workaround to avoid a regression for LS102x in the 2015.10 release. The proper fix is to make the watchdog driver endian-aware, so that it can work for i.MX, Vybrid and LS102x. Reported-by: Sinan Akman <sinan@writeme.com> Tested-by: Sinan Akman <sinan@writeme.com> Reviewed-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | imx_watchdog: Add a header file for watchdog registersFabio Estevam2015-10-12-13/+1
| | | | | | | | | | | | | | | | | | Create fsl_wdog.h to store the watchdog registers and bit fields. This can be useful when accesses to the watchdog block are made from other parts, such as arch/arm/ cpu code. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | nand: omap_gpmc: Change correctable bit-flips messages to debug()Ezequiel García2015-10-11-3/+3
| | | | | | | | | | | | | | | | Messages on corrected bit-flips are not really useful, as bit-flips are perfectly normal. Let's avoid cluttering the console and make them debug. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
* | Revert "powerpc: ppc4xx: remove lwmon5 support"Stefan Roese2015-10-11-1/+2
| | | | | | | | | | | | | | | | | | | | This reverts commit 8fe11b8901a31d11990488c82bc23612589d57be. I'll add support to lwmon5 in the next patch and will remove support for the broken lcd4_lwmon5 as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* | mtd: sf: Add support AT26DF081A chipYao Yuan2015-10-11-0/+1
| | | | | | | | | | | | | | | | AT26DF081A is the spi flash type of TWR-MEM(SCH-26248) card. We can access the flash through DSPI2 on LS1021ATWR board. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | spi: tegra20: Add support for mode selectionMirza Krak2015-10-11-0/+21
| | | | | | | | | | | | | | Respect the mode passed in set_mode ops. Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | spi: zynq_spi: Fix to configure CPOL, CPHA maskJagan Teki2015-10-11-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | priv->mode is initialized when .set_speed triggers with mode value, so checking mode for configuring CPOL, CPHA using priv->mode is invalid hence use mode from .set_speed argument, and at the end priv->mode will initialized with mode. This patch also replaces formatting string to use speed instead of mode in .set_speed ops. Signed-off-by: Jagan Teki <jteki@openedev.com>
* | spi: xilinx_spi: Fix to configure CPOL, CPHA maskJagan Teki2015-10-11-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | priv->mode is initialized when .set_speed triggers with mode value, so checking mode for configuring CPOL, CPHA using priv->mode is invalid hence use mode from .set_speed argument, and at the end priv->mode will initialized with mode. This patch also replaces formatting string to use speed instead of mode in .set_speed ops. Signed-off-by: Jagan Teki <jteki@openedev.com>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2015-10-09-0/+1
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| * | pci: Fix expansion ROM programming for multi-function devicesBin Meng2015-10-08-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | PCI_HEADER_TYPE register (offset 0x0e) bit 7 is an indicator for multi-function devices. We should mask it off before using it as the header type. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | Merge git://git.denx.de/u-boot-dmTom Rini2015-10-08-3/+7
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| * | | sandbox: Correct operaion of 'reset' commandSimon Glass2015-10-05-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently 'reset' only works with the test device tree. When run without a device tree, or with the normal device tree, the following error is displayed: Reset not supported on this platform Fix the driver and the standard device tree to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
| * | | dm: core: Don't use pinctrl for the root deviceSimon Glass2015-10-05-2/+6
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently when driver model starts up it finds the root uclass and the pinctrl uclass. This is because even the root node handles pinctrl processing. But this is not useful. The root node is not a real hardware device so cannot require any particular pinmux settings. Also it means that the memory leak tests fails, since they end up freeing more memory than they allocate: the marker it set after the root device and pinctrl uclass are allocated, and later once the pinctrl uclass is freed the memory used by driver model is less than when the marker was set. If a platform needs 'core' pin mulitplex settings it can do this with a driver that is probed on start-up. It would be an abuse of the root node to use this for pinctrl. To avoid this problem, only process pinctrl settings for non-root nodes. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | serial: rockchip: make ROCKCHIP_SERIAL depend on ARCH_ROCKCHIPMasahiro Yamada2015-10-03-1/+1
|/ / | | | | | | | | | | | | It looks like this line was copy-pasted, but not modified. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* | gpio: s5p: call: dev_get_addr() instead of fdtdec_get_addr()Przemyslaw Marczak2015-10-03-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After rework in lib/fdtdec.c, the function fdtdec_get_addr() doesn't work for nodes with #size-cells property set to 0. To get GPIO's 'reg' property, the code should use one of: fdtdec_get_addr_size_auto_no/parent() function. Fortunately dm core provides a function to get the property. This commit reworks function gpio_exynos_bind(), to properly use dev_get_addr() for GPIO device. This prevents setting a wrong base register for Exynos GPIOs. Tested on: Odroid U3/X2, Trats, Trats2, Odroid XU3, Snow (by Simon). Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-10-02-32/+26
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| * | gpio: tegra: use named constantsStephen Warren2015-10-02-14/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to make it clear what the parameters to set_config() and set_direction() mean, and similarly for the return values from the respective get_*(), define named constants for these values. Disassembly shows no diff in the generated code, except that the order of the code in the branches of tegra_gpio_get_function() gets modified without affecting behaviour. Suggested-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | gpio: tegra: remove unused typeStephen Warren2015-10-02-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | These enum values aren't used anywhere. Remove them. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: don't enable GPIOs until direction is setStephen Warren2015-10-02-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's GPIO driver currently enables pins as GPIO as soon as they're requested. This is not safe, since the desired direction and output value are not yet known. This could cause a glitch on the output pins between gpio_request() and gpio_direction_*(), depending on what values happen to be in the GPIO controller's in/out and out-value registers vs. the final desired configuration. To solve this, defer enabling pins as GPIOs until some gpio_direction_*() is invoked, and the desired configuration is explicitly programmed. In theory this change could cause regressions, if code exists that claims a GPIO, never explicitly sets a direction, and then gets/sets the GPIO value based on that assumption. However, I've read through all the Tegra- related board files and device drivers that touch GPIOs and I do not see such buggy code anywhere. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: fix GPIO init table programmingStephen Warren2015-10-02-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's gpio_config_table() currently uses common GPIO APIs. These used to work without requesting the GPIO, but since commit 2fccd2d96bad "tegra: Convert tegra GPIO driver to use driver model" no longer do so. This prevents any of the GPIO initialization table from being applied to HW. Fix gpio_config_table() to directly program the HW to solve this. Fixes: 2fccd2d96bad ("tegra: Convert tegra GPIO driver to use driver model") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-10-02-0/+6
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| * | I2C: mxc_i2c: make I2C1 and I2C2 optionalAlbert ARIBAUD \\(3ADEV\\)2015-10-02-0/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver assumed that I2C1 and I2C2 were always enabled, and if they were not, then an asynchronous abort was (silently) raised, to be caught much later on in the Linux kernel. Fix this by making I2C1 and I2C2 optional just like I2C3 and I2C4 are. To make the change binary-invariant, declare I2C1 and I2C2 in every include/configs/ file which defines CONFIG_SYS_I2C_MXC. Also, while updating README about CONFIG_SYS_I2C_MXC_I2C1 and CONFIG_SYS_I2C_MXC_I2C2, add missing descriptions for I2C4 speed (CONFIG_SYS_MXC_I2C4_SPEED) and slave (CONFIG_SYS_MXC_I2C4_SLAVE) config options. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2015-09-30-4/+12
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| * | net: fix netconsole when CONFIG_DM_ETH is setBernhard Nortmann2015-09-29-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | This patch uses the eth_is_active() function to work around issues that prevented compilation with the newer driver model. Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: on phy device create do not initialize link to 1Mugunthan V N2015-09-29-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently when phy device is created the link variable is initialized to 1 which denoted phy link is already up. On a power reset there is no issue as phy status register link status will not be set, so phy auto negotiate will be started. But when a cpu reset is issued (ex: dra72x-evm) phy's link status bit is already set which leads to assume that link is already setup in genphy_update_link() initial check which results in ehternet not working. So do not assume that link is already up and on phy device create set link to zero. This is verified on dra72x-evm. Reported-by: Franklin S Cooper Jr <fcooper@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | sunxi: mmc: Fix clk-delay settingsHans de Goede2015-09-29-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In recent allwinner kernel sources the mmc/sdio clk-delay settings have been slightly tweaked, and for sun9i they are completely different then what we are using. This commit brings us in sync with what allwinner does, fixing problems accessing sdcards on some A33 devices (and likely others). For pre sun9i hardware this makes the following changes: -At 400Khz change the sample delay from 7 to 0 (first introduced in A31 sdk) -At 50 Mhz change the sample delay from 5 to 4 (first introduced in A23 sdk) -Above 50 MHz change the out delay from 2 to 1 (first introduced in A20 sdk) Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi_nand_spl: Be smarter about where to look for backup u-boot.binHans de Goede2015-09-29-6/+20
|/ | | | | | | | | | | | | | | | | | We know when u-boot is written to its own partition, in this case the layout always is: eb 0 spl eb 1 spl-backup eb 2 u-boot eb 3 u-boot-backup eb: erase-block So if we cannot load u-boot from its primary offset we know exactly where to look for it. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* mmc: dw_mmc: Increase timeout to 4 minutes (as in Linux kernel)Łukasz Majewski2015-09-28-1/+1
| | | | | | | | | | | | | | | | | | | | The commit: d9dbb97be0e4a550457aec5f11afefb446169c90 "mmc: dw_mmc: Zap endless timeout" removed endless loop waiting for end of dw mmc transfer. For some workloads - dfu test @ Odroid XU3 (sending 8MiB file) - and SD cards (e.g. MicroSD Kingston 4GiB, Adata 4GiB) the default timeout is to short. The new value - 4 minutes (240 seconds) - is the same as the one used in Linux kernel driver. Such fix should be good enough until we come up with better fix for this issue. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-09-24-2/+10
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| * mtd: nand: mxs check maximum ecc that platfrom supportsPeng Fan2015-09-20-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | Check maximum ecc strength for each platfrom to avoid the calculated ecc exceed the limitation. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Han Xu <b45815@freescale.com> Tested-By: Tim Harvey <tharvey at gateworks.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: wdog: correct wcr register settingsPeng Fan2015-09-20-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | We should not simple use "writew(WCR_WDE, &wdog->wcr)" to set wcr, since this will override bits set before reset_cpu. Use clrsetbits_le16 instead of writew to fix this issue. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Sebastian Siewior <bigeasy@linutronix.de> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2015-09-24-0/+1142
|\ \
| * | ARM: uniphier: rename CONFIG_MACH_* to CONFIG_ARCH_UNIPHIER_*Masahiro Yamada2015-09-25-6/+6
| | | | | | | | | | | | | | | | | | | | | I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify they belong to UniPhier SoC family. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit v1.1 at 2024-11-13 02:44:43 +0000