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* mtd: nand: do not scan BBT after scrubMasahiro Yamada2015-01-09-8/+3
| | | | | | | | | | | | | | | | | Currently, "nand scrub" runs chip->scan_bbt at the end of nand_erase_opts() even if NAND_SKIP_BBTSCAN flag is set. It violates the intention of NAND_SKIP_BBTSCAN. Move NAND_SKIP_BBTSCAN flag check to nand_block_checkbad() so that chip->scan_bbt() is never run if NAND_SKIP_BBTSCAN is set. Also, unset NAND_BBT_SCANNED flag instead of running chip->scan_bbt() right after scrub. We can be lazier here because the BBT is scanned at the next call of nand_block_checkbad(). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com>
* mtd: nand: Mark the BBT as scanned prior to calling scan_bbt againMasahiro Yamada2015-01-09-1/+1
| | | | | | | | | | | | | | | | | | | | | Commit 35c204d8a9d0 (nand: reinstate lazy bad block scanning) broke NAND_BBT_USE_FLASH feature. Its git-log claimed that it reinstated the change as by commit fb49454b1b6c ("nand: reinstate lazy bad block scanning"), but it moved "chip->options |= NAND_BBT_SCANNED" below "chip->scan_bbt(mtd);". It causes recursion if scan_bbt does not find a flash based BBT and tries to write one, and the attempt to erase the BBT area causes a bad block check. Reinstate commit ff49ea8977b5 (NAND: Mark the BBT as scanned prior to calling scan_bbt.). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Rostislav Lisovy <lisovy@merica.cz> Cc: Heiko Schocher <hs@denx.de> Cc: Scott Wood <scottwood@freescale.com>
* mtd: nand: revive "nand scrub" commandMasahiro Yamada2015-01-09-1/+1
| | | | | | | | | Since commit ff94bc40af34 (mtd, ubi, ubifs: resync with Linux-3.14), the "nand scrub" command has not been working. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Heiko Schocher <hs@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-01-08-53/+303
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| * qspi:fsl implement AHB readPeng Fan2015-01-09-10/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QSPI controller in i.MX 6SoloX and Vybrid supports reading data using IP register and AHB bus. The original driver only supports reading data from IP interface. The IC team suggests to use AHB read which is faster then IP read. Using AHB read, we can directly memcpy, a "missed" access to the buffer will cause the controller to clear the buffer and use the SEQID stored in bfgencr register to initiate a read from flash device. Since AHB bus is 64 bit width, we can not set MCR register using 32bit. In order to minimize code change, redefine QSPI_MCR_END_CFD_LE to 64bit Little endian but not 32bit Little endia. Introduce a new configuration option CONFIG_SYS_FSL_QSPI_AHB. If want to use AHB read, just define CONFIG_SYS_FSL_QSPI_AHB. If not, just ignore it. Actually if Vybrid is migrated to use AHB read, this option can be removed and IP read function can be discared. The reason to introduce this option is that only i.MX SOC is tested in my side, no Vybrid platform for me. In spi_setup_slave, the original piece code to set AHB is deleted, since Vybrid platform does not use this to intiate AHB read. Instead, add qspi_init_ahb_read function if defined CONFIG_SYS_FSL_QSPI_AHB. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * spi: ftssp010_spi: Simplify code flow in ftssp010_[wait|wait_tx|wait_rx]Axel Lin2015-01-08-24/+12
| | | | | | | | | | | | | | No functional change, just simplify the code a bit. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * spi: cadence_qspi: Fix checking return value of fdt_first_subnode()Axel Lin2015-01-07-1/+1
| | | | | | | | | | | | | | | | fdt_first_subnode() returns -FDT_ERR_NOTFOUND if no subnode found. 0 is supposed to be a valid offset returns from fdt_first_subnode(). Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * spi:fsl-quadspi support bank register read writePeng Fan2015-01-07-15/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support bigger than 16MB size qspi flashes, spi framework uses bank switch to access higher bank or lower bank. In this patch, QSPI_CMD_BRRD, QSPI_CMD_BRWR, QSPI_CMD_WREAR, QSPI_CMD_RDEAR is initialized in LUT register with related pad and length configuration. qspi_op_pp is originally for page programming, this patch reuses this function for bank register switch and renamed it with qspi_op_write. Since bank or EAR register is only 1 byte length, however original qspi_op_pp or now renamed qspi_op_write only support 4 bytes lenght as the access unit, this will trigger data abort exception when access EAR or bank register. This is because upper framework passes a 1 bytes pointer to qspi_op_write, however qspi_op_write treat it as an int pointer. This patch fixes this for accessing EAR or bank register. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssiMarek Vasut2015-01-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * spi: designware_spi: Fix detecting FIFO depthAxel Lin2015-01-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code tries to find the highest valid fifo depth by checking the value it wrote to DW_SPI_TXFLTR. There are a few problems in current code: 1) There is an off-by-one in dws->fifo_len setting because it assumes the latest register write fails so the latest valid value should be fifo - 1. 2) We know the depth could be from 2 to 256 from HW spec, so it is not necessary to test fifo == 257. In the case fifo is 257, it means the latest valid setting is fifo = 256. So after the for loop iteration, we should check fifo == 2 case instead of fifo == 257 if detecting the FIFO depth fails. This patch fixes above issues. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | i2c:mxc fix array size of i2c_dataPeng Fan2015-01-08-11/+11
| | | | | | | | | | | | | | | | | | | | | | We should not hardcode array size of i2c_data to 3. To CONFIG_FSL_LSCH3, there are 4 i2c interface, but not 3. So the size of i2c_data array should be calculated using "ARRAY_SIZE(i2c_bases)". To avoid compile error, move i2c_bases before sram_data structure which contains i2c_data array. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2015-01-06-43/+60
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| * | MVEBUMMC : REMOVE unnecessary delay from initGerald Kerma2015-01-06-2/+0
| | | | | | | | | | | | | | | | | | | | | Remove unnessecary delay from mvebu_mmc_initialize Signed-off-by: Gérald Kerma <drEagle@doukki.net> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | MVEBUMMC : CLEAN codeGerald Kerma2015-01-06-20/+20
| | | | | | | | | | | | | | | | | | | | | Clean mvebu_mmc_send_cmd Signed-off-by: Gérald Kerma <drEagle@doukki.net> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | MVEBUMMC : REMOVE unnecessary delaysGerald Kerma2015-01-06-3/+0
| | | | | | | | | | | | | | | | | | | | | Remove delays in mvebu_mmc_set_bus and mvebu_mmc_set_clk Signed-off-by: Gérald Kerma <drEagle@doukki.net> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | MVEBUMMC : FIX debug stringsGerald Kerma2015-01-06-5/+13
| | | | | | | | | | | | | | | Signed-off-by: Gérald Kerma <drEagle@doukki.net> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | MVEBUMMC : Speed up access timeGerald Kerma2015-01-06-17/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Get about 40x faster access on SHEEVAPLUG MMC Fix some SD type compatibility Changes in v3: - fix the HW_STATE (from linux mvsdio) - review delays and timeouts Changes in v2: - increase number of loops - remove initial delay Changes in v1: - review all loops, delays and timeouts Signed-off-by: Gérald Kerma <drEagle@doukki.net> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | MVEBUMMC : Change copyright dateGerald Kerma2015-01-06-1/+1
| | | | | | | | | | | | | | | Signed-off-by: Gérald Kerma <drEagle@doukki.net> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | | Merge branch 'misc' of git://git.denx.de/u-boot-x86Tom Rini2015-01-05-10/+7
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| * | | cros-ec-keyboard: Synchronize DT binding from linuxSjoerd Simons2015-01-05-10/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ChromeOS EC keyboard is used by various different chromebooks. Peach pi being the third board in the u-boot tree to use it (snow and peach pit the other two). Rather then embedding the same big DT node in the peach-pi DT again, copy the dtsi snippit & bindings documentation from linux and include it in all 3 boards. This slightly changes the dt bindings in u-boot: * google,key-rows becomes keypad,num-rows * google,key-colums becomes keypad,num-colums * google,repeat-delay-ms and google,repeat-rate-ms are no longer used and replaced by hardcoded values (similar to tegra kbc) Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * | | i2c_eeprom: include <linux/err.h> to fix build errorMasahiro Yamada2015-01-05-0/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drivers/misc/i2c_eeprom.c fails to build unless CONFIG_FIT_SIGNATURE is defined. CC drivers/misc/i2c_eeprom.o drivers/misc/i2c_eeprom.c: In function 'i2c_eeprom_read': drivers/misc/i2c_eeprom.c:15:10: error: 'ENODEV' undeclared (first use in this function) drivers/misc/i2c_eeprom.c:15:10: note: each undeclared identifier is reported only once for each function it appears in drivers/misc/i2c_eeprom.c: In function 'i2c_eeprom_write': drivers/misc/i2c_eeprom.c:21:10: error: 'ENODEV' undeclared (first use in this function) drivers/misc/i2c_eeprom.c:22:1: warning: control reaches end of non-void function [-Wreturn-type] drivers/misc/i2c_eeprom.c: In function 'i2c_eeprom_read': drivers/misc/i2c_eeprom.c:16:1: warning: control reaches end of non-void function [-Wreturn-type] make[2]: *** [drivers/misc/i2c_eeprom.o] Error 1 make[1]: *** [drivers/misc] Error 2 make: *** [drivers] Error 2 By the way, Sandbox (enabling CONFIG_FIT_SIGNATURE) is luckily working depending on it. Sandbox includes include/asm-generic/errno.h from include/errno.h from include/u-boot/rsa-checksum.h from include/image.h from include/common.h from drivers/misc/i2c_eeprom.c Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | mtd: nand: omap_gpmc: fix error handlingGuido Martínez2015-01-05-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "err" was an unsigned variable, causing negative error codes to turn into positive values, which are interpreted as an amount of succesfully corrected bitflips (and thus not an error). In particular, this resulted in that if the elm reports uncorrectable errors (-EBADMSG), the MTD layer (and UBI) falsely succeeded. Signed-off-by: Guido Martínez <guido@vanguardiasur.com.ar> Reviewed-by: Stefan Roese <sr@denx.de>
* | | ahci-plat: provide a weak scsi_bus_reset() hookDmitry Lifshitz2015-01-05-2/+1
| | | | | | | | | | | | | | | | | | | | | This allow the platform to handle a custom reset sequence. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Reviewed-by: Tom Rini <trini@ti.com>
* | | ahci: introduce ahci_reset()Dmitry Lifshitz2015-01-05-17/+30
|/ / | | | | | | | | | | | | | | Extract controller reset code from ahci_host_init() into separate ahci_reset(). Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Reviewed-by: Tom Rini <trini@ti.com>
* | powerpc: mpc824x: remove MPC824X cpu supportMasahiro Yamada2015-01-05-990/+0
| | | | | | | | | | | | | | | | | | | | | | | | All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu>
* | mpc8260: remove atc board supportMasahiro Yamada2015-01-05-218/+0
| | | | | | | | | | | | | | | | | | | | These boards are still non-generic boards. drivers/rtc/ds12887.c should also be removed because it can not be built without CONFIG_ATC. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
* | mpc8xx: remove lwmon board supportMasahiro Yamada2015-01-05-17/+0
| | | | | | | | | | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
* | mpc8xx: remove R360MPI board supportMasahiro Yamada2015-01-05-25/+0
| | | | | | | | | | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
* | mpc8xx: remove RRvision board supportMasahiro Yamada2015-01-05-17/+0
| | | | | | | | | | | | | | | | | | | | | | This board is still a non-generic board. Unused code in arch/powerpc/cpu/mpc8xx/video.c should be also deleted because CONFIG_VIDEO_ENCODER_AD7176, CONFIG_VIDEO_ENCODER_AD7177, CONFIG_VIDEO_ENCODER_AD7179 are not defined any more. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
* | powerpc: manroland: remove uc100, uc101, mucmc52, hmi1001 supportMasahiro Yamada2015-01-05-8/+0
| | | | | | | | | | | | | | | | These boards are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Heiko Schocher <hs@denx.de> Cc: Stefan Roese <sr@denx.de>
* | mpc8xx: remove FPS{850, 860}L, NSCU, SM850, TK885D, virtlab2 supportMasahiro Yamada2015-01-05-51/+2
|/ | | | | | | These boards are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-01-02-446/+99
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| * imx:qspi add 4K erase supportPeng Fan2014-12-31-5/+19
| | | | | | | | | | | | | | | | | | Add 4k erase command support for qspi driver. reuse the 64k erase function, but change the function name from qspi_op_se to qspi_op_erase, since it supports 64k and 4k erase. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * arm:mx6sx add QSPI supportPeng Fan2014-12-31-0/+19
| | | | | | | | | | | | | | Add QSPI support for mx6solox. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * QuadSPI: use correct amba_basePeng Fan2014-12-31-5/+25
| | | | | | | | | | | | | | | | | | According cs, use different amba_base to choose the corresponding flash devices. If not, `sf probe 1:0` and `sf probe 1:1` will choose the same flash device, but not different flash devices. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * QuadSPI: use QSPI_CMD_xx instead of flash opcodesPeng Fan2014-12-31-31/+33
| | | | | | | | | | | | | | Use QSPI_CMD_xx instead of flash opcodes Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * sf: sf_params: Add S25FL164K flash identifier infoAdnan Ali2014-12-18-0/+1
| | | | | | | | | | | | | | | | Add the necessary flash entry for the Spansion S25FL164K flash. Tested on Marvell 88F6218 based design. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * sf: sf_params: Add S25FL116K flash supportAdnan Ali2014-12-18-0/+1
| | | | | | | | | | | | | | Added S25FL116K flash and tested on Marvell 88F6281 based system. Signed-off-by: Adnan Ali <adnan.ali@codethink.co.uk> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * mtd/spi: Add support for SST25WF040BShengzhou Liu2014-12-18-0/+1
| | | | | | | | | | | | | | | | Add support for SST25WF040B-40I-SN flash. Tested on T1024QDS board. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * mtd: sf: Zap ramtron driverJagannadha Sutradharudu Teki2014-12-18-405/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Removed ramtron driver since the EMK boards are no longer been active, and these are the only boards used this flash driver. Commit details for EMK zap: "ppc/arm: zap EMK boards" (sha1: d58a9451e7339ed4cf2b2627e534611f427fb791) Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-01-01-34/+1502
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| * | net: rtl8169: Add support for RTL-8168/8111gThierry Reding2014-12-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This network interface card is found on the NVIDIA Jetson TK1. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | net: rtl8169: Use non-cached memory if availableThierry Reding2014-12-18-11/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To work around potential issues with explicit cache maintenance of the RX and TX descriptor rings, allocate them from a pool of uncached memory if the architecture supports it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | net: rtl8169: Properly align buffersThierry Reding2014-12-18-29/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RX and TX descriptor rings should be aligned to 256 byte boundaries. Use the DEFINE_ALIGN_BUFFER() macro to define the buffers so that they don't have to be manually aligned later on. Also make sure that the buffers do align to cache-line boundaries in case the cache-line is higher than the 256 byte alignment requirements of the NIC. Also add a warning if the cache-line size is larger than the descriptor size, because the driver may discard changes to descriptors made by the hardware when requeuing RX buffers. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | net: rtl8169: Honor CONFIG_SYS_RX_ETH_BUFFERThierry Reding2014-12-18-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the top-level README file, this configuration setting can be used to override the number of receive buffers that an ethernet NIC uses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | pci: tegra: Add Tegra PCIe driverThierry Reding2014-12-18-0/+1144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the PCIe controller found on some generations of Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports with a total of 5 lanes. This is based on the Linux kernel driver, originally submitted upstream by Mike Rapoport. Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | power: Add AMS AS3722 PMIC supportThierry Reding2014-12-18-0/+265
| |/ | | | | | | | | | | | | | | | | The AS3722 provides a number of DC/DC converters and LDOs as well as 8 GPIOs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | usb: eth: add ASIX AX88179 DRIVERRene Griessl2014-12-31-0/+708
| | | | | | | | | | | | | | | | | | | | This patch adds driver support for the ASIX AX88179 USB3.0 to GbE network adapter. Driver has been tested on the RECS5250 COM module (similar to ARDALE5250). Testcase was DHCP and PXE boot. Signed-off-by: Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2014-12-19-15/+19
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| * | x86: Rename coreboot-serial to x86-serialBin Meng2014-12-18-7/+7
| | | | | | | | | | | | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-02 01:11:56 +0000