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| * | Driver/DDR: Add Freescale DDR driver for ARMYork Sun2013-11-25-4/+227
| | | | | | | | | | | | | | | | | | | | | Make PowerPC specific code conditional so ARM SoCs can reuse this driver. Add DDR3 driver for ARM. Signed-off-by: York Sun <yorksun@freescale.com>
| * | Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xxYork Sun2013-11-25-8/+14
| | | | | | | | | | | | | | | | | | | | | Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com>
| * | Driver/DDR: Moving Freescale DDR driver to a common driverYork Sun2013-11-25-0/+7977
| | | | | | | | | | | | | | | | | | | | | Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2013-11-25-193/+473
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| * | | net: rtl8169: Add support for RTL8168d/8111dThierry Reding2013-11-22-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This chip is compatible with the existing driver, except that it uses BAR2 instead of BAR1 for the I/O memory region. Using this patch I can use the PCIe ethernet interface on the CompuLab Trimslice to boot from the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Patch: 276477
| * | | net: rtl8169: Improve cache maintenanceThierry Reding2013-11-22-8/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of directly calling the low-level invalidate_dcache_range() and flush_cache() functions, provide thin wrappers that take into account alignment requirements. While at it, fix a case where the cache was flushed but should have been invalidated, two cases where the buffer data was flushed instead of the descriptor and a missing cache invalidation before reading the packet data that the NIC just wrote to memory. Signed-off-by: Thierry Reding <treding@nvidia.com> Patch: 276474
| * | | net: zynq_gem: Add d-cache supportSrikanth Thokala2013-11-22-29/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added d-cache support for zynq_gem.c, Observed a difference of +0.8 MiB/s when downloading a file of size of 3007944Bytes. With d-cache OFF: ---------------- Filename 'uImage'. Load address: 0x800 Loading: ################################################################# ################################################################# ################################################################# ########## 1.3 MiB/s done Bytes transferred = 3007944 (2de5c8 hex) With d-cache ON: --------------- Filename 'uImage'. Load address: 0x800 Loading: ################################################################# ################################################################# ################################################################# ########## 2.1 MiB/s done Bytes transferred = 3007944 (2de5c8 hex) Changes on zynq_gem for d-cache support: - Tx and Rx buffers are cache-aligned - Updated logic for invalidating Rx buffers and flushing Tx buffers. - Tx and Rx BD's are allocated from non-cacheable region. (When BDs are cached, we don't see a consistent link) - Use TX BD status intead of txsr status checks. Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | phy: Use general phy code for smsc lan8720aDavid Dueck2013-11-22-1/+2
| | | | | | | | | | | | | | | | Signed-off-by: David Dueck <davidcdueck@googlemail.com>
| * | | phy: Use supported field during autonegotiationDavid Dueck2013-11-22-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code incorrectly detects gigabit capabilities for some 100Mbit/s phys. (lan8720a) Signed-off-by: David Dueck <davidcdueck@googlemail.com>
| * | | net: dm9000: random mac address supportAndrew Ruder2013-11-22-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an unprogrammed EEPROM is attached to a dm9000, the dm9000 will come up with a invalid MAC address of ff:ff:ff:ff:ff:ff. Add code that gets enabled if CONFIG_RANDOM_MACADDR is enabled that generates a random (and valid) locally administered MAC address that allows the system to network boot until a real MAC address can be configured. Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
| * | | drivers/net/e1000: Introduce CONFIG_E1000_NO_NVMRojhalat Ibrahim2013-11-22-5/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The e1000 driver expects to always have some kind of non-volatile memory attached directly to the ethernet controller chip. This means that I would have to add an additional separate flash chip to my custom board just to store essentially the MAC address. Since I don't want to do that, this patch introduces a new config option CONFIG_E1000_NO_NVM. If defined it disables all accesses to the NVM. I have tested the patch with a 82574 controller. Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
| * | | net: phy: atheros: Fix masks for AR8035 and AR8021Fabio Estevam2013-11-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The masks were ignoring the last 4 bits which didn't allow detection differences between the ar8031 and ar8035. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Patch: 288018
| * | | net/phy: Fix the phy id mask of AR8031Chunhe Lan2013-11-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The both AR8031 and AR8035 belong to Atheros 803x serial PHY. So the phy id mask of AR8031 is the same to the phy id mask of AR8035. The right mask value is 0x4fffff. This patch has been tested on the P1010 and P1023. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 287748
| * | | net: tsec: Fix mac addr setup portability, cleanupClaudiu Manoil2013-11-22-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the 32-bit memory access that is not "endianess safe", i.e. not giving the desired byte layout for LE cpus: tempval = *((uint *) (tmpbuf + 4)), where 'char tmpbuf[]'. Free the stack from rendundant local vars: tmpbuf[] and i. Use a portable type (u32) for the 32bit tsec register value holder: tempval. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
| * | | net: tsec: Use portable regs type (uint->u32)Claudiu Manoil2013-11-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use cross arch portable u32 instead of uint for the tsec registers. Remove the typedefs for the register struct definitions in the process. Fix long lines. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
| * | | net: tsec: Use portable types and accessors for BDsClaudiu Manoil2013-11-22-42/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the buffer descriptor (BD) fields cannot be correctly accessed by a little endian processor. This patch fixes the issue by making the access of BDs to be portable among different cpu architectures. Use portable data types for the Rx/Tx buffer descriptor fields. Use portable I/O accessors to insure that the big endian BDs are correctly accessed by little endian cpus too, and to insure proper sync with the H/W. Removed the redundant RTXBD "volatile" type, as proper synchronization around BD data accesses is provided by the I/O accessors now. The "sparse" tool was also used to verify the correctness of these changes. Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
| * | | net: tsec: Fix CamelCase issues around BD codeClaudiu Manoil2013-11-22-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix bufPtr and the rxIdx/ txIdx occurrences to solve the related checkpatch warnings for the coming patches. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
| * | | net: fsl_mdio: Fix warnings for __iomem pointersClaudiu Manoil2013-11-22-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the __iomem address space marker for the tsec pointers to struct tsec_mii_mng memory mapped register regions. This solves the sparse warnings for mixig normal pointers with __iomem pointers for tsec. E.g.: fsl_mdio.c:34:19: warning: incorrect type in argument 1 (different address spaces) fsl_mdio.c:34:19: expected unsigned int volatile [noderef] <asn:2>*addr fsl_mdio.c:34:19: got unsigned int *<noident> [...] tsec.c:91:35: warning: incorrect type in argument 1 (different address spaces) tsec.c:91:35: expected struct tsec_mii_mng *phyregs tsec.c:91:35: got struct tsec_mii_mng [noderef] <asn:2>*phyregs_sgmii [...] tsec.c:680:19: warning: incorrect type in assignment (different address spaces) tsec.c:680:19: expected struct tsec_mii_mng *regs tsec.c:680:19: got struct tsec_mii_mng [noderef] <asn:2>*<noident> [...] Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
| * | | net: tsec: Cleanup tsec regs init and fix __iomem warnsClaudiu Manoil2013-11-22-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove tsec_t typedef. Define macros as getters of tsec and mdio register memory regions, for consistent initialization of various 'regs' fields and also to manage overly long initialization lines. Use the __iomem address space marker to address sparse warnings in tsec.c where IO accessors are used, like: tsec.c:394:19: warning: incorrect type in argument 1 (different address spaces) tsec.c:394:19: expected unsigned int volatile [noderef] <asn:2>*addr tsec.c:394:19: got unsigned int *<noident> [...] Add the __iomem address space marker for the tsec pointers to struct tsec_mii_mng memory mapped register regions. This solves the sparse warnings for mixig normal pointers with __iomem pointers for tsec. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
| * | | net: tsec: Fix priv pointer in tsec_mcast_addr()Claudiu Manoil2013-11-22-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Access to privlist[1] (hardcoded referece to the 2nd tsec's priv area) is neither correct nor does it make sense in the current context. Each tsec dev has access to its own priv instance only, and hence to its own set of group address registers (GADDR) to filter multicast addresses. This fix leads to removal of the unused (faulty) privlist[] and related global static vars. Note that mcast() can be called only after eth_device allocation and init, and hence after priv area allocation, so dev->priv is correctly initialized upon mcast() call. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Patch: 278990
| * | | net: tsec: Fix and cleanup tsec_mcast_addr()Claudiu Manoil2013-11-22-16/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are several implementation issues for tsec_mcast_addr() addressed by this patch: * unmanaged, not portable r/w access to registers; fixed with setbits_be32()/ clrbits_be32() * use of volatile pointers * unnecessary forced cast to u8 for the ether_crc() result * removed redundant parens * corrected some comment slips Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Patch: 279000
| * | | net: Fix mcast function pointer prototypeClaudiu Manoil2013-11-22-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the following compiler warnings when activating CONFIG_MCAST_TFTP: tsec.c: In function 'tsec_mcast_addr': tsec.c:130:2: warning: passing argument 2 of 'ether_crc' makes pointer from integer without a cast [enabled by default] In file included from /work/u-boot-net/include/common.h:874:0, from tsec.c:15: /work/u-boot-net/include/net.h:189:5: note: expected 'const unsigned char *' but argument is of type 'u8' tsec.c: In function 'tsec_initialize': tsec.c:646:13: warning: assignment from incompatible pointer type [enabled by default] eth.c: In function 'eth_mcast_join': eth.c:358:2: warning: passing argument 2 of 'eth_current->mcast' makes integer from pointer without a cast [enabled by default] eth.c:358:2: note: expected 'u32' but argument is of type 'u8 *' In the eth_mcast_join() implementation, eth_current->mcast() takes a u8 pointer to the multicast mac address and not a ip address value as implied by its prototype. Fix parameter type mismatch for tsec_macst_addr() (tsec.c): ether_crc() takes a u8 pointer not a u8 value. mcast() is given a u8 pointer to the multicats mac address. Update parameter type for the rest of mcast() instances. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Patch: 278989
| * | | net: designware: Fix alignment of buffer descriptorsAlexey Brodkin2013-11-22-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's important that buffer descriptors are aligned in accordance to GMAC data bus width (32/64/128-bit). It's safe to align to 128-bit (16-bytes) for every bus width type. If buffer descriptor is improperly aligned GMAC discards lower bits of provided address and as a result reads from improper location that doesn't match expected fields. Commit ef76025a99247cdb8f927a2c9f15400678dfb599 "net: Multiple updates/enhancements to designware.c" introduced another structure member "link_printed" right before buffer descriptors while "padding" member was left untouched. This together with alignment of structure itself to 16-byte boundary forces buffer descriptoprs always to be 4-byte aligned that causes driver complete disfunction if GMAC bus width is 64 or 128-bit. Proposed change makes sure all buffer descriptors are 16-byte (128-bit) aligned. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Patch: 277902
| * | | net: designware: Respect "bus mode" register contents on SW resetAlexey Brodkin2013-11-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "bus mode" register contains lots of fields and some of them don't expect to be written with 0 (zero). So since we're only interested in resetting MAC (which is done with setting the least significant bit of this register with "0") I believe it's better to modify only 1 bit of the register. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Vipin Kumar <vipin.kumar@st.com> Patch: 277864
| * | | net: sh-eth: Add support R8A7791Nobuhiro Iwamatsu2013-11-22-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R8A7791 has the same sh-ether IP core as other SH/rmobile. This patch adds support of R8A7791. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Joe Hershberger <joe.hershberger@gmail.com>
| * | | net, phy: fix AR8031 phy_maskHeiko Schocher2013-11-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AR8035 driver will be never applied because of wrong mask for AR8031 driver. Fix this. Signed-off-by: Heiko Schocher <hs@denx.de> Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 276944
| * | | net: rtl8169: Add support for RTL8168evl/8111evlThierry Reding2013-11-22-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This chip is compatible with other RTL8168 chips and can be found on the NVIDIA Cardhu and Beaver boards. Signed-off-by: Thierry Reding <treding@nvidia.com> Patch: 276475
| * | | net: rtl8169: Fix format stringThierry Reding2013-11-22-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | currticks() is defined as get_timer(0), which returns an unsigned long, so use %lu instead of %d to print the result. Signed-off-by: Thierry Reding <treding@nvidia.com> Patch: 276473
| * | | net: add function to read/write extended registers in Micrel PhyStefano Babic2013-11-22-0/+32
| | | | | | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | net: fix mask for phy Micrel KSZ9031Stefano Babic2013-11-22-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is ↵Bhupesh Sharma2013-11-22-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | detected The 'get_phy_driver' code in 'drivers/net/phy/phy.c' uses the following method to determine which driver is to be loaded for a particular PHY module: list_for_each(entry, &phy_drivers) { drv = list_entry(entry, struct phy_driver, list); if ((drv->uid & drv->mask) == (phy_id & drv->mask)) return drv; } This means that a drv->mask of 0xfffff0 will return incorrect phy driver for the logic above, even if the drv->uid is anything other than something ending with a 0x0. For e.g. if the RTL8211E drv->uid is 0x1cc915 and drv->mask is 0xffffff and the RTL8211B drv->uid is 0x1cc910 and drv->mask is 0xffffff0, then the phy driver selected will always be RTL8211B even though the underlying phy connected on the board is a 8211E module. This patch fixes this issue. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
| * | | net: phy/vitesse: Add support for VSC8514 phy moduleArpit Goel2013-11-22-1/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for VSC8514 PHY module which can be found on Freescale's T1040RDB boards. Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
| * | | net: sh-eth: Add support R8A7790Nobuhiro Iwamatsu2013-11-22-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R8A7790 has the same sh-ether IP core as other SH/rmobile. This patch adds support of R8A7790. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | | net: sh-eth: Add invalidate cache control for rmobile (ARM SoC)Nobuhiro Iwamatsu2013-11-22-5/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sh-eth of rmobile needs to use invalidate_cache* function. This patch adds invalidate_cache* function. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Patch: 268948
| * | | net: sh-eth: Add control for padding size of packet descriptorNobuhiro Iwamatsu2013-11-22-10/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sh-eth can change the alignment size of a packet descriptor according to BUS size. This patch adds this function. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | | net: sh-eth: Change cache API of SHNobuhiro Iwamatsu2013-11-22-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The cache API of SH was changed from dcache_wback_range to flush_dcache_range. sh-eth uses dcache_wback_range. This patch changes to flush_dcache_range. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | | NET: mvgbe: avoid unused variable warning when used without phylib supportSascha Silbe2013-11-22-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid a recently introduced unused variable warning for boards that use mvgbe but not phylib. Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de> Patch: 266334
| * | | phylib: update atheros ar803x phyShengzhou Liu2013-11-22-2/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the common driver. Currently AR8031_driver didn't work for AR8033, hence updated it to have it work on AR8031/AR8033. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2013-11-25-151/+528
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| * | | mtd: nand: omap: add CONFIG_NAND_OMAP_ECCSCHEME for selection of ecc-schemepekon gupta2013-11-21-9/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds new CONFIG_NAND_OMAP_ECCSCHEME, replacing other distributed CONFIG_xx used for selecting NAND ecc-schemes. This patch aims at solving following issues. 1) Currently ecc-scheme is tied to SoC platform, which prevents user to select other ecc-schemes also supported in hardware. like; - most of OMAP3 SoC platforms use only 1-bit Hamming ecc-scheme, inspite the fact that they can use higher ecc-schemes like 8-bit ecc-schemes with software based error detection (OMAP_ECC_BCH4_CODE_HW_DETECTION_SW). - most of AM33xx SoC plaforms use 8-bit BCH ecc-scheme for now, but hardware supports BCH16 ecc-scheme also. 2) Different platforms use different CONFIG_xx to select ecc-schemes, which adds confusion for user while migrating platforms. - *CONFIG_NAND_OMAP_ELM* which enables ELM hardware engine, selects only 8-bit BCH ecc-scheme with h/w based error-correction (OMAP_ECC_BCH8_CODE_HW) whereas ELM hardware engine supports other ecc-schemes also like; BCH4, and BCH16 (in future). - *CONFIG_NAND_OMAP_BCH8* selects 8-bit BCH ecc-scheme with s/w based error correction (OMAP_ECC_BCH8_CODE_HW_DETECTION_SW). - *CONFIG_SPL_NAND_SOFTECC* selects 1-bit Hamming ecc-scheme using s/w library Thus adding new *CONFIG_NAND_OMAP_ECCSCHEME* de-couples ecc-scheme dependency on SoC platform and NAND driver. And user can select ecc-scheme independently foreach board. However, selection some hardware based ecc-schemes (OMAP_ECC_BCHx_CODE_HW) still depends on presence of ELM hardware engine on SoC. (Refer doc/README.nand) Signed-off-by: Pekon Gupta <pekon@ti.com>
| * | | mtd: nand: omap: enable BCH ECC scheme using ELM for generic platformpekon gupta2013-11-21-125/+201
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BCH8_ECC scheme implemented in omap_gpmc.c driver has following favours +-----------------------------------+-----------------+-----------------+ |ECC Scheme | ECC Calculation | Error Detection | +-----------------------------------+-----------------+-----------------+ |OMAP_ECC_BCH8_CODE_HW |GPMC |ELM H/W engine | |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |GPMC |S/W BCH library | +-----------------------------------+-----------------+-----------------+ Current implementation limits the BCH8_CODE_HW only for AM33xx device family. (using CONFIG_AM33XX). However, other SoC families (like TI81xx) also have ELM hardware module, and can support ECC error detection using ELM. This patch - removes CONFIG_AM33xx Thus this driver can be reused by all devices having ELM h/w engine. - adds omap_select_ecc_scheme() A common function to handle ecc-scheme related configurations. This can be used both during device-probe and via user-space u-boot commads to change ecc-scheme. During device probe ecc-scheme is selected based on CONFIG_NAND_OMAP_ELM or CONFIG_NAND_OMAP_BCH8 - enables CONFIG_BCH S/W library (lib/bch.c) required by OMAP_ECC_BCHx_CODE_HW_DETECTION_SW is enabled by CONFIG_BCH. - enables CONFIG_SYS_NAND_ONFI_DETECTION for auto-detection of ONFI compliant NAND devices - updates following README doc doc/README.nand board/ti/am335x/README doc/README.omap3 Signed-off-by: Pekon Gupta <pekon@ti.com> [scottwood@freescale.com: fixed unused variable warning] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | mtd: nand: omap: make am33xx/elm.c as common driver for all OMAPx and AMxxxx ↵pekon gupta2013-11-21-1/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | platforms ELM hardware engine which is used for ECC error detection, is present on all latest OMAP SoC (like OMAP4xxx, OMAP5xxx, DRA7xxx, AM33xx, AM43xx). Thus ELM driver should be moved to common drivers/mtd/nand/ folder so that all SoC having on-chip ELM hardware engine can re-use it. This patch has following changes: - mv arch/arm/include/asm/arch-am33xx/elm.h arch/arm/include/asm/omap_elm.h - mv arch/arm/cpu/armv7/am33xx/elm.c drivers/mtd/nand/omap_elm.c - update Makefiles - update #include <asm/elm.h> - add CONFIG_NAND_OMAP_ELM to compile driver/mtd/nand/omap_elm.c and include in all board configs using AM33xx SoC platform. Signed-off-by: Pekon Gupta <pekon@ti.com>
| * | | mtd: atmel_nand: use dev_xxx instead of printkWu, Josh2013-11-21-11/+11
| | | | | | | | | | | | | | | | Signed-off-by: Josh Wu <josh.wu@atmel.com>
| * | | mtd: atmel_nand: don't print bit correction message in driverWu, Josh2013-11-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since for some MLC nand, bit errors happened too often. Just disable it to avoid noise Signed-off-by: Josh Wu <josh.wu@atmel.com>
| * | | mtd: atmel_nand: enable PMECC support for 8k bytes page NAND flashWu, Josh2013-11-21-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | increase the delay to 75us to support the 8k bytes page nand flash Signed-off-by: Josh Wu <josh.wu@atmel.com>
| * | | mtd/ifc: Add support of 8K page size NAND flashPrabhakar Kushwaha2013-11-21-2/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Liu Po <po.liu@freescale.com>
| * | | mtd: move & update nand_ecclayout structure (plus board changes)Prabhakar Kushwaha2013-11-21-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nand_ecclayout is present in mtd.h at Linux. Move this structure to mtd.h to comply with Linux. Also, increase the ecc placement locations to 640 to suport device having writesize/oobsize of 8KB/640B. This means that the maximum oobsize has gone up to 640 bytes and consequently the maximum ecc placement locations have also gone up to 640. Changes from Prabhabkar's version (squashed into one patch to preserve bisectability): - Added _LARGE to MTD_MAX_*_ENTRIES This makes the names match current Linux source, and resolves a conflict between http://patchwork.ozlabs.org/patch/280488/ and http://patchwork.ozlabs.org/patch/284513/ The former was posted first and is closer to matching Linux, but unlike Linux it does not add _LARGE to the names. The second adds _LARGE to one of the names, and depends on it in a subsequent patch (http://patchwork.ozlabs.org/patch/284512/). - Made max oobfree/eccpos configurable, and used this on tricorder, alpr, ASH405, T4160QDS, and T4240QDS (these boards failed to build for me without doing so, due to a size increase). On tricorder SPL, this saves 2576 bytes (and makes the SPL build again) versus the new default of 640 eccpos and 32 oobfree, and saves 336 bytes versus the old default of 128 eccpos and 8 oobfree. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Vipin Kumar <vipin.kumar@st.com> [scottwood@freescale.com: changes as described above] Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Thomas Weber <weber@corscience.de> Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Cc: Stefan Roese <sr@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Tom Rini <trini@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | driver/mtd/ifc: Read Status while programming NAND flashPrabhakar Kushwaha2013-11-13-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | as per controller description, "While programming a NAND flash, status read should never skipped. Because it may happen that a new command is issued to the NAND Flash, even when the device has not yet finished processing the previous request. This may result in unpredictable behaviour." IFC controller never polls for R/B signal after command send. It just return control to software. This behaviour may not occur with NAND flash access. because new commands are sent after polling R/B signal. But it may happen in scenario where GPCM-ASIC and NAND flash device are working simultaneously. Update the controller driver to take care of this requirement Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| * | | MTD: atmel_nand: support for software BCH ECCBo Shen2013-11-13-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add possible to use software BCH ECC for atmel nand driver Signed-off-by: Bo Shen <voice.shen@gmail.com>
* | | | bios_emulator: delete an unnecessary include pathMasahiro Yamada2013-11-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | -I$(TOPDIR)/include is defined in the top config.mk. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
generated by cgit v1.1 at 2024-12-17 00:44:07 +0000