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* omap-gpmc: use SECTOR_BYTES instead of hardcoded valueLadislav Michl2017-01-14-4/+4
| | | | | | | Replace hardcoded value with defined constant SECTOR_BYTES. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* Kconfig: CONFIG_OF_PLATDATA doesn't really existTom Rini2017-01-14-1/+1
| | | | | | | There is no CONFIG_OF_PLATDATA, only CONFIG_SPL_OF_PLATDATA, so rename the two references to CONFIG_OF_PLATDATA to CONFIG_SPL_OF_PLATDATA. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of http://git.denx.de/u-boot-mmcTom Rini2017-01-13-6/+6
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| * mmc: sunxi: revive depends on UART0_PORT_FMasahiro Yamada2017-01-13-1/+1
| | | | | | | | | | | | | | | | | | Commit f401e907fcbc ("ARM: sunxi: remove bare default for CONFIG_MMC") dropped "depends on UART0_PORT_F", but it is still needed. Revive it as a prerequisite of CONFIG_MMC_SUNXI. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * mmc: pic32_sdhci: rename {pci->pic}32_sdhci_get_cdMasahiro Yamada2017-01-13-2/+2
| | | | | | | | | | | | I suspect this is a typo. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * mmc: sdhci: fix NULL pointer access when host->ops is not setMasahiro Yamada2017-01-13-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until recently, sdhci_ops was used only for overriding IO accessors. (so, host->ops was not set by any drivers except bcm2835_sdhci.c) Now, we have more optional callbacks, get_cd, set_control_reg, and set_clock. However, the code if (host->ops->get_cd) host->ops->get_cd(host); ... expects host->ops is set for all drivers. Commit 5e96217f0434 ("mmc: pic32_sdhci: move the code to pic32_sdhci.c") and commit 62226b68631b ("mmc: sdhci: move the callback function into sdhci_ops") added sdhci_ops for pic32_sdhci.c and s5p_sdhci.c, but the other drivers still do not (need not) set host->ops because all callbacks in sdhci_ops are optional. host->ops must be checked to avoid the system crash caused by NULL pointer access. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | net: gmac_rockchip: Add Rockchip GMAC driverSjoerd Simons2017-01-11-0/+162
| | | | | | | | | | | | | | | | | | | | | | Add a new driver for the GMAC ethernet interface present in Rockchip RK3288 SOCs. This driver subclasses the generic design-ware driver to add the glue needed specifically for Rockchip. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: designware: Export the operation functionsSimon Glass2017-01-11-10/+18
| | | | | | | | | | | | | | | | | | Export all functions so that drivers can use them, or not, as the need arises. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: designware: Split the link init into a separate functionSimon Glass2017-01-11-2/+24
| | | | | | | | | | | | | | | | | | | | With rockchip we need to make adjustments after the link speed is set but before enabling received/transmit. In preparation for this, split these two pieces into separate functions. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: designware: Adjust dw_adjust_link() to return an errorSimon Glass2017-01-11-4/+8
| | | | | | | | | | | | | | | | This function can fail, so return the error if there is one. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: designware: Export various functions/struct to allow subclassingSjoerd Simons2017-01-11-3/+7
| | | | | | | | | | | | | | | | | | | | | | To allow other DM drivers to subclass the designware driver various functions and structures need to be exported. Export these. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Romain Perier <romain.perier@collabora.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | rockchip: video: fix mpixelclock in rockchip HDMINickey Yang Nickey Yang2017-01-11-10/+10
| | | | | | | | | | | | Correct mpixelclock errors in rockchip_phy_config[] and rockchip_mpll_cfg[]. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
* | mmc: rockchip_sdhci: add clock init for mmcKever Yang2017-01-11-2/+17
|/ | | | | | | Init the clock rate to max-frequency from dts with clock driver api. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* power_i2c.c: Fix unused variable warningTom Rini2017-01-11-1/+0
| | | | | | | | The variable ret was added but never set as we did not make calls to other functions that we needed to check the return value on. Fixes: 505cf4750ae5 ("power: change from meaningless value to error number") Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'xilinx-for-v2017.03' of git://www.denx.de/git/u-boot-microblazeTom Rini2017-01-11-37/+279
|\ | | | | | | | | | | | | | | | | | | Xilinx changes for v2017.03 - ATF handoff - DT syncups - gem: Use wait_for_bit(), add simple clk support - Simple clk driver for ZynqMP - Other small changes
| * xilinx_phy: Pass correct pointer to fdtdec_get_int()Kamensky Ivan2017-01-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | This patch fixes incorrect pointer on offset device in device tree blob. When using with the component "Ethernet 1G/2.5G BASE-X PCS/PMA or SGMII" it does not understand what type is XAE_PHY_TYPE_1000BASE_X and trying to change frequency. Signed-off-by: Kamensky Ivan <kamensky.ivan@mail.ru> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * i2c: cdns: Add additional compatible string for r1p14 of the IP.Moritz Fischer2017-01-10-0/+1
| | | | | | | | | | | | | | | | | | Adding additional compatible string for version 1.4 of the IP block. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: zynq_gem: Use clock driver for ZynqMPSiva Durga Prasad Paladugu2017-01-10-0/+18
| | | | | | | | | | | | | | | | | | Enable and use the clock driver routine defined in clock driver toset required clock appropriately. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * clk: zynqmp: Add clock driver support for zynqmpSiva Durga Prasad Paladugu2017-01-10-0/+249
| | | | | | | | | | | | | | | | | | Add basic clock driver support for zynqmp which sets the required clock for GEM controller Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * fpga: zynqmp: Remove empty functionsMichal Simek2017-01-10-12/+0
| | | | | | | | | | | | | | Xilinx core files will take care about it. There is no need to have these functions because they do nothing. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: gem: Use wait_for_bit() instead of private mdio_wait()Michal Simek2017-01-10-23/+9
| | | | | | | | | | | | | | Using generic wait_for_bit() implementation instead of using private wait function. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | mmc: move more driver config options to KconfigMasahiro Yamada2017-01-11-7/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move (and rename) the following CONFIG options to Kconfig: CONFIG_DAVINCI_MMC (renamed to CONFIG_MMC_DAVINCI) CONFIG_OMAP_HSMMC (renamed to CONFIG_MMC_OMAP_HS) CONFIG_MXC_MMC (renamed to CONFIG_MMC_MXC) CONFIG_MXS_MMC (renamed to CONFIG_MMC_MXS) CONFIG_TEGRA_MMC (renamed to CONFIG_MMC_SDHCI_TEGRA) CONFIG_SUNXI_MMC (renamed to CONFIG_MMC_SUNXI) They are the same option names as used in Linux. This commit was created as follows: [1] Rename the options with the following command: find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \ -type f -print | xargs sed -i -e ' s/CONFIG_DAVINCI_MMC/CONFIG_MMC_DAVINCI/g s/CONFIG_OMAP_HSMMC/CONFIG_MMC_OMAP_HS/g s/CONFIG_MXC_MMC/CONFIG_MMC_MXC/g s/CONFIG_MXS_MMC/CONFIG_MMC_MXS/g s/CONFIG_TEGRA_MMC/CONFIG_MMC_SDHCI_TEGRA/g s/CONFIG_SUNXI_MMC/CONFIG_MMC_SUNXI/g ' [2] Commit the changes [3] Create entries in driver/mmc/Kconfig. (copied from Linux) [4] Move the options with the following command tools/moveconfig.py -y -r HEAD \ MMC_DAVINCI MMC_OMAP_HS MMC_MXC MMC_MXS MMC_SDHCI_TEGRA MMC_SUNXI [5] Sort and align drivers/mmc/Makefile for readability Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
* | mmc: move DesignWare-based drivers to KconfigMasahiro Yamada2017-01-11-5/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move (and rename) the following CONFIG options to Kconfig: CONFIG_EXYNOS_DWMMC (renamed to CONFIG_MMC_DW_EXYNOS) CONFIG_HIKEY_DWMMC (renamed to CONFIG_MMC_DW_K3) CONFIG_SOCFPGA_DWMMC (renamed to CONFIG_MMC_DW_SOCFPGA) The "HIKEY" is a board name, so it is not suitable for the MMC controller name. I am following the name used in Linux. This commit was generated as follows: [1] Rename the config options with the following command: find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \ -type f -print | xargs sed -i -e ' s/CONFIG_EXYNOS_DWMMC/CONFIG_MMC_DW_EXYNOS/g s/CONFIG_HIKEY_DWMMC/CONFIG_MMC_DW_K3/g s/CONFIG_SOCFPGA_DWMMC/CONFIG_MMC_DW_SOCFPGA/g ' [2] Commit the changes [3] Create the entries in drivers/mmc/Kconfig (with default y for EXYNOS and SOCFPGA) [4] Run the following: tools/moveconfig.py -y -r HEAD MMC_DW_EXYNOS MMC_DW_K3 MMC_DW_SOCFPGA [5] Sort and align drivers/mmc/Makefile for readability [6] Clean-up doc/README.socfpga by hand Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
* | mmc: move CONFIG_DWMMC to Kconfig, renaming to CONFIG_MMC_DWMasahiro Yamada2017-01-11-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit was created as follows: [1] Rename the option with the following command: find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \ -type f -print | xargs sed -i -e 's/CONFIG_DWMMC/CONFIG_MMC_DW/g' [2] create the entry for MMC_DW in drivers/mmc/Kconfig (the prompt and help were copied from Linux) [3] run "tools/moveconfig.py -y MMC_DW" [4] add "depends on MMC_DW" to the MMC_DW_ROCKCHIP entry [5] Clean-up doc/README.socfpga by hand Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
* | mmc: rename CONFIG_ROCKCHIP_DWMMC to CONFIG_MMC_DW_ROCKCHIPMasahiro Yamada2017-01-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | I am trying to make all DesignWare-based driver options prefixed with CONFIG_MMC_DW_. This commit was generated as follows: find . -name .git -prune -o -type f -print | \ xargs sed -i -e 's/ROCKCHIP_DWMMC/MMC_DW_ROCKCHIP/g' Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
* | power: change from meaningless value to error numberJaehoon Chung2017-01-11-67/+64
| | | | | | | | | | | | | | | | '-1' is absolutely meaningless value. This patch changed from meaningless value to error number. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | mmc: uniphier-sd: fix Kconfig dependencyMasahiro Yamada2017-01-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some MMC drivers describe operations with the DM_MMC_OPS form, but there are still several drivers with older implementation. We can not compile drivers from different groups at the same time because the core framework is shared with #ifdef CONFIG_DM_MMC_OPS. Every driver should have "depends on DM_MMC_OPS" (or !DM_MMC_OPS) explicitly to express which framework it is based on. This will avoid enabling drivers with incompatible interface at the same time. It is incorrect to make a driver "select DM_MMC_OPS". While we are here, add "depends on OF_CONTROL" as well because this driver can be configured only by Device Tree. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | mmc: sdhci-cadence: add Cadence SD4HC supportMasahiro Yamada2017-01-11-0/+138
| | | | | | | | | | | | Add a driver for the Cadence SD4HC SD/SDIO/eMMC Controller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | mmc: sdhci: combine the Host controller v3.0 feature into one conditionJaehoon Chung2017-01-11-10/+7
| | | | | | | | | | | | It doesn't need to seperate the condition. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: sdhci: remove the SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWERJaehoon Chung2017-01-11-3/+0
| | | | | | | | | | | | Ther is no usage anywhere. It doesn't need to maintain this bit. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: sdhci: move the callback function into sdhci_opsJaehoon Chung2017-01-11-7/+10
| | | | | | | | | | | | | | | | callback function should be moved into sdhci_ops struct. Other controller can use these ops for controlling clock or their own specific register. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: s5p_sdhci: add the s5p_set_clock functionJaehoon Chung2017-01-11-1/+7
| | | | | | | | | | | | | | | | Add the s5p_set_clock function. It's not good that "set_mmc_clk" is assigned directly. In future, it should be changed to use the clock framework. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: change the set_ios return type from void to intJaehoon Chung2017-01-11-29/+59
| | | | | | | | | | | | To maintain consistency, set_ios type of legacy mmc_ops changed to int. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: sdhci: remove the SDHCI_QUIRK_NO_CDJaehoon Chung2017-01-11-5/+3
| | | | | | | | | | | | | | This quirk doesn't need anymore. It's replaced to get_cd callback function. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: pic32_sdhci: move the code to pic32_sdhci.cJaehoon Chung2017-01-11-6/+17
| | | | | | | | | | | | | | | | This code is used for only pic32_sdhci controller. To remove the "#ifdef", moves to pic32_sdhci.c. And use the get_cd callback function. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: sdhci: remove the unused code about testing Card detectJaehoon Chung2017-01-11-11/+0
| | | | | | | | | | | | This code is dead code..There is no usage anywhere. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: sdhci: disable the 8bit mode when host doesn't support itJaehoon Chung2017-01-11-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Buswidth is depeneded on Hardware schematic. Evne though host can support the 8bit buswidth, if hardware doesn't support 8bit mode, it doesn't work fine. So the buswidth mode selection leaves a matter in each SoC drivers. On the contrary to this, hardware supports 8bit mode, but host doesn't support it. then controller has to disable the MMC_MODE_8BIT. (Host can check whether 8bit mode is supported or not, since V3.0) Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2017-01-10-15/+174
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| * | drivers: usb: gadget: ether/rndis: convert driver to adopt device driver modelMugunthan V N2017-01-09-15/+174
| |/ | | | | | | | | | | Adopt usb ether gadget and rndis driver to adopt driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2017-01-10-1/+1
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| * spl: sunxi: Fix build error with CONFIG_SPL_SPI_SUNXIPriit Laes2017-01-04-1/+1
| | | | | | | | | | | | | | Fix typo introduced in ebc4ef61d76fc182773fe225151adc9b913c62eb Signed-off-by: Priit Laes <plaes@plaes.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2017-01-04-2/+2
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| * | pci: kconfig: fix spelling in descriptionMarcel Ziswiler2017-01-03-1/+1
| | | | | | | | | | | | | | | | | | | | | Fix 'driver model' rather than 'driver mode' in description. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | video: tegra: fix spelling in commentMarcel Ziswiler2017-01-03-1/+1
| |/ | | | | | | | | | | | | Get rid of spurious 'are' in the comment. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2017-01-04-13/+37
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| * | mtd: nand: mxs_nand_spl: Fix to remove twise 'NAND' printJagan Teki2017-01-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPL from nand will print 'NAND' in boot_from_devices based on the image_loader name, remove the extra 'NAND ' in mxs_nand_spl driver. Original behaviour: ------------------- U-Boot SPL 2017.01-rc2-gf84dd8b (Jan 02 2017 - 22:24:19) Trying to boot from NANDNAND : 512 MiB After the fix: ------------- U-Boot SPL 2017.01-rc2-gf84dd8b-dirty (Jan 02 2017 - 23:17:00) Trying to boot from NAND: 512 MiB Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jagan@openedev.com>
| * | spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possibleVignesh R2017-01-04-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Section 11.15.4.9.1 Indirect Read Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface reads until the last word of an indirect transfer So, make sure that QSPI indirect reads are 32 bit sized except for the final read. If the rxbuf is unaligned then use bounce buffer, so that readsl() can be used instead of readsb() to avoid non 32-bit accesses. [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possibleVignesh R2017-01-04-6/+20
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that QSPI indirect writes are 32 bit sized except for the last write. If the txbuf is unaligned then use bounce buffer to avoid data aborts. So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER for all boards that use Cadence QSPI driver. [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLSYork Sun2017-01-04-64/+64
| | | | | | | | | | | | | | | | These two macros are used for the same thing, the total number of DDR controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and merge existing usage. Signed-off-by: York Sun <york.sun@nxp.com>
* | ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to KconfigYork Sun2017-01-04-0/+14
| | | | | | | | | | | | | | | | Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing usage in ls102xa and fsl-layerscape. Remove all powerpc macros in config header and board header files. Signed-off-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-10-30 21:04:54 +0000