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* dm: Use dev_get_addr() where possibleSimon Glass2015-08-31-29/+26
| | | | | | | | | | This is a convenient way for a driver to get the hardware address of a device, when regmap or syscon are not being used. Change existing callers to use it as an example to others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
* serial: uniphier: drop platform data supportMasahiro Yamada2015-08-31-26/+15
| | | | | | | | | | This driver is enabled only for UniPhier SoCs and ARCH_UNIPHIER now selects OF_CONTROL and SPL_OF_CONTROL. This driver no longer needs to support platform data configuration. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mtd: denali_spl: do not allocate page_buffer in .bss sectionMasahiro Yamada2015-08-30-20/+12
| | | | | | | | | | | | | | | | | | | Since commit 2580a2a7e719 ("mtd: nand: Increase max sizes of OOB and Page size"), three boards (ph1_ld4, ph1_pro4, ph1_sld8) fail to build with the following error message: arm-linux-gnueabi-ld.bfd: SPL image plus BSS too big They compile drivers/mtd/nand/denali_spl.c and it has a page_buffer as static data: static uint8_t page_buffer[NAND_MAX_PAGESIZE]; This buffer required 8KB in .bss section before that commit and now it has been increased to 16KB. Given limited code/memory size for SPL, it is not a good idea to allocate a page buffer statically. In the first place, the load address 'dst' can be used as a page buffer. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* TI PHY: Add support to control 2nd USB PHY in DRA7xx/AM57xxKishon Vijay Abraham I2015-08-28-4/+11
| | | | | | | | Added support to power on/power off the second USB PHY present in DRA7xx and AM57xx. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* usb: dwc3: dwc3-omap: Use the clear register inorder to clear the interruptsKishon Vijay Abraham I2015-08-28-18/+28
| | | | | | | | | | Writing "0x00" to the USBOTGSS_IRQENABLE_SET_MISC and USBOTGSS_IRQENABLE_SET_0 doesn't disable the interrupts. Used USBOTGSS_IRQENABLE_CLR_MISC and USBOTGSS_IRQENABLE_CLR_0 instead. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* mtd/nand/ubi: assortment of alignment fixesMarcel Ziswiler2015-08-28-1/+1
| | | | | | | | | | | | | | Various U-Boot adoptions/extensions to MTD/NAND/UBI did not take buffer alignment into account which led to failures of the following form: ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108 ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108 Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Scott Wood <scottwood@freescale.com> [trini: Add __UBOOT__ hunk to lib/zlib/zutil.c due to malloc.h in common.h] Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-08-26-413/+423
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| * dm: core: Fix code reentrancy issue in device_probe_child()Bin Meng2015-08-26-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The device might have already been probed during the call to device_probe() on its parent device (e.g. PCI bridge devices). In its parent device's probe routine, it might probe all of its child devices via device_probe() thus the codes reenter device_probe_child(). To support code reentrancy, test these allocated memory against NULL to avoid memory leak, and return to the caller if dev->flags has DM_FLAG_ACTIVATED set after device_probe() returns, so that we don't mess up the device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: pci: Optimize pci_uclass_post_bind()Bin Meng2015-08-26-0/+7
| | | | | | | | | | | | | | | | If there is no pci device listed in the device tree, don't bother scanning the device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * video: ct69000: Remove unused codesBin Meng2015-08-26-21/+0
| | | | | | | | | | | | | | | | Remove unused CONFIG_USE_CPCIDVI wrapped codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
| * video: cfb_console: Allow VGA device to work without i8042 keyboardBin Meng2015-08-26-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | So far if CONFIG_VGA_AS_SINGLE_DEVICE is not defined, the VGA device will try to initialize a keyboard device (for x86, it is i8042). But if i8042 controller initialization fails (eg: there is no keyboard connected to the PS/2 port), drv_video_init() just simply returns. This kills the opportunity of using a usb keyboard later with the vga console, as the vga initialization part is actually ok, only keyboard part fails. Change the code logic to allow this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
| * x86: i8042: Correctly initialize the controllerBin Meng2015-08-26-22/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing i8042 keyboard controller driver has some issues. First of all, it does not issue a self-test command (0xaa) to the controller at the very beginning. Without this, the controller does not respond to any command at all. Secondly, it initializes the configuration byte register to turn on the keyboard's interrupt, as U-Boot does not normally allow interrupts to be processed. Finally, at the end of the initialization routine, it wrongly sets the controller to disable all interfaces including both keyboard and mouse. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: i8042: Clean up the driver per coding conventionBin Meng2015-08-26-112/+118
| | | | | | | | | | | | | | | | | | - Rename CamelCase variables to conform U-Boot coding convention - Rename wait_until_kbd_output_full() to kbd_output_full() - Change to use macros for i8042 command and control register bits Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: i8042: Reorder static functionsBin Meng2015-08-26-268/+222
| | | | | | | | | | | | | | | | Reorder those static function so that their declarations can be removed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: i8042: Remove unused codesBin Meng2015-08-26-17/+0
| | | | | | | | | | | | | | Remove unused CONFIG_USE_CPCIDVI wrapped codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: gpio: Tidy up gpio_ich6_get_base() and callersSimon Glass2015-08-26-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This function can return an error. Correct the detection of this error so that it works even with large 32-bit addresses. The return value is set up for returning an I/O address but the function is also used to return a memory-mapped address. Adjust the return code to make this work. Also add a bit more debugging. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: gpio: Correct calls to _ich6_gpio_set_direction()Simon Glass2015-08-26-2/+2
| | | | | | | | | | | | | | These calls seem to be incorrect. The function expects an I/O address but the existing callers pass the value at an I/O address. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: pci: Save devfn without bus number in pci_uclass_child_post_bind()Bin Meng2015-08-26-2/+2
| | | | | | | | | | | | | | | | In pci_uclass_child_post_bind(), bdf is extracted from fdt_pci_addr. Mask bus number before save it to pplat->devfn. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: superio: Add keyboard controller support to smsc_lpc47m driverBin Meng2015-08-26-1/+12
| | | | | | | | | | | | | | | | | | Add an api to enable and configure the integrated keyboard controller on SMSC LPC47m superio chipset. It also adds several macros to help future extension. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Call fsp_init_phase_pci() in pci_uclass_post_probe()Bin Meng2015-08-26-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per Intel FSP specification, we should call FSP notify API to inform FSP that PCI enumeration has been done so that FSP will do any necessary initialization as required by the chipset's BIOS Writer's Guide (BWG). Unfortunately we have to put this call here as with driver model, the enumeration is all done on a lazy basis as needed, so until something is touched on PCI it won't happen. Note we only call this after U-Boot is relocated and root bus has finished probing. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: pci: Support selected device/driver binding before relocationBin Meng2015-08-26-11/+30
| | | | | | | | | | | | | | | | | | | | | | On some platforms pci devices behind bridge need to be probed (eg: a pci uart on recent x86 chipset) before relocation. But we won't bind all devices found during the enumeration. Only devices whose driver with DM_FLAG_PRE_RELOC set will be bound. Any other generic devices except bridges won't be bound. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Set up video framebuffer for coreboot before loading kernelBin Meng2015-08-26-2/+0
| | | | | | | | | | | | | | | | | | Currenlty we only set up video framebuffer when VIDEO_VESA driver is used. With coreboot, VIDEO_COREBOOT driver is used instead. Since we already saved VESA mode in the VIDEO_COREBOOT driver, now we can also set up video framebuffer for coreboot before loading Linux kernel. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * video: coreboot: Save VESA mode for future useBin Meng2015-08-26-1/+25
| | | | | | | | | | | | | | | | When booting as a coreboot payload, the framebuffer details are passed from coreboot via configuration tables. We save these information into vesa_mode_info structure for future use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * net: e1000: Fix build warnings for 32-bitBin Meng2015-08-26-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 6497e37 "net: e1000: Support 64-bit physical address" causes compiler warnings on 32-bit U-Boot build below. drivers/net/e1000.c: In function 'e1000_configure_tx': drivers/net/e1000.c:4982:2: warning: right shift count >= width of type [enabled by default] drivers/net/e1000.c: In function 'e1000_configure_rx': drivers/net/e1000.c:5126:2: warning: right shift count >= width of type [enabled by default] This commit fixes the build warnings. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge git://git.denx.de/u-boot-nand-flashTom Rini2015-08-26-630/+2350
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| * mtd: nand: mxs invalidate dcache before DMA readPeng Fan2015-08-25-0/+6
| | | | | | | | | | | | | | | | | | | | | | Follow linux dma flow: Before DMA read, be sure to invalidate the cache over the address range of DMA buffer to prevent cache coherency problems. After DMA read, invalidate dcache again. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com>
| * mtd: nand: mxs support oobsize bigger than 512Peng Fan2015-08-25-9/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If ecc chunk data size is 512 and oobsize is bigger than 512, there is a chance that block_mark_bit_offset conflicts with bch ecc area. The following graph is modified from kernel gpmi-nand.c driver with each data block 512 bytes. We can see that Block Mark conflicts with ecc area from bch view. We can enlarge the ecc chunk size to avoid this problem to those oobsize which is larger than 512. | P | |<----------------------------------------------------------------->| | | | (Block Mark) | | P' | | | | |<--------------------------------------------------->| D | | O'| | |<--------->| |<->| V V V V V +---+--------------+-+--------------+-+--------------+-+----------+-+---+ | M | data |E| data |E| data |E| data |E| | +---+--------------+-+--------------+-+--------------+-+----------+-+---+ ^ ^ | O | |<---------------->| P : the page size for BCH module. E : The ECC strength. G : the length of Galois Field. N : The chunk count of per page. M : the metasize of per page. C : the ecc chunk size, aka the "data" above. P': the nand chip's page size. O : the nand chip's oob size. O': the free oob. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-By: Tim Harvey <tharvey@gateworks.com>
| * mtd: nand: Add mvebu (PXA / AXP / A38x) NAND device driverStefan Roese2015-08-25-0/+1693
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cloned from the Linux driver v4.2.0-rc2. Plus some patches from Antoine Tenart enabling controller initialization and ONFI timing support: http://lists.infradead.org/pipermail/linux-mtd/2015-July/060197.html Please note that this driver needs the Linux NAND subsystem sync to v4.1 from Scott to be applied: https://www.mail-archive.com/u-boot@lists.denx.de/msg175762.html Otherwise it will not compile. Tested on the Marvell Armada XP DB-MV784MP-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Antoine Tenart <antoine.tenart@free-electrons.com> Cc: Ezeguil Garcia <ezequiel.garcia@free-electrons.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Scott Wood <scottwood@freescale.com>
| * nand: Sync with Linux v4.1Scott Wood2015-08-25-193/+573
| | | | | | | | | | | | | | | | | | | | | | Update the NAND code to match Linux v4.1. The previous sync was from Linux v3.15 in commit 4e67c57125290b25. CONFIG_SYS_NAND_RESET_CNT is removed, as the upstream Linux code now has its own timeout. Plus, CONFIG_SYS_NAND_RESET_CNT was undocumented and not selected by any board. Signed-off-by: Scott Wood <scottwood@freescale.com>
| * mtd: Introduce mtd_block_isreserved()Ezequiel Garcia2015-08-25-2/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In addition to mtd_block_isbad(), which checks if a block is bad or reserved, it's needed to check if a block is reserved only (but not bad). This commit adds an MTD interface for it, in a similar fashion to mtd_block_isbad(). While here, fix mtd_block_isbad() so the out-of-bounds checking is done before the callback check. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> [scottwood: Cherry-picked from Linux 8471bb73ba10ed67] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * nand: Remove __UBOOT__ ifdefsScott Wood2015-08-25-428/+4
| | | | | | | | | | | | | | I didn't approve the patch that added them. Get them out of the way before doing a sync. Signed-off-by: Scott Wood <scottwood@freescale.com>
* | lcd: pxa: clean-up include file orderMarcel Ziswiler2015-08-24-5/+4
| | | | | | | | | | | | | | Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* | usb: pxa27x_udc: clean-up include file orderMarcel Ziswiler2015-08-24-3/+2
| | | | | | | | | | | | | | Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* | serial: pxa: clean-up include file orderMarcel Ziswiler2015-08-24-2/+2
| | | | | | | | | | | | | | Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* | arm: pxa: mmc: clean-up include file orderMarcel Ziswiler2015-08-24-5/+3
|/ | | | | | | Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* Merge git://git.denx.de/u-boot-socfpgaTom Rini2015-08-23-2/+177
|\ | | | | | | | | | | | | | | | | | | | | Conflicts: configs/socfpga_arria5_defconfig configs/socfpga_cyclone5_defconfig configs/socfpga_socrates_defconfig Merged these by hand and re-ran savedefconfig on them. Signed-off-by: Tom Rini <trini@konsulko.com>
| * gpio: Add DW APB GPIO driverMarek Vasut2015-08-23-0/+175
| | | | | | | | | | | | | | | | Add driver for the DesignWare APB GPIO IP block. This driver is DM capable and probes from DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
| * ddr: altera: Repair uninited variableMarek Vasut2015-08-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following problem: drivers/ddr/altera/sequencer.c: In function 'sdram_calibration_full': drivers/ddr/altera/sequencer.c:1943:25: warning: 'found_failing_read' may be used uninitialized in this function [-Wmaybe-uninitialized] if (found_passing_read && found_failing_read) ^ drivers/ddr/altera/sequencer.c:1803:26: note: 'found_failing_read' was declared here u32 found_passing_read, found_failing_read, initial_failing_dtap; ^ Signed-off-by: Marek Vasut <marex@denx.de>
| * ddr: altera: Replace float multiplication with integer oneMarek Vasut2015-08-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This gem is really really rare, there was an actual float used in the Altera DDR init code, which pulled in floating point ops from the libgcc, just wow. Since we don't support floating point operations the same way Linux does not support them, replace this with an integer multiplication and division combo. This removes some 2kiB of size from the SPL as the floating point ops are no longer pulled in from libgcc. This was detected by enabling CONFIG_USE_PRIVATE_LIBGCC=y , which does not contain the floating point bits. Signed-off-by: Marek Vasut <marex@denx.de>
* | net: e1000: Add Kconfig optionsSimon Glass2015-08-21-7/+32
| | | | | | | | | | | | | | Add Kconfig options in preparation for moving boards to use Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: e1000: Convert to driver modelSimon Glass2015-08-21-0/+142
| | | | | | | | | | | | | | | | | | Update this driver to support driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Apalis T30 2GB on Apalis Evaluation Board
* | net: e1000: Prepare for driver model conversionSimon Glass2015-08-21-200/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since struct eth_device does not exist with CONFIG_DM_ETH defined, avoid using it in the driver unless necessary. Most of the time it is better to pass the private driver pointer anyway. Also refactor the code so that code that the driver model implementation will share are available in functions that can be called. Add stubs where necessary. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Apalis T30 2GB on Apalis Evaluation Board
* | net: e1000: Move #include of common.h to the C filesSimon Glass2015-08-21-1/+2
| | | | | | | | | | | | | | | | | | | | | | We cannot currently include any header files in the C files since common.h needs to be included first, and it is in the header file. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Apalis T30 2GB on Apalis Evaluation Board
* | net: e1000: Support 64-bit physical addressMingkai Hu2015-08-21-4/+4
|/ | | | | | | | | High 32-bit address is needed when u-boot runs in 64-bit space. Tested on armv8-based LS2085ARDB. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* usb: dwc2: Rename to dwc2_usbMarek Vasut2015-08-19-1/+1
| | | | | | | This driver is not used only on exynos, but also on Altera SoCFPGA, HiSilicon SoCs, RPi etc, so rename it accordingly to prevent confusion. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: dwc2: Add original Synopsys compat stringMarek Vasut2015-08-19-0/+1
| | | | | | Add the Synopsys compatible string. This is used in SoCFPGA DT files. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: gadget: ether: populate _reset_ callbackKishon Vijay Abraham I2015-08-19-0/+1
| | | | | | | | | | | populate _reset_ callback to the USB ethernet gadget since UDC core expects every gadget driver to have the reset callback. This shouldn't be needed once the ethernet gadget driver is adapted to use the composite driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* usb: host: xhci-omap: invoke board_usb_cleanup in xhci_hcd_stopKishon Vijay Abraham I2015-08-19-0/+1
| | | | | | | | | | | | xhci omap driver has board_usb_init in xhci_hcd_init but doesn't have the corresponding cleanup function in xhci_hcd_stop. Fix it here by invoking board_usb_cleanup() in xhci_hcd_stop(). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* usb: gadget: ether: Perform board initialization from ethernet gadget driverKishon Vijay Abraham I2015-08-19-0/+4
| | | | | | | | | | | Ethernet gadget driver can be used both by both SPL and u-boot. Since usb_eth_init() is the entry point for ethernet gadget driver, perform board initialization there. Also perform the cleanup in usb_eth_halt. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* usb: xhci: Fix a potential NULL pointer dereferenceSergey Temerkhanov2015-08-19-5/+14
| | | | | | | | | This patch fixes a potential NULL pointer dereference arising on non-present/non-initialized xHCI controllers and adds some error handling to xHCI code Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
generated by cgit v1.1 at 2024-12-30 17:53:39 +0000