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* cfi_flash: Use flash_read32() in sector_erased()Stefan Roese2010-12-17-3/+3
| | | | | | | | | | The function sector_erased() is modified to not use pointer access, but to use the correct accessor functions. This fixes a problem on the t3corp board with the Xilinx DS617 flash chips. Here a board specific accessor function is needed to read from flash in 32bit mode. This patch enables such an operation mode. Signed-off-by: Stefan Roese <sr@denx.de>
* cfi_flash: Fix problems with status/id read modeStefan Roese2010-12-17-0/+12
| | | | | | | | | This patch adds some calls to set the flash chip in the read-status- register- or read-id-mode before the corresponding register is read back. This problem was detected while porting the common CFI driver to support the Xilinx DS617 flash chips. Signed-off-by: Stefan Roese <sr@denx.de>
* Serial: Add UART support for Marvell ARMADA 100 SoCs.Prafulla Wadaskar2010-12-16-2/+3
| | | | | | | | ARMADA 100 SoCs has NS16550 compatible UART peripheral This patch enables the same for ARMADA100 platforms Signed-off-by: Mahavir Jain <mjain@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macroPrafulla Wadaskar2010-12-16-2/+6
| | | | | | | | | | On some processors this ier register configuration is different for ex. Marvell Armada100 This patch introduce CONFIG_SYS_NS16550_IER macro support to unconditionally initialize this register. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* gpio: Add Multi-Function-Pin configuration driver for Marvell SoCsPrafulla Wadaskar2010-12-16-0/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the Marvell SoCs has Multi Function Pin (MFP) configuration registers For ex. ARMADA100. These registers are programmed to expose the specific functionality associated with respective SoC Pins This driver provides configuration APIs, using them, configuration need to be done in board specific code for ex- following code configures MFPs 107 and 108 for UART_TX/RX functionality int board_early_init_f(void) { u32 mfp_cfg[] = { /* Console on UART1 */ MFP107_UART1_RXD, MFP108_UART1_TXD, MFP_EOC /*End of configureation*/ }; /* configure MFP's */ mfp_config(mfp_cfg); return 0; } Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* Merge branch 'master' of ../master into nextWolfgang Denk2010-12-16-27/+536
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| * fsl_esdhc: Set the eSHDC DMACTL[SNOOP] bit after resetting the controllerP.V.Suresh2010-12-13-4/+4
| | | | | | | | | | | | | | | | | | eSDHC host controller reset results in clearing of snoop bit also. This patch sets the SNOOP bit after the completion of host controller reset. Without this patch mmc reads are not consistent. Signed-off-by: P.V.Suresh <pala@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_upm: Add MxMR/MDR synchronizationJohn Schmoller2010-12-13-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Freescale reference manuals (eg section "13.4.4.2 Programming the UPMs" of the P4080 Reference Manual): "Since the result of any update to the MxMR/MDR register must be in effect before the dummy read or write to the UPM region, a write to MxMR/MDR should be followed immediately by a read of MxMR/MDR." The UPM on a custom P4080-based board did not work without performing a read of MxMR/MDR after a write. Signed-off-by: John Schmoller <jschmoller@xes-inc.com> Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * tsec: Revert to setting TBICR_ANEG_ENABLE by default for SGMIIKumar Gala2010-12-13-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following commit: commit 46e91674fb4b6d06c6a4984c0b5ac7d9a16923f4 Author: Peter Tyser <ptyser@xes-inc.com> Date: Tue Nov 3 17:52:07 2009 -0600 tsec: Force TBI PHY to 1000Mbps full duplex in SGMII mode Removed setting Auto-Neg by default, however this is believed to be proper default configuration for initialization of the TBI interface. Instead we explicitly set CONFIG_TSEC_TBICR_SETTINGS for the XPedite5370 & XPedite5500 boards that use a Broadcomm PHY which require Auto-Neg to be disabled to function properly. This addresses a breakage on the P2020 DS & MPC8572 DS boards when used with an SGMII riser card. We also remove setting CONFIG_TSEC_TBICR_SETTINGS on the P1_P2_RDB family of boards as now the default setting is sufficient for them. Additionally, we clean up the code a bit to remove an unnecessary second define. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Peter Tyser <ptyser@xes-inc.com>
| * Merge branch 'master' of git://git.denx.de/u-boot-imxWolfgang Denk2010-12-09-15/+2
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| | * imx: Get fec mac address from fuseLiu Hui-R643432010-11-21-15/+2
| | | | | | | | | | | | | | | | | | | | | The patch is to support getting FEC MAC address from fuse bank. Signed-off-by: Jason Liu <r64343@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de>
| * | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-12-08-0/+1
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| | * | AT91: gen_atmel_mci.c: fix bug when Slot B is usedReinhard Meyer2010-12-07-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
| * | | fix s3c2410_nand timing default valuesDavid Müller (ELSOFT AG)2010-12-06-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The attached patch fixes wrong timing default values and adds the possibility to specify board specific timing value in the board config file. Signed-off-by: David Mueller <d.mueller@elsoft.ch>
| * | | video: move fsl_diu_fb driver to drivers/videoAnatolij Gustschin2010-12-01-0/+514
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Since the driver is used not only on Freescale boards, we move it to a common place for video drivers as suggested by Wolfgang. The patch also cleans up the top level Makefile. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | | OMAP3: SPI driverDirk Behme2010-12-11-0/+470
| | | | | | | | | | | | | | | | | | CC: Ruslan N. Araslanov <byaaka@yandex.ru> Signed-off-by: Ruslan Araslanov <ruslan.araslanov@vitecmm.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | | ARMV7: OMAP4: twl6030 add battery charging supportBalaji T K2010-12-11-2/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add battery charging support twl6030 driver. Add support for battery voltage and current measurements. Add command to get battery status and start/stop battery charging from USB. Signed-off-by: Balaji T K <balajitk@ti.com> Tested-by: Steve Sakoman <steve.sakoman@linaro.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | | Merge branch 'next' of git://git.denx.de/u-boot-arm into nextWolfgang Denk2010-11-30-1/+40
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| * | | da850: Add RMII support for EMACSudhakar Rajashekhara2010-11-30-1/+40
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is a port of the work by Sudhakar Rajeshekhara in commit ab3effbcad8851cc65dc5241a01c064d2030a3b2 of git://arago-project.org/git/people/sandeep/u-boot-davinci.git. The da850 UI board has on it an RMII PHY which can be used if the MDC line to the MII PHY on the baseboard is disabled and the RMII PHY is enabled by configuring the values of some GPIO pins on the IO expander of the UI board. This patch implements disabling that line via GPIO2[6], configuring the UI board's IO expander and setting only the pinmux settings that are needed for RMII operation. Tested on da850evm by adding a define for CONFIG_DRIVER_TI_EMAC_USE_RMII. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca> CC: Sandeep Paulraj <s-paulraj@ti.com> CC: Ben Warren <biggerbadderben@gmail.com> CC: Mike Frysinger <vapier@gentoo.org> CC: Sughosh Ganu <urwithsughosh@gmail.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | | pl01x: use C structs and readl/writelRabin Vincent2010-11-30-39/+52
| | | | | | | | | | | | | | | | | | | | | | | | Use C structs for registers, and use readl/writel instead of custom accessors. Acked-by: Michael Brandt <michael.brandt@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
* | | add Xilinx_abort_fn to Xilinx_Spartan3_Slave_Serial_fnsWolfgang Wegner2010-11-30-0/+6
|/ / | | | | | | | | | | | | | | Currently the hardware was left in an undefined state in case Spartan3 serial load failed. This patch adds Xilinx_abort_fn to give the board a possibility to clean up in this case. Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
* | cfi_flash: fix bug introduced while recent change to flash_get_size()Anatolij Gustschin2010-11-28-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit ec50a8e389863ac35bfd9d9a2e8b30187318e59e "cfi_flash: handle 'chip size exceeds address window' situation" added 3rd argument to flash_get_size() but didn't fix all the function calls from the board specific code. Many boards have their own flash_get_size() definitions in the board code and use them there, but some boards (e.g. tqm834x, tqm85xx, pdm360ng) use flash_get_size() from the cfi_flash.c driver. The bug shows up if the value of the "max_size" argument (which is not defined when calling the function with two arguments) happens to be less than "info->size". In this case on the affected boards we end up with a bank of reduced size and in the worst case might even be not able to update U-Boot or to boot the kernel from flash: => fli Bank # 1: CFI conformant FLASH (32 x 16) Size: 0 kB in 1 Sectors AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E Erase timeout: 4096 ms, write timeout: 1 ms Buffer write timeout: 3 ms, buffer size: 64 bytes Sector Start Addresses: F0000000 RO Bank # 2: CFI conformant FLASH (32 x 16) Size: 128 MB in 512 Sectors AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E Erase timeout: 4096 ms, write timeout: 1 ms Buffer write timeout: 3 ms, buffer size: 64 bytes Sector Start Addresses: F8000000 F8040000 F8080000 F80C0000 F8100000 F8140000 F8180000 F81C0000 F8200000 F8240000 ... E.g., updating U-Boot is not possible now: => protect off ${u-boot_addr} +${u-boot_size} Error: end address (0xf007ffff) not in flash! Bad address format => era ${u-boot_addr} +${u-boot_size} Error: end address (0xf007ffff) not in flash! Bad address format This patch removes the 3rd argument of flash_get_size() again and sets "max_size" in the function itself instead of passing it as a function argument. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | 74xx_7xx: Cleanup for partial linking and --gc-sectionsWolfgang Denk2010-11-27-1/+2
| | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* | 824x: Cleanup for partial linking and --gc-sectionsWolfgang Denk2010-11-27-3/+7
| | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* | ppc4xx/NAND: Reduce size of NAND SPL imageStefan Roese2010-11-27-2/+2
| | | | | | | | | | | | | | | | | | | | This is needed for the canyonlands_nand build target. Without it the resulting image won't fit into 4k. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Acked-by: Stefan Roese <sr@denx.de>
* | e1000: fix compile warningWolfgang Denk2010-11-26-1/+2
| | | | | | | | | | | | | | | | | | Get rid of compiler warning: e1000.c: In function 'e1000_transmit': e1000.c:5028: warning: passing argument 1 of 'virt_to_phys' discards qualifiers from pointer target type Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbWolfgang Denk2010-11-26-2/+5
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| * | usb: Remove usb_dev_init() from ehci-ppc4xx.cStefan Roese2010-11-26-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Calling usb_dev_init() from within the EHCI host driver is wrong. The EHCI host driver should have no dependency/interconnection to the USB device driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Remy Bohmer <linux@bohmer.net>
| * | usb: Clear CMD_RUN while issuing CMD_RESET in ehci_reset()Stefan Roese2010-11-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a problem noticed on lwmon5 (PPC440EPx) using the common EHCI driver, when "usb reset" is issued multiple times. Upon the 2nd (and further) "usb reset" command, the command fails with the following messages: => usb reset (Re)start USB... USB: Register 1111 NbrPorts 1 USB EHCI 1.00 scanning bus for devices... 5 USB Device(s) found scanning bus for storage devices... 2 Storage Device(s) found => usb reset (Re)start USB... USB: EHCI fail to reset Error, couldn't init Lowlevel part This patch fixes this problem. Now "usb reset" can be called multiple times. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Remy Bohmer <linux@bohmer.net>
| * | usb: Add WATCHDOG_RESET call to polling loopStefan Roese2010-11-26-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This watchdog reset call is needed here, otherwise the lwmon5 board (PPC440EPx based) will reset upon the "usb reset" command. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Remy Bohmer <linux@bohmer.net>
| * | usb: fix for USB_ST_STALLED status reporting in ehci_submit_async()Anatolij Gustschin2010-11-26-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Checking the status field of the qTD token in the current code do not take into acount cases where endpoint stall (halted) bit is set together with XactErr status bit. As a result clearing stall on an endpoint won't be done if this status bit was also set. Check for halted bit and report USB_ST_STALLED status if the host controller also indicates endpoit stall condition. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-11-26-25/+82
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| * | mmc: omap: timeout counter fixNishanth Menon2010-11-19-25/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having a loop with a counter is no timing guarentee for timing accuracy or compiler optimizations. For e.g. the same loop counter which runs when the MPU is running at 600MHz will timeout in around half the time when running at 1GHz. or the example where GCC 4.5 compiles with different optimization compared to GCC 4.4. use timer to keep track of time elapse and we use an emperical number - 1sec for a worst case timeout. This should never happen, and is adequate imaginary condition for us to fail with timeout. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2010-11-19-70/+94
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| * | | GRETH: removed space in network driver device name.Daniel Hellstrom2010-11-18-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | | GRETH: fixed 2 decriptor table typosDaniel Hellstrom2010-11-18-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | | GRETH: Added extra RESET, this is needed if GRETH was stopped during an ↵Daniel Hellstrom2010-11-18-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | ethernet frame reception. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | | GRETH: Added autodetection of PHY address, or let BSP hardcode it.Daniel Hellstrom2010-11-18-23/+55
| | | | | | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | | GRETH: made debug printouts use common debug() macro.Daniel Hellstrom2010-11-18-41/+25
| | | | | | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | | GRETH: removed unneccesary register write and one clean up.Daniel Hellstrom2010-11-18-3/+1
| |/ / | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
* | | Exclude drivers/qe/fdt.c without CONFIG_QESebastien Carlier2010-11-18-3/+1
|/ / | | | | | | | | | | | | | | | | | | | | Previously with archive libraries fdt.o was compiled and included in qe.a and then discarded by the linker. With partial linking this results in unresolved symbols, which this commit fixes. This commit also cleans up a now-useless conditional in fdt.c. Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com> Tested-by: Wolfgang Denk <wd@denx.de>
* | net: e1000: typo using wrong argument to sizeofMatthew McClintock2010-11-17-1/+1
| | | | | | | | | | | | Typo from 4b29bdb0ed08412d225a8be94f61fc6c37a59dd5 Signed-off-by: Matthew McClintock <msm@freescale.com>
* | Switch from archive libraries to partial linkingSebastien Carlier2010-11-17-62/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, weak symbols were not overridden by non-weak symbols found in archive libraries when linking with recent versions of binutils. As stated in the System V ABI, "the link editor does not extract archive members to resolve undefined weak symbols". This commit changes all Makefiles to use partial linking (ld -r) instead of creating library archives, which forces all symbols to participate in linking, allowing non-weak symbols to override weak symbols as intended. This approach is also used by Linux, from which the gmake function cmd_link_o_target (defined in config.mk and used in all Makefiles) is inspired. The name of each former library archive is preserved except for extensions which change from ".a" to ".o". This commit updates references accordingly where needed, in particular in some linker scripts. This commit reveals board configurations that exclude some features but include source files that depend these disabled features in the build, resulting in undefined symbols. Known such cases include: - disabling CMD_NET but not CMD_NFS; - enabling CONFIG_OF_LIBFDT but not CONFIG_QE. Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-11-17-95/+53
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| * mmc: Add multi-block read support to the generic mmc driverAlagu Sankar2010-11-04-71/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds multi-block read support for the generic MMC driver. Large reads are broken into chunks of 65535 blocks to ensure that the code works with controllers having a 16 bit block counter. This patch results in a significant performance improvement. Time to read a 45 MB file went from 36 seconds to 9 seconds on Overo Signed-off-by: Steve Sakoman <steve.sakoman@linaro.org> Tested-by: Steve Sakoman <steve.sakoman@linaro.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * mmc: Clean up generic mmc driver multi-block write functionsSteve Sakoman2010-11-04-24/+14
| | | | | | | | | | | | | | | | | | | | | | The current mmc write implementation is type ulong, but returns int values. Some of the printf's are terminated with /n/r, one has none. This patch fixes these issues and also removes some unnecessary local variables. Signed-off-by: Steve Sakoman <steve.sakoman@linaro.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | pci: Use intelligent indentation for CONFIG_PCI_SCAN_SHOWPeter Tyser2010-11-14-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_PCI_SCAN_SHOW is defined U-Boot prints out PCI devices as they are found during bootup, eg: PCIE1: connected as Root Complex 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 03:00.0 - 10b5:8112 - Bridge device 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 07:00.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:01.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:02.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d This information is useful, but its difficult to determine the PCI bus topology. To things clearer, we can use indention to make it more obvious how the PCI bus is organized. For the example above, the updated output with this change is: PCIE1: connected as Root Complex 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 03:00.0 - 10b5:8112 - Bridge device 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 07:00.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:01.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:02.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d In the examples above, an MPC8640 is connected to a PEX8518 PCIe switch (01:00 and 02:0x), which is connected to another PEX8518 PCIe switch (06:00 and 07:0x), which then connects to a MPC8572 processor (08:00). Also, the MPC8640's PEX8518 PCIe switch is connected to a PCI ethernet card (04:01) via a PEX8112 PCIe-to-PCI bridge (03:00). Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | pci: Fix ordering of devices when CONFIG_PCI_SCAN_SHOWPeter Tyser2010-11-14-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the printing of PCI device information to before the PCI device is configured. This prevents the case where recursive scanning results in the deepest devices being printed first. This change also makes PCI lockups during enumeration easier to diagnose since the device that is being configured is printed out prior to configuration. Previously, it was not possible to determine which device caused the PCI lockup. Original example: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b Updated example: PCIE1: connected as Root Complex 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 03:00.0 - 10b5:8112 - Bridge device 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 07:00.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:01.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:02.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOWPeter Tyser2010-11-14-28/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | fsl_pci_init: Quiet scanning printf()Peter Tyser2010-11-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "Scanning PCI bus X" message doesn't provide any real useful information, so remove it. Original output: PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> CC: galak@kernel.crashing.org
generated by cgit v1.1 at 2024-12-24 10:08:35 +0000