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* usb: dwc3: Makefile: Don't build gadget code if USB_GADGET is disabledRoger Quadros2016-05-27-1/+1
| | | | | | | It is pointless to build gadget driver if USB_GADGET is disabled. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Marek Vasut <marex@denx.de>
* arm: add initial support for Amlogic Meson and ODROID-C2Beniamino Galvani2016-05-27-0/+178
| | | | | | | | | | | | This adds platform code for the Amlogic Meson GXBaby (S905) SoC and a board definition for ODROID-C2. This initial submission only supports UART and Ethernet (through the existing Designware driver). DTS files are the ones submitted to Linux arm-soc for 4.7 [1]. [1] https://patchwork.ozlabs.org/patch/603583/ Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* net: designware: fix descriptor layout and warnings on 64-bit archsBeniamino Galvani2016-05-27-29/+34
| | | | | | | | | | | | | All members of the DMA descriptor must be 32-bit, even on 64-bit architectures: change the type to u32 to ensure this. Also, fix other warnings. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Use phys_addr_t not unsigned long long to test that we're within DMA'able memory] Signed-off-by: Tom Rini <trini@konsulko.com>
* dm: gpio: pca953x: Support PCA953X with 40 GPIOsmario.six@gdsys.cc2016-05-27-3/+6
| | | | | | | | | | | A DM driver for PCA953x was recently introduced by Peng Fan, which lacked support for the 40 GPIO versions. This patch adds support for these chips. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-05-25-2/+31
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| * dm: ns16550: Don't map_physmem for I/O portsPaul Burton2016-05-26-2/+8
| | | | | | | | | | | | | | | | | | | | | | If the UART is to be accessed using I/O port accessors (inb & outb) then using map_physmem doesn't make sense, since it operates in a different memory space. Remove the call to map_physmem when CONFIG_SYS_NS16550_PORT_MAPPED is defined, allowing I/O port addresses to not be mangled by the incorrect mapping. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * fdt: Support for ISA bussesPaul Burton2016-05-25-0/+23
| | | | | | | | | | | | | | | | | | | | Support ISA busses in much the same way as Linux does. This allows for ISA bus addresses to be translated, and only if CONFIG_OF_ISA_BUS is selected in order to avoid including the code in builds which won't need it. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-05-25-46/+321
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| * | sunxi: power: add AXP809 supportChen-Yu Tsai2016-05-25-26/+285
| | | | | | | | | | | | | | | | | | | | | | | | The A80 uses the AXP809 as its primary PMIC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Implement poweroff support for axp818 pmicChen-Yu Tsai2016-05-25-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Adds poweroff support for axp818 pmic. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: power: axp818: Add support for switch SWChen-Yu Tsai2016-05-25-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | The AXP818 has a switchable output, SW. This is commonly used for controlling power to the LCD backlight. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | power: axp818: Fix typo for fldo2 Kconfig descriptionChen-Yu Tsai2016-05-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Description said eldo2 instead of fldo2, a copy-paste error. Fixes: 38491d9c6515 ("power: axp818: Add support for FLDOs") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | power: axp221: Remove switch case to simplify axp_set_eldoChen-Yu Tsai2016-05-25-20/+7
| |/ | | | | | | | | | | | | | | | | | | The ELDO enable bits and registers are contiguous for axp221. Instead of a switch case testing against the index, just use the index to shift the bit or register offset. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-05-25-0/+4
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| * | clk: uniphier: add Media I/O clock driver support for PH1-LD11Masahiro Yamada2016-05-26-0/+4
| |/ | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2016-05-25-1/+1
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| * powerpc:t4240: MAC9 and MAC10 should not be identified as 1G interface in ↵Ying Zhang2016-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | some case When using rcw protocols to support 10G on MAC9 and MAC10, these MACs should not be identified as 1G interface, otherwise, one MAC will be listed as two Ethernet ports. For example, MAC9 will be listed as FM1@TGEC1 and FM1@DTSEC9. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-05-24-156/+381
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| * | driver/ddr/fsl: Add workaround for erratum A-010165Shengzhou Liu2016-05-18-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | During DDR-2133 operation, the transmit data eye margins determined during the memory controller initialization may be sub-optimal, set DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | crypto/fsl: add support for multiple SEC engines initializationAlex Porosanu2016-05-18-115/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | For SoCs that contain multiple SEC engines, each of them needs to be initialized (by means of initializing among others the random number generator). Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | sf: Disable 4-KB erase command for SPANSION S25FS-S familyYuan Yao2016-05-18-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The S25FS-S family physical sectors may be configured as a hybrid combination of eight 4-kB parameter sectors at the top or bottom of the address space with all but one of the remaining sectors being uniform size. The default status of the flash is in this hybrid architecture. The parameter sectors and the uniform sectors have different erase commands. This patch disable the hybrid sector architecture then the flash will has uniform sector size and uniform erase command. This configuration is temporary, the flash will revert to hybrid architecture after power on reset. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | spi: fsl_qspi: Enable Spansion S25FS-S family flashesYuan Yao2016-05-18-6/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The flash type of LS2085AQDS QSPI is S25FS256S. It has special write any device register command and read any device register command. This patch enable support for those commands. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | spi: fsl_qspi: Assign AMBA mem according CS num in dtsYuan Yao2016-05-18-12/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QSPI controller automatic enable the chipselect signal according the dest AMBA memory address. Now we distribute the AMBA memory zone averagely to every chipselect slave device according chipselect numbers got from dts node. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | spi: fsl_qspi: Fix issues on arm64Yuan Yao2016-05-18-19/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The address value and size value get from dts "reg" property have type of u64 on arm64. If we assign those values to "u32" variables, driver can't work correctly. Converting the type of those variables to fdt_xxx_t. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | driver/ddr/fsl: Add workaround for erratum A-009801Shengzhou Liu2016-05-17-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | drivers/ddr/fsl: update workaround for erratum A-008511Shengzhou Liu2016-05-17-3/+7
| |/ | | | | | | | | | | | | | | Per the latest erratum document, update step 4 and step 8, only DEBUG_29[21] is changed, all other bits should not be changed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-05-24-530/+1172
|\ \ | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: drivers/net/zynq_gem.c
| * | net: phy: dp83867: Add SGMII helper for configurationDan Murphy2016-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code assumed that if the interface is not RGMII configured then it must be SGMII configured. This device has the ability to support most of the MII interfaces. Therefore add the helper for SGMII and only configure the device if the interface is configured for SGMII. Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: Move is_rgmii helper to phy.hDan Murphy2016-05-24-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the phy_interface_is_rgmii to the phy.h file for all phy's to be able to use the API. This now aligns with the Linux kernel based on commit e463d88c36d42211aa72ed76d32fb8bf37820ef1 Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: ti: Allow the driver to be more configurableDan Murphy2016-05-24-10/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all devices use the same internal delay or fifo depth. Add the ability to set the internal delay for rx or tx and the fifo depth via the devicetree. If the value is not set in the devicetree then set the delay to the default. If devicetree is not used then use the default defines within the driver. Signed-off-by: Dan Murphy <dmurphy@ti.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: zynq_gem: Add the passing of the phy-handle nodeDan Murphy2016-05-24-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the ability to pass the phy-handle node offset to the phy driver. This allows the phy driver to access the DT subnode's data and parse accordingly. Signed-off-by: Dan Murphy <dmurphy@ti.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers: net: cpsw: Add reading of DT phy-handle nodeDan Murphy2016-05-24-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the ability to read the phy-handle node of the cpsw slave. Upon reading this handle the phy-id can be stored based on the reg node in the DT. The phy-handle also needs to be stored and passed to the phy to access any phy data that is available. Signed-off-by: Dan Murphy <dmurphy@ti.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers: net: cpsw: add support for reading mac address from efuseMugunthan V N2016-05-24-17/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Different TI platforms has to read with different combination to get the mac address from efuse. So add support to read mac address based on machine/device compatibles. The code is taken from Linux drivers/net/ethernet/ti/cpsw-common.c done by Tony Lindgren. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers: net: cpsw: fix get mdio base and gmii_sel reg from DTMugunthan V N2016-05-24-4/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since dra7x platforms address bus is define as 64 bits to support LAPE, fdtdec_get_addr() returns a invalid address for mdio based and gmii_sel register address. Fixing this by using fdtdec_get_addr_size_auto_noparent() which will derive address cell and size cell from its parent. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers: net: cpsw: fix cpsw dp parse when num slaves as 1Mugunthan V N2016-05-24-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some boards number of slaves can be 1 when only one port ethernet is pinned out. So do not break when slave_index and num slaves check fails, instead continue to parse the next child. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers: core: device: add support to check dt compatible for a device/machineMugunthan V N2016-05-24-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide an api to check whether the given device or machine is compatible with the given compat string which helps in making decisions in drivers based on device or machine compatible. Idea taken from Linux. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: Add PHY driver for mv88e61xx switchesKevin Smith2016-05-24-0/+1020
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous mv88e61xx driver was a driver for configuring the switch, but did not integrate with the PHY/networking system, so it could not be used as a PHY by U-boot. This is a complete rework to support this device as a PHY. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: Remove unused mv88e61xx switch driverKevin Smith2016-05-24-598/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No boards are using this driver. Remove in preparation for a new driver with integrated PHY support. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-05-24-73/+152
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| * | | phy: marvell: Do not reset phy after negotiationMichal Simek2016-05-24-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch "net: phy: do not read configuration register on reset" (sha1: a058052c358c3ecf5f394ff37def6a45eb26768c) was causing regression on zynq zc702 board where Marwell 88e1118 phy was resetted after negotiation was setup. Phy reset is done pretty early in phy_connect_dev() and doens't need to be called again in phy code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | phy: Wire return value from phy_config()Michal Simek2016-05-24-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | Fix zynq_gem driver to handle error from phy_config correctly. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | net: phy: Handle phy_startup() error codes properlyMichal Simek2016-05-24-56/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Propagate error code from genphy_update_link() to phy startup(). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | | phy: Return correct error code when timeout happensMichal Simek2016-05-24-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Return -ETIMEDOUT if timeout happens. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | | net: xilinx: Handle error value from phy_startup()Michal Simek2016-05-24-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Handle error returned by phy_startup() properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | | fpga: Fix typo in function commentMichal Simek2016-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Trivial patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | gpio: zynq: Add support for reading gpio pin stateMichal Simek2016-05-24-0/+22
| |/ / | | | | | | | | | | | | | | | | | | Add zynq_gpio_get_function() which return status on gpio pin. This function enables gpio status command. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-05-23-0/+393
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| * | cmd: qfw: bring ACPI generation code into qfw coreMiao Yan2016-05-23-0/+206
| | | | | | | | | | | | | | | | | | | | | | | | Loading ACPI table from QEMU's fw_cfg interface is not x86 specific (ARM64 may also make use of it). So move the code to common place. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h]Miao Yan2016-05-23-3/+3
| | | | | | | | | | | | | | | | | | | | | Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: qemu: move x86 specific operations out of qfw coreMiao Yan2016-05-23-17/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original implementation of qfw includes several x86 specific operations, like directly calling outb/inb and using some inline assembly code which prevents it being ported to other architectures. This patch adds callback functions and moves those to arch/x86/ Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-11-09 02:18:10 +0000