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| * | imx: mxc_gpio: add support for imx7d SoCAdrian Alonso2015-09-02-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | * Add mxc_gpio support for imx7d SoC * Use CONFIG_MX7 to extend mxc gpio driver support for imx7d Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
| * | power: pmic: add pfuze3000 supportAdrian Alonso2015-09-02-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | * Add pmic pfuze3000 support, implement power_pfuze3000_init to be used in power_init_board callback function. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | net: fec: do not access reserved register for i.MX6ULPeng Fan2015-09-02-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIB RAM and FIFO receive start register does not exist on i.MX6UL. Accessing these register will cause enet not work well. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Stefano Babic <sbabic@denx.de>
| * | mxs_ocotp: Shift the HBUS divider correctlyChris Smith2015-09-02-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | When the original HBUS divider value is retrieved in mxs_ocotp_scale_hclk() for the purpose or restoring it back later, the value is not shifted by the HBUS divider offset in that register. This is not a problem, since the shift is zero on all MXS hardware. Add the shift anyway, for completeness and in case FSL ever decides to re-use this driver on future designs. Signed-off-by: Chris Smith <chris@zxdesign.info> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* | pci/layerscape: Setup mmu-masters property for the PCIeVarun Sethi2015-09-01-0/+9
| | | | | | | | | | | | | | | | | | Setup mmu-masters property for the PCIe controllers. This would be used by the Linux SMMU driver, while setting up stream ID table mappings for the PCIe devices. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | arm/ls102xa:add hwconfig setting to support disable unused devicesZhuoyu Zhang2015-09-01-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | DEVDISRn registers provides a mechanism for gating clocks of IP blocks that are not used. Here we implement hwconfig option to allow users to disable unused peripherals on the board. For ex. If eSDHC/qDMA/eDMA are unused and with disabled status in dts, User can enable CONFIG_FSL_DEVICE_DISABLE and set "devdis:esdhc,qdma,edma" in hwconfig, thus ESDHC controller & eDMA/qDMA will be clock gated to save more power. Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | ls102xa: etsec: Use proper settings for BE BDsClaudiu Manoil2015-09-01-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the DMACTRL[LE] hack with recommended settings for ETSECDMAMCR to get the same end effect - obtaining big-endian buffer descriptors and frame data for eTSEC. The reset / default value for ETSECDMAMCR is preserved, excepting the BD and FR bits which are cleared to enable the BE mode in accordance with the H/W specifications. Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA" Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Tested-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | driver: misc: debug server: Update Error messagePrabhakar Kushwaha2015-09-01-5/+5
| | | | | | | | | | | | | | | | Append "debug server FW" in error message to make more informative. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | net: phy/vitesse: Add support for VSC8584 phyPrabhakar Kushwaha2015-09-01-0/+11
| | | | | | | | | | | | | | | | | | | | Add support of VSC8584 phy placed on new QSGMII/SGMII ethernet riser cards used on LS2085QDS platforms. Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | rtc:ds3232/ds3231: Add support to generate 32KHz outputPriyanka Jain2015-09-01-0/+10
|/ | | | | | | | | | | | RTC devices can generate 32KHz output if for -DS3232 device, EN32KHz bit and BB32KHz bit are set -DS3231 device, EN32KHz bit is set, BB32KHz bit is don't care Patch adds rtc_enable_32khz_output() which when called will enable 32KHz output on 32KHz pin Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-08-31-159/+187
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| * sunxi: mmc: set transfer timeout according to byte_cnt.Yousong Zhou2015-08-31-2/+4
| | | | | | | | | | | | | | | | | | | | | | Originally a timeout value of 2 seconds was used regardless of the size of data to be transfered. This prevented slow devices from working correctly while there was no much gain for faster devices, e.g. it takes 3708ms for a transfer of uImage of size 1899008 bytes. Signed-off-by: Yousong Zhou <yszhou4tech@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * mtd: nand: Make CONFIG_SYS_NAND_U_BOOT_OFFS configurable through KconfigHans de Goede2015-08-31-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make CONFIG_SYS_NAND_U_BOOT_OFFS configurable through Kconfig, just like SYS_NAND_BUSWIDTH_16BIT this is only enabled on some SoCs using depends, to avoid double defining it for SoCs which have not yet moved to Kconfig for this. Having this in Kconfig is useful because this is something which may differ from one board to the other even when using the same SoC. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Scott Wood <scottwood@freescale.com>
| * sunxi_nand_spl: clear status flags in SPL implementationBoris Brezillon2015-08-31-3/+8
| | | | | | | | | | | | | | | | | | | | | | Some status flags remain set until you explicetly clear the bit in the status register. Fix the SPL implementation to avoid false positive. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [hdegoede@redhat.com: Port from v2015.07 to v2015.10] Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi_nand_spl: Remove NAND_SUNXI_SPL_SYNDROME_PARTITIONS_ENDHans de Goede2015-08-31-10/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We only ever use syndrome mode for the partitions which contain the SPL, as that is required for the BROM to be able to read the SPL. Instead of using some arbritray limit for deciding whether or not to use syndrome, be smart and check if u-boot-dtb.bin is directly behind the SPL, if it is not then it is on its own partition and we should not use syndrome. Note the reason why we only use syndrome mode for the SPL is because it comeswith weaker randomization, introducing a risk for more bit errors, so we want to avoid it when possible. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi_nand_spl: Rename SPL_NAND_SUNXI to NAND_SUNXIHans de Goede2015-08-31-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We eventually want to add full nand support, since it makes no sense to build SPL with nand support and u-boot without, or the other way around, a single option will suffice. Renaming the Kconfig option now makes things easier when we add full nand support in the future. The "obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o" is moved to an "ifdef CONFIG_SPL_BUILD" block in the Makefile. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi_nand_spl: Add support for backup boot partitionsHans de Goede2015-08-31-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | The BROM does not care / use bad page markings, instead it deals with any bad pages in the first erase-block by simply trying to load "boot0" from the next erase-block. This commit implements the same strategy for the sunxi spl nand code, allowing it to boot from the backup boot partition when the main boot partition is bad (tested by erasing the main boot partition). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi_nand_spl: Auto detect nand configuration parametersHans de Goede2015-08-31-29/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Auto detect the nand configuration parameters, like the BROM does. This allows us to get rid of various Kconfig settings, and is necessary to support generic boards like the mk802 which have seen many production runs with different nands. The full blown u-boot/kernel nand driver uses the nand id to determine this info, for the SPL we do as the BROM does and simply try a few standard configs. Note the table only contains configs which are known to actually be used, rather then all the configs the BROM tries. This means that it may need to be updated in the future as we add support for nand on more boards. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi_nand_spl: Parametrize lowlevel read functionsHans de Goede2015-08-31-38/+48
| | | | | | | | | | | | | | | | | | | | | | | | Parametrize the lowlevel nand_read_page function, instead of directly using the CONFIG_foo settings for page-size, etc. there and add a few wrappers / helper functions for calling it. This is a preparation patch for adding auto-detecting of the nand parameters like the BROM does. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi_nand_spl: Properly config page-size in the nand ctl registerHans de Goede2015-08-31-0/+5
| | | | | | | | | | | | | | | | | | Properly config page-size in the nand ctl register, it seems that things work fine without doing this, but still lets play it safe and properly set the page-size. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi_nand_spl: Add support for sun4i and sun5i SoCsHans de Goede2015-08-31-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Other then having a few less chip-select lines the nand controller on sun4i, sun5i and sun7i is identical. Note this patch also muxes GPC7 to the NAND on sun7i where as before it was not muxed this way. GPC7 is a standard NAND pin, so it should always be muxed to the NAND when in use. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi_nand_spl: Use kernel driver algorithm for determining ecc_mode / _offHans de Goede2015-08-31-46/+12
| | | | | | | | | | | | | | | | | | Sync the code for figuring out the ecc_mode and ecc_offset with the linux kernel v4.1. Keeping this in sync seems like a good idea in general, and it fixes / adds support for ecc strengths of 56, 60 and 64 bits. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi_nand_spl: Add proper cache flusingHans de Goede2015-08-31-0/+8
| | | | | | | | | | | | | | | | | | | | We are using dma, so we should flush the cache before starting the dma, and invalidate it once the dma is done. Things are working without this by mostly luck, but lets not rely on that. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi_nand_spl: Turn off clocks when we're done with the nandHans de Goede2015-08-31-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | Turn off the nand and dma clocks when we're done with the nand, this puts the nand and dma controllers back into a clean state for when the kernel boots. Without this the kernel will not boot properly when it is built with dma-controller support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi_nand_spl: Use SYS_NAND_SELF_INIT and only do nand init when necessaryHans de Goede2015-08-31-0/+3
| | | | | | | | | | | | | | | | Use SYS_NAND_SELF_INIT and only setup the pinmux and clocks when we are actually using the nand. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi_nand_spl: Do not bother writing the spare-area reg in syndrome modeHans de Goede2015-08-31-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | In syndrome mode we set the NFC_SEQ bit in the command register, so the spare-area register is not used. Also the value currently being written is actual wrong, the ecc sits at "column + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE" not just CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE. So the current code only serves to confuse the user -> remove it. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi_nand_spl: We only need to reset the nand chip onceHans de Goede2015-08-31-10/+10
| | | | | | | | | | | | | | There is no need to reset the nand chip for every ecc-block read. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi_nand_spl: Drop unnecessary temp bufHans de Goede2015-08-31-27/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nand_spl_load_image() always gets called with either CONFIG_SYS_TEXT_BASE or spl_image.load_addr as destination, both of which are properly aligened, and have plenty of space for "overshooting" up to CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE bytes, as we read in CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE bytes chunks. This saves CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE (typically 1k) in SPL size, which is a lot on the total 24k we have. Note this changes the dma destination from SRAM to DRAM, so this patch updates the DDMA_DST_TYPE bits in the dma controller cfg0 reg accordingly. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: musb: Drop no longer accurate comment in Kconfig help textHans de Goede2015-08-31-3/+1
| | | | | | | | | | | | | | | | | | Drop the no longer accurate part of the USB_MUSB_SUNXI Kconfig help text, since the musb-host code now supports the device-model, ehci and musb in host mode can both be enabled at the same time without issues. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: axp221: Allow specifying dcdc2 voltage via KconfigHans de Goede2015-08-31-0/+9
| | | | | | | | | | | | | | | | Allow specifying the axp221 dcdc2 voltage via Kconfig, this is necessary because on some boards the 1.2V default does not work reliable. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | Merge git://git.denx.de/u-boot-dmTom Rini2015-08-31-1298/+1915
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| * | pinctrl: sandbox: add sandbox pinctrl driverMasahiro Yamada2015-08-31-0/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver actually does nothing but test pinctrl uclass, and demonstrate how things work. To try this driver, uncomment /* #define DEBUG */ in the drivers/pinctrl/pinctrl-sandbox.c, and debug messages will be displayed. DRAM: 128 MiB sandbox pinmux: group = 1 (serial_a), function = 1 (serial) Using default environment In: cros-ec-keyb Out: lcd Err: lcd Net: Net Initialization Skipped eth0: eth@10002000, eth1: eth@80000000, eth5: eth@90000000 => i2c dev 0 Setting bus to 0 sandbox pinmux: group = 0 (i2c), function = 0 (i2c) sandbox pinconf: group = 0 (i2c), param = 3, arg = 1 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | pinctrl: add pin control uclass supportMasahiro Yamada2015-08-31-0/+709
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This creates a new framework for handling of pin control devices, i.e. devices that control different aspects of package pins. This uclass handles pinmuxing and pin configuration; pinmuxing controls switching among silicon blocks that share certain physical pins, pin configuration handles electronic properties such as pin- biasing, load capacitance etc. This framework can support the same device tree bindings, but if you do not need full interface support, you can disable some features to reduce memory foot print. Typically around 1.5KB is necessary to include full-featured uclass support on ARM board (CONFIG_PINCTRL + CONFIG_PINCTRL_FULL + CONFIG_PINCTRL_GENERIC + CONFIG_PINCTRL_PINMUX), for example. We are often limited on code size for SPL. Besides, we still have many boards that do not support device tree configuration. The full pinctrl, which requires OF_CONTROL, does not make sense for those boards. So, this framework also has a Do-It-Yourself (let's say simple pinctrl) interface. With CONFIG_PINCTRL_FULL disabled, the uclass itself provides no systematic mechanism for identifying the peripheral device, applying pinctrl settings, etc. They must be done in each low-level driver. In return, you can save much memory footprint and it might be useful especially for SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | dm: core: allow device_bind() to not return a device pointerMasahiro Yamada2015-08-31-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | This is useful when we want to bind a device, but do not need the pointer to the device. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | dm: tpm: Convert LPC driver to driver modelSimon Glass2015-08-31-155/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the tpm_tis_lpc driver to use driver model and update boards which use it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Christophe Ricard<christophe-h.ricard@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | dm: tpm: Convert I2C driver to driver modelSimon Glass2015-08-31-346/+203
| | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the tpm_tis_i2c driver to use driver model and update boards which use it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Christophe Ricard<christophe-h.ricard@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | dm: tpm: sandbox: Convert TPM driver to driver modelSimon Glass2015-08-31-12/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the sandbox TPM driver to use driver model. Add it to the device tree so that it can be found on start-up. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Christophe Ricard <christophe-h.ricard@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | dm: tpm: Add a uclass for Trusted Platform ModulesSimon Glass2015-08-31-286/+434
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new uclass for TPMs which uses almost the same TIS (TPM Interface Specification) as is currently implemented. Since init() is handled by the normal driver model probe() method, we don't need to implement that. Also rename the transfer method to xfer() which is a less clumbsy name. Once all drivers and users are converted to driver model we can remove the old code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Christophe Ricard<christophe-h.ricard@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | tpm: tpm_tis_i2c: Tidy up delaysSimon Glass2015-08-31-31/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use a _US suffix for microseconds and a _MS suffic for milliseconds. Move all timeouts and delays into one place. Use mdelay() instead of udelay() where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Christophe Ricard <christophe-h.ricard@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | tpm: tpm_tis_i2c: Use a consistent tpm_tis_i2c_ prefixSimon Glass2015-08-31-55/+58
| | | | | | | | | | | | | | | | | | | | | | | | Use the same prefix on each function for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Christophe Ricard <christophe-h.ricard@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | tpm: tpm_tis_i2c: Simplify init codeSimon Glass2015-08-31-23/+10
| | | | | | | | | | | | | | | | | | | | | | | | Move all the init and uninit code into one place. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Christophe Ricard<christophe-h.ricard@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | tpm: tpm_tis_i2c: Move definitions into the header fileSimon Glass2015-08-31-335/+335
| | | | | | | | | | | | | | | | | | | | | | | | Some definitions are in the C file and some are in the header file. Move everything into the header file for consistency and to reduce clutter. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | tpm: tpm_tis_i2c: Merge struct tpm into tpm_chipSimon Glass2015-08-31-15/+10
| | | | | | | | | | | | | | | | | | | | | | | | There are too many structures storing the same sort of information. Move the fields from struct tpm into struct tpm_chip and remove the former struct. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | tpm: tpm_tis_i2c: Merge struct tpm_dev into tpm_chipSimon Glass2015-08-31-44/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | There are too many structures storing the same sort of information. Move the fields from struct tpm_dev into struct tpm_chip and remove the former struct. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | tpm: tpm_tis_i2c: Drop struct tpm_vendor_specificSimon Glass2015-08-31-60/+35
| | | | | | | | | | | | | | | | | | | | | | | | This function is misnamed since it only applies to a single driver. Merge its fields into its parent. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | tpm: tpm_tis_i2c: Drop unnecessary methodsSimon Glass2015-08-31-12/+4
| | | | | | | | | | | | | | | | | | | | | | | | The function methods in struct tpm_vendor_specific just call local functions. Change the code to use a direct call. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | tpm: Move the I2C TPM code into one fileSimon Glass2015-08-31-618/+550
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current Infineon I2C TPM driver is written in two parts, intended to support use with other I2C devices. However we don't have any users and the Atmel I2C TPM device does not use this file. We should simplify this and remove the unused abstration. As a first step, move the code into one file. Also the name tpm_private.h suggests that the header file is generic to all TPMs but it is not. Rename it indicate that it relates only to this driver Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | tpm: Convert drivers to use SPDXSimon Glass2015-08-31-29/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add an SPDX header to two drivers that don't have it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Christophe Ricard <christophe-h.ricard@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | tpm: Add Kconfig options for TPMsSimon Glass2015-08-31-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add new Kconfig options for TPMs in preparation for moving boards to use Kconfig for TPM configuration. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Christophe Ricard<christophe-h.ricard@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | tpm: Remove old pre-driver-model I2C codeSimon Glass2015-08-31-179/+7
| | | | | | | | | | | | | | | | | | | | | | | | This is not used anymore by any board so drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Christophe Ricard <christophe-h.ricard@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
generated by cgit v1.1 at 2024-12-29 03:25:03 +0000