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* atmel_nand: Add 32 bit ecc support for sama5d2 chipJosh Wu2016-02-02-1/+9
| | | | | | | | | | Also if minimum ecc requirment is bigger then what we support, then just use our maxium pmecc support. But it is not safe, so we'll output a warning about this. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* atmel_nand_ecc: update pmecc registers according to sama5d2 chipJosh Wu2016-02-02-4/+32
| | | | | | | | | | 1. add the pmecc register mapping for sama5d2. 2. add the pmecc error location register mapping for sama5d2. 3. add some new field that is different from old ip. 4. add sama5d2 pmecc ip version number. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* atmel_nand: use the definition: PMECC_OOB_RESERVED_BYTES instead magic numberJosh Wu2016-01-27-1/+1
| | | | | | | | | As atmel_nand_ecc.h is sync with v4.1 kernel, which adds the PMECC_OOB_RESERVED_BYTES. So use it in the driver. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
* atmel_nand: add '\n' in the end of error message for better displayJosh Wu2016-01-27-2/+2
| | | | | | | | Also align the open parenthesis. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* atmel_nand: use nand ecc_{strength, step}_ds instead of our own functionJosh Wu2016-01-27-37/+7
| | | | | | | | | | Since ecc_{strength,step}_ds is introduced in nand_chip structure for minimum ecc requirements. So we can use them directly and remove our own get_onfi_ecc_param function. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
* net: macb: Not all the GEM are gigabit capableGregory CLEMENT2016-01-27-2/+19
| | | | | | | | | | | | | | | | | | During the initialization of PHY the gigabit bit capable is set if the controller is a GEM. However, for sama5d2 and sama5d4, the GEM is configured to support only 10/100. Improperly setting the GBE capability leads to an unresponsive MAC controller. This patch fixes this behavior allowing using the gmac with these SoCs. Suggested-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> [fixed minor checkpatch warning] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* mmc: atmel: Properly fix clock configurationGregory CLEMENT2016-01-27-3/+12
| | | | | | | | | | | | | | | | | Timing issue occurs on eMMC not only when modifying the frequency but also for all the switch command(CMD6). According to the MMC spec waiting 8 clocks after a switch command would be the thing to do. This patch allows fixing CPU hang observed when trying to changing the bus width on a eMMC on SAMA5D4. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Marek Vasut <marex@denx.de> # on DENX MA5D4EV Acked-by: Marek Vasut <marex@denx.de> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com> # on atngw100 Acked-by: Andreas Bießmann <andreas.devel@googlemail.com> [fixed minor checkpatch warning] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-01-26-79/+158
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| * mvtwsi: Fix breakage introduced by "Fix mvtwsi not working on sun6i and ↵Hans de Goede2016-01-26-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | newer sunxi SoCs" "Fix mvtwsi not working on sun6i and newer sunxi SoCs" includes the following: @@ -189,7 +200,8 @@ static int twsi_start(struct i2c_adapter *adap, int expected_status) /* globally set TWSIEN in case it was not */ twsi_control_flags |= MVTWSI_CONTROL_TWSIEN; /* assert START */ - writel(twsi_control_flags | MVTWSI_CONTROL_START, &twsi->control); + twsi_control_flags |= MVTWSI_CONTROL_START | MVTWSI_CONTROL_CLEAR_IFLG; + writel(twsi_control_flags, &twsi->control); /* wait for controller to process START */ return twsi_wait(adap, expected_status); } The modification of twsi_control_flags done here was introduced while merging to fix a line > 80 chars, but twsi_control_flags is a global variable and should not be modified like this here, this commit fixes this, restoring mvtwsi functionality. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: power: axp818: Enable support for ALDOsChen-Yu Tsai2016-01-26-3/+47
| | | | | | | | | | | | | | | | | | | | | | | | Previously, AXP818 ALDO support was partially added to Kconfig, but never enabled in the board file, nor properly set or configured in Kconfig. The boards continue to work because the AXP818 is designed to pair with the A83T/H8, and the default voltages match the reference design's requirements. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * power: axp818: Add support for DLDO and ELDO regulatorsChen-Yu Tsai2016-01-26-6/+50
| | | | | | | | | | | | | | | | | | AXP818 provides an array of LDOs to provide power to various peripherals. None of these regulators are critical. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * power: axp: merge separate DLDO functions into 1Chen-Yu Tsai2016-01-26-68/+20
| | | | | | | | | | | | | | | | | | | | | | Instead of one function for each DLDO regulator, make 1 function that takes an extra "index". Since the control bits for the DLDO regulators are contiguous, this makes the function very simple. This removes a lot of duplicate code. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Implement poweroff support for axp221 pmicHans de Goede2016-01-26-0/+13
| | | | | | | | | | | | | | Adds poweroff support for axp221 pmic. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Implement poweroff support for axp209 pmicMichael van Slingerland2016-01-26-0/+13
| | | | | | | | | | | | | | | | Adds poweroff support for axp209 pmic. Signed-off-by: Michael van Slingerland <michael@deviousops.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Implement poweroff support for axp152 pmicHans de Goede2016-01-26-0/+13
| | | | | | | | | | | | | | Adds poweroff support for axp152 pmic. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2016-01-26-1/+549
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| * | video: add CONFIG_I2C_EDID and disable CONFIG_DISPLAY by defaultAnatolij Gustschin2016-01-26-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling CONFIG_DISPLAY breaks building for some architectures (microblaze-generic), so we disable CONFIG_DISPLAY in Kconfig by default and enable this option in defconfigs. CONFIG_DISPLAY depends on CONFIG_I2C_EDID, so add and enable it in defconfigs, too. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reported-by: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * | video: Add support for Armada XP LCD controllerStefan Roese2016-01-23-0/+540
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the LCD controller of the Marvell Armada XP SoC. An AXP based custom board port will be added later, to use this driver to display a splash screen via the bmp command later. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> [agust: rebased] Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-01-25-100/+3291
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| * | usb: add clock support for generic EHCIMasahiro Yamada2016-01-25-0/+14
| | | | | | | | | | | | | | | | | | | | | This driver is designed in a generic manner, so clocks should be handled genericly as well. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | usb: eth: add Realtek RTL8152B/RTL8153 DRIVERTed Chen2016-01-23-0/+3075
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds driver support for the Realtek RTL8152B/RTL8153 USB network adapters. Signed-off-by: Ted Chen <tedchen at realtek.com> [swarren, fixed a few compiler warnings] [swarren, with permission, converted license header to SPDX] [swarren, removed printf() spew during probe()] Signed-off-by: Stephen Warren <swarren at nvidia.com>
| * | usb: dwc2: Do not mix data toggle for IN and OUT endpoints, check boundsStefan Brüns2016-01-23-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB protocol allows for 16 IN and 16 OUT endpoints (USB 2.0 Spec, 8.3.2.2 Endpoint Field). A function may have an EP 1 for both IN and OUT, so these two should be kept separate. As EPs are either BULK or INTERRUPT (or ISO), it is fine to have one array per direction for all transfer types (also see e236519b7365ef75c5da6a5623f0b03d9c00cfae). USB device address is 7 bits, so a bus may have more than 16 devices. Check the device number, as the DWC2 driver only supports BULK/ISO for the first 16 devices. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
| * | usb: dwc2: Add SPLIT INTERRUPT transaction supportStefan Brüns2016-01-23-5/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CSPLITs for INTERRUPT transactions have to be scheduled in each microframe following the SSPLIT. INTERRUPT transfers are executed in the next even/ odd microframe depending on the HCCHAR_ODDFRM flag. As there are no handshakes for INTERRUPT SSPLITs the SSPLIT may have failed (transport error) without the error being detected by the host driver. If the last CSPLIT is not received within 4 microframes after the SSPLIT there was a transaction error and the complete transaction has to be restarted. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
| * | usb: dwc2: Implement SPLIT transaction supportStefan Brüns2016-01-23-15/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | In contrast to non-SPLIT transfers each transaction has to be submitted as an individual chunk. The transaction state machine proceeds from SSPLIT to CSPLIT if the ACK flag is set. CSPLIT has to be repeated while NYET is set. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
| * | usb: dwc2: add helper function for setting SPLIT HC registersStefan Brüns2016-01-23-1/+14
| | | | | | | | | | | | | | | | | | | | | The split register setting is used for both SSPLIT and CSPLIT transactions, the bit for CSPLIT has to be set seperately. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
| * | usb: dwc2: split transfer core from outer loopStefan Brüns2016-01-23-48/+64
| | | | | | | | | | | | | | | | | | | | | | | | Split the movement of data between CPU and Host Controller from the status handling and tracking of transfer progress. This will also simplify adding of SPLIT transaction support. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
| * | usb: dwc2: Simplify wait_for_chhltd(), remove ignore_ackStefan Brüns2016-01-23-23/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A transfer is completed if the XFERCOMP flag is set, irrespective of the ACK flag. BULK OUT transfers to some HS devices complete without having the ACK flag set, which signal the devices has responded with an NYET to the transfer (PING protocol). The new behaviour matches the Linux kernel minus any PING protocol. Also see 5966defabdcc (usb: dwc2: fix bulk transfers) Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
| * | usb: dwc2: Fix out-of-bounds access, fix chunk sizeStefan Brüns2016-01-23-15/+15
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix two errors in transfer len calculation, move loop invariant code out of loop. If xfer_len is equal to CONFIG_DWC2_MAX_TRANSFER_SIZE (or slightly smaller), the xfer_len will be to large, e.g.: xfer_len = MAX_TRANSFER_SIZE = 65535 max packet size = 512 => num_packets = 128 => IN xfer_len = 65536 For OUT transactions larger than (65536 - mps) bytes, the xfer_len determination is quite awkward, it is only correct due to: - max_packet_size for control/bulk/interrupt is required to be power-of-two. - (CONFIG_DWC2_MAX_TRANSFER_SIZE + 1) % max-packet-size is zero for all allowed (2^3 ... 2^9) packet sizes As the max xfer len is loop invariant, it can be moved out of the loop. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-imxTom Rini2016-01-25-3/+3
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| * | imx: nand: update GPMI NAND driver to support MX7Peng Fan2016-01-24-2/+2
| | | | | | | | | | | | | | | | | | | | | Update GPMI NAND driver and BCH head file to support i.MX7 Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: apbh_dma: Update APBH-DMA for MX7DPeng Fan2016-01-24-1/+1
| |/ | | | | | | | | | | | | Update APBH-DMA driver and head files to support i.MX7D Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | ns16550: zap the rockchip serial compatible stringThomas Chou2016-01-25-1/+5
| | | | | | | | | | | | | | | | Zap the rockchip serial compatible string, because rockchip serial has "snps,dw-apb-uart" compatible string in the dts. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
* | net: eepro100: Fix build warningsBin Meng2016-01-25-4/+4
| | | | | | | | | | | | | | | | | | | | | | When building katmai, it reports quite a lot warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Fix this by casting the dev->iobase with u_long. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | bug.h: move BUILD_BUG_* defines to include/linux/bug.hMasahiro Yamada2016-01-25-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUILD_BUG_* macros have been defined in several headers. It would be nice to collect them in include/linux/bug.h like Linux. This commit is cherry-picking useful macros from include/linux/bug.h of Linux 4.4. I did not import BUILD_BUG_ON_MSG() because it would not work if it is used with include/common.h in U-Boot. I'd like to postpone it until the root cause (the "error()" macro in include/common.h causes the name conflict with "__attribute__((error()))") is fixed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | net: zynq_gem: Use shared wait_for_bitMateusz Kulikowski2016-01-25-33/+2
| | | | | | | | | | Use existing library function to poll bit(s). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
* | usb: ehci-mx6: Use shared wait_for_bitMateusz Kulikowski2016-01-25-28/+4
| | | | | | | | | | | | Use existing library function to poll bit(s). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
* | usb: ohci-lpc32xx: Use shared wait_for_bitMateusz Kulikowski2016-01-25-27/+7
| | | | | | | | | | | | | | Use existing library function to poll bit(s). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* | usb: dwc2: Use shared wait_for_bitMateusz Kulikowski2016-01-25-28/+13
| | | | | | | | | | | | Use existing library function to poll bit(s). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
* | serial: Remove serial_putc_raw_devTom Rini2016-01-25-11/+0
| | | | | | | | | | | | | | | | | | clang-3.8 reports that serial_putc_raw_dev in serial_ns16550.c is unused. Further investigation shows that we have 3 places that implement this function and no callers, remove. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Use the I2C driver to perform SMbus initSimon Glass2016-01-24-0/+24
| | | | | | | | | | | | | | | | Move the init code into the I2C driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: i2c: Add a stub driver for Intel I2C/SMbusSimon Glass2016-01-24-0/+61
| | | | | | | | | | | | | | | | | | | | | | This is used on most Intel platforms. We don't have a driver for it yet, but add a stub to handle the init. For now this targets ivybridge so we may want to add a device tree binding and generalise it when other platforms are supported. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | ahci: Add a disk-controller uclassSimon Glass2016-01-24-0/+24
| | | | | | | | | | | | | | | | | | Add a uclass ID for a disk controller. This can be used by AHCI/SATA or other controller types. There are no operations and no interface so far, but it is possible to probe a SATA device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: pci: Convert bios_emu to use the driver model PCI APISimon Glass2016-01-24-7/+147
| | | | | | | | | | | | | | | | At present this BIOS emulator uses a bus/device/function number. Change it to use a device if CONFIG_DM_PCI is enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: syscon: Allow finding devices by driver dataSimon Glass2016-01-24-12/+19
| | | | | | | | | | | | | | | | We have a way to find a regmap by its syscon driver data value. Add the same for syscon itself. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: usb: Add a compatible string for PCI EHCI controllerSimon Glass2016-01-24-0/+6
| | | | | | | | | | | | | | | | | | Add a compatible string to allow this to be specified in the device tree if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: core: Display the error number when driver binding failsSimon Glass2016-01-24-1/+2
| | | | | | | | | | | | | | | | This is often -96 (-EPFNOSUPPORT) which indicates that the uclass is not compiled in. Display the error number to make this easier to spot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: x86: spi: Convert ICH SPI driver to driver model PCI APISimon Glass2016-01-24-116/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* | spi: ich: Separate out the read/write trace from normal debuggingSimon Glass2016-01-24-9/+15
| | | | | | | | | | | | | | | | | | The trace is seldom useful for basic debugging. Allow it to be enabled separately so that it is easier to see the more important init and error debug messages. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: x86: Add a driver for Intel PCH9Simon Glass2016-01-24-0/+44
| | | | | | | | | | | | | | | | | | At some point we may need to distinguish between different types of PCHs, but for existing supported platforms we only need to worry about version 7 and version 9 bridges. Add a driver for the PCH9. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: x86: Add a driver for Intel PCH7Simon Glass2016-01-24-0/+62
| | | | | | | | | | | | | | | | | | At some point we may need to distinguish between different types of PCHs, but for existing supported platforms we only need to worry about version 7 and version 9 bridges. Add a driver for the PCH7. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-10-22 21:31:34 +0000