summaryrefslogtreecommitdiff
path: root/drivers
Commit message (Collapse)AuthorAgeLines
* i2c: Select SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED for SPEArStefan Roese2016-05-17-0/+10
| | | | | | | | | The DW I2C controller in the SPEAr SoCs doesn't support the enable status register check. This patch selects SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED for these boards. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de>
* i2c: Add entry for Designware I2C driver in KconfigStefan Roese2016-05-17-0/+8
| | | | | | | | This patch adds an entry for the Designware I2C driver in Kconfig. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: fsl_i2c: Enable DM for FSL I2Cmario.six@gdsys.cc2016-05-17-0/+110
| | | | Signed-off-by: Mario Six <mario.six@gdsys.cc>
* dm: fsl_i2c: Factor out adap parametermario.six@gdsys.cc2016-05-17-67/+49
| | | | Signed-off-by: Mario Six <mario.six@gdsys.cc>
* dm: fsl_i2c: Prepare compatibility functionsmario.six@gdsys.cc2016-05-17-8/+39
| | | | Signed-off-by: Mario Six <mario.six@gdsys.cc>
* dm: fsl_i2c: Rename methods for reading/writing datamario.six@gdsys.cc2016-05-17-8/+8
| | | | Signed-off-by: Mario Six <mario.six@gdsys.cc>
* dm: fsl_i2c: Rename probe methodmario.six@gdsys.cc2016-05-17-5/+5
| | | | Signed-off-by: Mario Six <mario.six@gdsys.cc>
* dm: fsl_i2c: Remove unnecessary variablemario.six@gdsys.cc2016-05-17-3/+2
| | | | Signed-off-by: Mario Six <mario.six@gdsys.cc>
* dm: fsl_i2c: Reword and clarify commentmario.six@gdsys.cc2016-05-17-14/+6
| | | | Signed-off-by: Mario Six <mario.six@gdsys.cc>
* dm: fsl_i2c: Use clearer parameter namesmario.six@gdsys.cc2016-05-17-31/+32
| | | | Signed-off-by: Mario Six <mario.six@gdsys.cc>
* dm: fsl_i2c: Rename I2C register structuremario.six@gdsys.cc2016-05-17-57/+66
| | | | Signed-off-by: Mario Six <mario.six@gdsys.cc>
* i2c: designware_i2c: Optionally check enable status registerStefan Roese2016-05-17-0/+9
| | | | | | | | | | | | | Some platforms don't implement the enable status register at offset 0x9c. The SPEAr600 platform is one of them. The recently added check to this status register can't be performend on these platforms. This patch introduces a new config option that can be enabled on such platforms not supporting this register. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>
* i2c: muxes: Add support for TI PCA954X muxMichal Simek2016-05-17-0/+90
| | | | | | | | | | | | | Add support for common TI i2c mux which is available on ZynqMP zcu102 board. DM i2c mux core code is selecting/deselecting bus before/after every command is performed that's why only one channel is active at a time. That's also the reason why deselect is just disable all available channels. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* i2c: cdns: Support different bus speedsMichal Simek2016-05-17-7/+69
| | | | | | | | | | 400kHz is maximum freq which can be used on Xilinx ZynqMP. Support it with standard divider calculator. Input freq is hardcoded to 100MHz input freq till we have clock driver which can provide this information for exact configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* i2c: cdns: Moving speed setup from probe to set_bus_speed functionMichal Simek2016-05-17-37/+11
| | | | | | | | set_bus_speed is the right function where bus speed should be setup. This move enable option to remove probe and remove functions which are empty. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* i2c: cdns: Read address from DT in ofdata_to_platdataMichal Simek2016-05-17-4/+12
| | | | | | | | Extract reading IP base address in function which is designed for it. Also enable option to read more information from DT in this function. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-05-06-167/+87
|\
| * mtd: cqspi: Simplify indirect read codeMarek Vasut2016-05-06-71/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The indirect read code is a pile of nastiness. This patch replaces the whole unmaintainable indirect read implementation with the one from upcoming Linux CQSPI driver, which went through multiple rounds of thorough review and testing. All the patch does is it plucks out duplicate ad-hoc code distributed across the driver and replaces it with more compact code doing exactly the same thing. There is no speed change of the read operation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Jagan Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vignesh R <vigneshr@ti.com>
| * mtd: cqspi: Simplify indirect write codeMarek Vasut2016-05-06-96/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The indirect write code is buggy pile of nastiness which fails horribly when the system runs fast enough to saturate the controller. The failure results in some pages (256B) not being written to the flash. This can be observed on systems which run with Dcache enabled and L2 cache enabled, like the Altera SoCFPGA. This patch replaces the whole unmaintainable indirect write implementation with the one from upcoming Linux CQSPI driver, which went through multiple rounds of thorough review and testing. While this makes the patch look terrifying and violates all best-practices of software development, all the patch does is it plucks out duplicate ad-hoc code distributed across the driver and replaces it with more compact code doing exactly the same thing. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Jagan Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vignesh R <vigneshr@ti.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-05-06-12/+18
|\ \
| * | usb: gadget: dfu: discard dead codePeng Fan2016-05-06-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reported by Coverity: Logically dead code (DEADCODE) dead_error_line: Execution cannot reach this statement: (f_dfu->strings + --i).s = .... If calloc failed, i is still 0 and no need to call free, so discard the dead code. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: "Łukasz Majewski" <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
| * | dfu: avoid memory leakPeng Fan2016-05-06-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When dfu_fill_entity fail, need to free dfu to avoid memory leak. Reported by Coverity: " Resource leak (RESOURCE_LEAK) leaked_storage: Variable dfu going out of scope leaks the storage it points to. " Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: "Łukasz Majewski" <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
| * | usb: dwc2: Add delay to fix the USB detection problem on SoCFPGAStefan Roese2016-05-06-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With patch c998da0d (usb: Change power-on / scanning timeout handling), the USB scanning is started earlier and with a smaller timeout. This resulted on SoCFPGA (using the DWC2 driver) in some USB sticks not getting detected any more. This patch now adds a 1 second delay (in the host mode only) to the DWC2 driver before the scanning is started. With this delay, now all problematic USB keys are detected successfully again. And there is no need any more to change the delay / timeout in the common USB code (usb_hub.c). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Marek Vasut <marex@denx.de>
| * | usb: ehci-mx6: allow board_ehci_hcd_init to failStefan Agner2016-05-06-2/+5
| |/ | | | | | | | | | | | | | | | | | | | | There could be runtime determined board specific reason why a EHCI initialization fails (e.g. ENODEV if a Port is not available). In this case, properly return the error code. While at it, that function (board_ehci_hcd_init) has actually two documentation blocks... Use the correct function name for the documentation block of board_usb_phy_mode. Signed-off-by: Stefan Agner <stefan@agner.ch>
* | Fix various typos, scattered over the code.Robert P. J. Day2016-05-05-8/+8
|/ | | | | | | | | | | | | Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller
* pci: tegra: fix DM conversion issues on Tegra20Stephen Warren2016-05-04-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra20's PCIe controller has a couple of quirks. There are workarounds in the driver for these, but they don't work after the DM conversion: 1) The PCI_CLASS value is wrong in HW. This is worked around in pci_tegra_read_config() by patching up the value read from that register. Pre-DM, the PCIe core always read this via a 16-bit access to the 16-bit offset 0xa. With DM, 32-bit accesses are used, so we need to check for offset 0x8 instead. Mask the offset value back to 32-bit alignment to make this work in all cases. 2) Accessing devices other than dev 1 causes a data abort. Pre-DM, this was worked around in pci_skip_dev(), which the PCIe core code called during enumeration while iterating over a bus. The DM PCIe core doesn't use this function. Instead, enhance tegra_pcie_conf_address() to validate the bdf being accessed, and refuse to access invalid devices. Since pci_skip_dev() isn't used, delete it. I've also validated that both these WARs are only needed for Tegra20, by testing on Tegra30/Cardhu and Tegra124/Jetson TKx. So, compile them in conditionally. Fixes: e81ca88451cf ("dm: tegra: pci: Convert tegra boards to driver model for PCI") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* drivers: net: ldpaa: Memset pools_params as "0" before usePrabhakar Kushwaha2016-05-03-0/+1
| | | | | | | | Memset pools_params as "0" to avoid garbage value in dpni_set_pools. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reported-by: Jose Rivera <german.rivera@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* usb: dwc2: Init desc_before_addrMarek Vasut2016-05-03-0/+3
| | | | | | | | | | | Initialize desc_before_addr, otherwise the USB core won't send the first 64B Get Device Descriptor request in common/usb.c function usb_setup_descriptor() . There are some USB devices which expect this sequence and otherwise can misbehave. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Tom Rini <trini@konsulko.com>
* usb: dwc2: Make OC protection configurableMarek Vasut2016-05-03-3/+14
| | | | | | | | | | Introduce a new flag in the controller private data, which allows selectively disabling the OC protection. Use the standard 'disable-over-current' OF prop to set this flag. This OC protection must be disabled on EBV SoCrates rev 1. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org>
* usb: dwc2: Pull Ext VBUS macro from dwc_otg_core_init()Marek Vasut2016-05-03-7/+14
| | | | | | | | | | | Introduce a boolean flag in the dwc2 controller private data and set it according to the macro (for now) instead of having this macro directly in the dwc_otg_core_init(). This will let us configure the flag from DT or such later on, if needed. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org>
* usb: dwc2: Pass private data into dwc_otg_core_init()Marek Vasut2016-05-03-2/+3
| | | | | | | | | | Pass the whole bulk of private data instead of just the regs, since the private data will soon contain important configuration flags. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org>
* Fix spelling of "occurred".Vagrant Cascadian2016-05-02-14/+14
| | | | | Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers/video/am335x-fb: Properly point framebuffer behind paletteMartin Pietryka2016-04-28-4/+4
| | | | | | | | | | | | | | | | | | | | | The DMA was outputting the palette on the screen because the base for the DMA was not after the palette. In addition to that, the ceiling was also too high, this led that the output on the screen was shifted. NOTE: According to the TRM, even in 16/24bit mode a palette is required in the first 32 bytes of the framebuffer. See also: https://e2e.ti.com/support/arm/sitara_arm/f/791/p/234967/834483#834483 "In this mode, the LCDC will assume all information is data and thus you need to ensure that the DMA points to the first pixel of data and not the first entry in the frame buffer which is the beginning of the 512 byte palette." Signed-off-by: Martin Pietryka <martin.pietryka@chello.at> Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at> Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
* drivers/video/am335x-fb: Add support for 16bpp formatMartin Pietryka2016-04-28-3/+19
| | | | | | | | | | | | | | | To support 16bpp we just need to change the raster_ctrl register accordingly. Also 32bpp mode should work as well, but was not tested. According to the TRM the uppermost byte will be ignored when LCD_TFT_24BPP_UNPACK is set. The switch logic is based on the Linux kernel tilcdc driver: drivers/gpu/drm/tilcdc/tilcdc_crtc.c: lines 407 through 419 (kernel was checked out at commit: bcc981e9ed8) Signed-off-by: Martin Pietryka <martin.pietryka@chello.at> Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at> Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
* Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2016-04-25-1/+1
|\
| * drivers/video/am335x-fb: Fix bits for LCD_PALMODE_RAWDATA definitionMartin Pietryka2016-04-25-1/+1
| | | | | | | | | | | | | | According to the TRM you have to set bits [21:20] to 0b10 for RAW mode, so (0x10 << 20) is obviously wrong here. Signed-off-by: Martin Pietryka <martin.pietryka@chello.at>
* | pci: Device scanning range fixYoshinori Sato2016-04-25-1/+1
| | | | | | | | | | | | | | | | The terminal condition in the area where a PCI device is scanned is wrong, and 1f.7 isn't scanned. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | mmc: sdhci: add const qualifier to the name of struct sdhci_hostMasahiro Yamada2016-04-25-3/+3
| | | | | | | | | | | | | | This allows to drop annoying (char *) casts when setting the host name of struct sdhci_host. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | sf: fix timebase data type in _wait_ready()Stephen Warren2016-04-25-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | get_timer() returns an unsigned 64-bit value, but is currently assigned to a signed 32-bit variable. Due to sign extension and data truncation, this causes the timeout loop in spi_flash_cmd_wait_ready() to immediately (and incorrectly) fire for about 50% of all time values, based on whether bit 31 is set. In sandbox at least, this causes the test to pass or fail based on system uptime, as opposed to time since the U-Boot binary was started. Fixes: 4efad20a1751 ("sf: Update status reg check in spi_flash_cmd_wait_ready") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-uniphierTom Rini2016-04-25-106/+110
|\ \
| * | clk: uniphier: add Media I/O clock driver support for PH1-LD20Masahiro Yamada2016-04-24-0/+4
| | | | | | | | | | | | | | | | | | PH1-LD20 needs this for its SD card controller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: fix NAND and SD pin-mux settings for PH1-LD11/LD20Masahiro Yamada2016-04-24-4/+4
| | | | | | | | | | | | | | | | | | | | | I found many mistakes in the initial version. Fixes: 8a3328c209d0 ("pinctrl: uniphier: support UniPhier PH1-LD20 pinctrl driver") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: rename function/array namesMasahiro Yamada2016-04-24-102/+102
| |/ | | | | | | | | | | Make function/array names match the file names for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-usbTom Rini2016-04-25-50/+81
|\ \
| * | dfu: ram: fix number base of RAM entity parametersStephen Warren2016-04-25-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot typically interprets unprefixed numbers as base 16, and DFU RAM entity parsing has historically done so. Reverse the change to default to base 10, so that values in previously working command-lines aren't mis-parsed, causing RAM corruption, crashes, hangs, etc. Fixes: 6aeb877afef0 ("drivers: dfu: ram: fix a crash with dfu ram with invalid dfu_alt_info env") Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> [Test HW: AM335x BBB]
| * | drivers: dfu: ram: fix a crash with dfu ram with invalid dfu_alt_info envMugunthan V N2016-04-25-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot crashes when an invalid dfu_alt_info is set and tried using dfu command. Fixing this as it is handled in dfu-mmc. => dfu 0 ram 0 data abort pc : [<9ff893d6>] lr : [<9ff6edb9>] reloc pc : [<808323d6>] lr : [<80817db9>] sp : 9ef36cf0 ip : 00000158 fp : 9ffbc0b8 r10: 9ffbc0b8 r9 : 9ef36ed8 r8 : 00000000 r7 : 00000000 r6 : 9ffbc0c8 r5 : 9ef36cfc r4 : 9ef392c8 r3 : 00000004 r2 : 00000000 r1 : 9ff9a985 r0 : ffffffff Flags: Nzcv IRQs off FIQs on Mode SVC_32 Resetting CPU ... resetting ... Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | usb: s3c-otg: Fix remaining bytes in debug messagesRoger Quadros2016-04-25-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remaining bytes means bytes that are not yet transferred and not the bytes that were transferred in the last transfer. Reported-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Tested-by: Steve Rae <srae@broadcom.com> [Test HW: bcm28155_ap board]
| * | usb: s3c-otg: Fix short packet for request size > ep.maxpacketRoger Quadros2016-04-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Request size can be greater than ep.packet and still end in a short packet. We need to tackle this case as end of transfer (if short_not_ok is not set) as indicated in USB 2.0 Specification [1], else we get stuck up on certain protocols like fastboot. [1] - USB2.0 Specification, Section 5.3.2 Pipes Reported-by: Steve Rae <steve.rae@broadcom.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Tested-by: Steve Rae <steve.rae@broadcom.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com>
| * | fastboot: Clean up bulk-out logicRoger Quadros2016-04-25-27/+23
| | | | | | | | | | | | | | | | | | | | | | | | Just use ep->maxpacket to get the maxpacket size and simplify the bulk-out maxpacket alignment. Signed-off-by: Roger Quadros <rogerq@ti.com> Tested-by: Steve Rae <srae@broadcom.com>
| * | fastboot: Enable the respective speed endpoints at runtimeRoger Quadros2016-04-25-7/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In a dual speed configuration we need to check at runtime if we want to enable the Full-Speed or High-Speed endpoint. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Steve Rae <srae@broadcom.com> [Test HW: bcm235xx board]
generated by cgit v1.1 at 2024-12-29 10:35:40 +0000