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| * ARM: Rmobile: Rename CONFIG_RMOBILE to CONFIG_ARCH_RMOBILENobuhiro Iwamatsu2016-08-17-1/+1
| | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | pinctrl: fix typos in comment blocks of pinconfig_post_bind()Masahiro Yamada2016-08-20-2/+2
| | | | | | | | | | | | '-' is never used in function names. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | fastboot: implement KconfigSteve Rae2016-08-20-0/+5
| | | | | | | | | | | | implement Kconfig for the 'fastboot' feature set Signed-off-by: Steve Rae <steve.rae@raedomain.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-08-16-21/+334
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| * | i2c: intel_i2c: SMBus driver PCI addition (e.g. BayTrail)Stefan Roese2016-08-16-21/+269
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the SMBus block read/write functionality. Other protocols like the SMBus quick command need to get added if this is needed. This patch also removed the SMBus related defines from the Ivybridge pch.h header. As they are integrated in this driver and should be used from here. This change is added in this patch to avoid compile breakage to keep the source git bisectable. Tested on a congatec BayTrail board to configure the SMSC2513 USB hub. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de> Cc: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | misc: Add simple driver for some Nuvoton NCT6102D devicesStefan Roese2016-08-16-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This simple driver provides some functions to control some of the integrated devices. The watchdog is enabled per default. This driver adds a function to disable the watchdog. Also the internal legacy UART (io address 0x3f8/0x2f8) is enabled per default. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org>
* | | mmc: mmc_legacy: fix the compiler error with disabled CONFIG_DM_MMC_OPSJaehoon Chung2016-08-16-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To prevent the compiler error, split the checking condition whether cfg->ops is NULL or not. It's more clearly, because it's not included in mmc_config structure when CONFIG_DM_MMC_OPS is disabled. drivers/mmc/mmc_legacy.c: In function ‘mmc_create’: drivers/mmc/mmc_legacy.c:118:31: error: ‘const struct mmc_config’ has no member named ‘ops’ drivers/mmc/mmc_legacy.c:118:58: error: ‘const struct mmc_config’ has no member named ‘ops’ make[1]: *** [drivers/mmc/mmc_legacy.o] Error 1 Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | mmc: send CMD0 before CMD1 for some MMC cardsYangbo Lu2016-08-16-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the MMC framework was added in u-boot, the mmc_go_idle was added before mmc_send_op_cond_iter in function mmc_send_op_cond annotating that some cards seemed to need this. Actually, we still need to do this in function mmc_complete_op_cond for those cards. This has been verified on Micron MTFC4GACAECN eMMC chip. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* | | drivers: mmc: omap_hsmmc: fix build breakageSekhar Nori2016-08-16-0/+2
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | structure member 'cd_inverted' of omap_hsmmc_data is available only when OMAP_HSMMC_USE_GPIO is defined. When CONFIG_DM_MMC is defined, but not CONFIG_OMAP_GPIO, this will cause build breakage in omap_hsmmc driver of the sort: CC drivers/mmc/omap_hsmmc.o ../drivers/mmc/omap_hsmmc.c: In function 'omap_hsmmc_ofdata_to_platdata': ../drivers/mmc/omap_hsmmc.c:1763:6: error: 'struct omap_hsmmc_data' has no member named 'cd_inverted' priv->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted"); ^ Fix this by accessing cd_inverted only when OMAP_HSMMC_USE_GPIO is defined. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | xtensa: add support for the 'xtfpga' evaluation boardChris Zankel2016-08-15-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'xtfpga' board is actually a set of FPGA evaluation boards that can be configured to run an Xtensa processor. - Avnet Xilinx LX60 - Avnet Xilinx LX110 - Avnet Xilinx LX200 - Xilinx ML605 - Xilinx KC705 These boards share the same components (open-ethernet, ns16550 serial, lcd display, flash, etc.). Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-08-15-74/+1794
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| * | mmc: atmel_sdhci: Convert to the driver model supportWenyou Yang2016-08-15-0/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the driver to the driver model while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | dm: atmel: Add driver model support for the ehci driverWenyou Yang2016-08-15-0/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver model support while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | pinctrl: at91-pio4: Add pinctrl driverWenyou Yang2016-08-15-0/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AT91 PIO4 controller is a combined gpio-controller, pin-mux and pin-config module. The peripheral's pins are assigned through per-pin based muxing logic. The pin configuration is performed on specific registers which are shared along with the gpio controller. So regard the pinctrl device as a child of atmel_pio4 device. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | gpio: atmel_pio4: Rework to support DM & DTWenyou Yang2016-08-15-23/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rework the driver to support driver model and device tree, and support to regard the pio4 pinctrl device as a child of atmel_pio4 device. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | gpio: atmel_pio4: Move PIO4 definitions to head fileWenyou Yang2016-08-15-53/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | In order to make these PIO4 definitions shared with AT91 PIO4 pinctrl driver, move them from the existing gpio driver to the head file, and rephrase them. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | clk: at91: Add clock driverWenyou Yang2016-08-15-0/+776
| | | | | | | | | | | | | | | | | | | | | | | | The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | tpm: atmel_twi: Make compatible with DM I2C bussesmario.six@gdsys.cc2016-08-15-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 302c5db ("dm: tpm: Add Driver Model support for tpm_atmel_twi driver") converted the Atmel TWI TPM driver itself to driver model, but kept the legacy-style i2c_write/i2c_read calls. Commit 3e7d940 ("dm: tpm: Every TPM drivers should depends on DM_TPM") then made DM_I2C a dependency of the driver, effectively forcing users to turn on CONFIG_DM_I2C_COMPAT to get it to work. This patch adds the necessary dm_i2c_write/dm_i2c_read calls to make the driver compatible with DM, but also keeps the legacy calls in ifdefs, so that the driver is now compatible with both DM and non-DM setups. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | i2c: atmel: add i2c driverSongjun Wu2016-08-15-0/+426
| | | | | | | | | | | | | | | | | | | | | | | | Add i2c driver. Signed-off-by: Songjun Wu <songjun.wu@atmel.com> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-08-15-369/+980
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| * | | net: mii: Changes not made by spatchJoe Hershberger2016-08-15-50/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the functions passed to the registration function are not in the same C file (extern) then spatch will not handle the dependent changes. Make those changes manually. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> For the 4xx related files: Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | net: mii: Fix changes made by spatchJoe Hershberger2016-08-15-37/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the changes were a bit too complex. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | net: mii: Use spatch to update miiphy_registerJoe Hershberger2016-08-15-145/+381
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Run scripts/coccinelle/net/mdio_register.cocci on the U-Boot code base. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | net/ethoc: implement MDIO bus and support phylibMax Filippov2016-08-15-6/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement MDIO bus read/write functions, initialize the bus and scan for the PHY when phylib is enabled. Limit PHY speeds to 10/100 Mbps. Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | net/ethoc: support private memory configurationsMax Filippov2016-08-15-5/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ethoc device can be configured to have a private memory region instead of having access to the main memory. In that case egress packets must be copied into that memory for transmission and pointers to that memory need to be passed to net_process_received_packet or returned from the recv callback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | net/ethoc: don't mix virtual and physical addressesMax Filippov2016-08-15-10/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Addresses used in buffer descriptors and passed in platform data or device tree are physical. Addresses used by CPU to access packet data and registers are virtual. Don't mix these addresses and use virt_to_phys for translation. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | net/ethoc: support device treeMax Filippov2016-08-15-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add .of_match table and .ofdata_to_platdata callback to allow for ethoc device configuration from the device tree. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | net/ethoc: add CONFIG_DM_ETH supportMax Filippov2016-08-15-47/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extract reusable parts from ethoc_init, ethoc_set_mac_address, ethoc_send and ethoc_receive, move the rest under #ifdef CONFIG_DM_ETH. Add U_BOOT_DRIVER, eth_ops structure and implement required methods. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | net/ethoc: use priv instead of dev internallyMax Filippov2016-08-15-55/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't use physical base address of registers directly, ioremap it first. Save pointer in private struct ethoc and use that struct in all internal functions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | net/ethoc: add Kconfig entry for the driverMax Filippov2016-08-15-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Kconfig entry for the driver, remove #define CONFIG_ETHOC from the only board configuration that uses it and put it into that board's defconfig. Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | net: e1000: Fix the build with driver model and SPI EEPROMAlban Bedel2016-08-15-30/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When adding support for the driver model the SPI EEPROM feature had been ignored. Fix the build with both CONFIG_DM_ETH and CONFIG_E1000_SPI enabled. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | net: smsc95xx: Use correct get_unaligned functionsChris Packham2016-08-15-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The __get_unaligned_le* functions may not be declared on all platforms. Instead, get_unaligned_le* should be used. On many platforms both of these are the same function. Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | net: macb: Fix build error for CONFIG_DM_ETH enabledWenyou Yang2016-08-15-8/+69
| |/ / | | | | | | | | | | | | | | | | | | | | | Use the right phy_connect() prototype for CONFIGF_DM_ETH. Support to get the phy interface from dt and set GMAC_UR. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | i2c: tegra: add standardized clk/reset API supportBryan Wu2016-08-15-4/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk/reset API was tested on T186 platform and previous chip like T210/T124 will still use the old APIs. Signed-off-by: Bryan Wu <pengw@nvidia.com> (swarren, simplified some ifdefs, removed indent level inside an ifdef) (swarren, added comment about the ifdefs) Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | pci: tegra: port to standard clock/reset/pwr domain APIsStephen Warren2016-08-15-5/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra186 supports the new standard clock, reset, and power domain APIs. Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so that it can operate with either set of APIs. On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming. Consequently, this logic is disabled too. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | mmc: tegra: port to standard clock/reset APIsStephen Warren2016-08-15-9/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra186 supports the new standard clock and reset APIs. Older Tegra SoCs still use custom APIs. Enhance the Tegra MMC driver so that it can operate with either set of APIs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | i2c: add Tegra186 BPMP driverStephen Warren2016-08-15-0/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Tegra186, some I2C controllers are directly controlled by the main CPU, whereas others are controlled by the BPMP, and can only be accessed by the main CPU via IPC requests to the BPMP. This driver covers the latter case. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | power domain: add Tegra186 driverStephen Warren2016-08-15-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Tegra186, SoC power domains are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | reset: add Tegra186 reset driverStephen Warren2016-08-15-0/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Tegra186, on-SoC reset signals are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | clock: add Tegra186 clock driverStephen Warren2016-08-15-0/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. A tegra/ sub-directory is created to follow the existing pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | misc: add Tegra BPMP driverStephen Warren2016-08-15-0/+270
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra BPMP (Boot and Power Management Processor) is a separate auxiliary CPU embedded into Tegra to perform power management work, and controls related features such as clocks, resets, power domains, PMIC I2C bus, etc. This driver provides the core low-level communication path by which feature-specific drivers (such as clock) can make requests to the BPMP. This driver is similar to an MFD driver in the Linux kernel. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-08-12-11/+25
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| * | misc: add "call" uclass opStephen Warren2016-08-12-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The call op requests that the callee pass a message to the underlying HW or device, wait for a response, and then pass back the response error code and message to the callee. It is useful for drivers that represent some kind of messaging or IPC channel to a remote device. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | power: pmic: act8846: add missing newline to debug statementsJohn Keeping2016-08-12-2/+2
| | | | | | | | | | | | | | | Signed-off-by: John Keeping <john@metanate.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | power: regulator: act8846: fix reading valuesJohn Keeping2016-08-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The voltage and control registers need to be looked up from the value in driver_data. Adjust the get_value and get_enable functions to match the corresponding set_* functions. Signed-off-by: John Keeping <john@metanate.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | fdt: allow fdtdec_get_addr_size_*() to translate addressesStephen Warren2016-08-12-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some code may want to read reg values from DT, but from nodes that aren't associated with DM devices, so using dev_get_addr_index() isn't appropriate. In this case, fdtdec_get_addr_size_*() are the functions to use. However, "translation" (via the chain of ranges properties in parent nodes) may still be desirable. Add a function parameter to request that, and implement it. Update all call sites to default to the original behaviour. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Squashed in build fix from Stephen: Signed-off-by: Simon Glass <sjg@chromium.org>
* | | kconfig: use bool instead of boolean for type definition attributesMasahiro Yamada2016-08-12-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux stopped the use of keyword 'boolean' in Kconfig. Refer to commit 6341e62b212a2541efb0160c470e90bd226d5496 ("kconfig: use bool instead of boolean for type definition attributes") in Linux Kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | drivers: net: cpsw: always flush cache of size aligned to PKTALIGNLokesh Vutla2016-08-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpsw tries to flush dcache which is not in the range of PKTALIGN. Because of this the following warning comes while flushing: CACHE: Misaligned operation at range [dffecec0, dffed016] Fix it by flushing cache of size aligned to PKTALIGN. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | drivers/sysreset: group sysreset driversMax Filippov2016-08-12-12/+212
| | | | | | | | | | | | | | | | | | | | | | | | Create drivers/sysreset and move sysreset-uclass and all sysreset drivers there. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | i2c: Drop redundant platform data setting in driversSimon Glass2016-08-12-6/+0
|/ / | | | | | | | | | | | | | | | | The i2c uclass has a default setting for per_child_platdata_auto_alloc_size so drivers do not need to set it. Remove this from drivers to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-11-08 22:26:40 +0000