| Commit message (Collapse) | Author | Age | Lines |
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The reset_sata should reset the sata device info and free the probe_ent
memory. Otherwise, it will cause memory leak if we init the sata again.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 39c9261fd057b0fa98f9dfdee7d368aa029ff736)
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i.MX6UL/ULL evk board net get the wrong MAC address from fuse, exp,
eth1 get MAC0 address, eth0 get MAC1 address from fuse. Set the
priv->dev_id to device->seq as the real net interface alias id then
.fec_get_hwaddr() read the related MAC address from fuse.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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Fix coverity:392391 392382 392385 Unsigned compared against 0
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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The device managed API actually not free the memory, so need
to use devm_kfree to free the memory to avoid leakage.
Coverity: 392384 resource leak
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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There are two problems in enabling DDR mode in this new driver:
1. The TDH bits in FLSHCR register should be set to 1. Otherwise, the TX DDR delay logic
won't be enabled. Since u-boot driver does not have DDR commands in LUT. So this won't
cause explicit problem.
2. When doing read/write/readid/erase operations, the MCR register is overwritten, the bits
like DDR_EN are cleared during these operations. When we using DDR mode QSPI boot, the TDH bit
is set to 1 by ROM. if the DDR_EN is cleared, there is no clk2x output for TX data shift.
So these operations will fail.
The explicit problem is users may get "SF: unrecognized JEDEC id bytes: ff, ff, ff" error
after using DDR mode QSPI boot on 6UL/ULL EVK boards.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The compatible string "fsl,imx6sl-fec" is missed for i.mx6sl in
u-boot FEC driver, so that FEC can't be recognized.
Signed-off-by: Ye Li <ye.li@nxp.com>
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For LPI2C IP, NACK is detected by the rising edge of the ninth clock.
In current uboot driver, once NACK is detected, it will reset and then
disable LPI2C master. As a result, we can never see the falling edge
of the ninth clock.
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
(cherry picked from commit dd139ee52b709c95af3e0c968bcbc3cf42cca408)
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Current USDHC driver will reset VSELECT to 0 (3.3v) during mmc init,
then set to 1 for 1.8v eMMC I/O. When booting from eMMC, since ROM has
already set VSELECT to 1.8v before running the u-boot. This reset in
USDHC driver causes a short 2.2v pulse on CMD pin.
Fix this issue by not reset VSELECT to 0 when 1.8v flag is set.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit f01ebfdaa57b4c74ede32a6a40cf9cf9184ce049)
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Fix wrong usage of device_get_supply_regulator.
device_get_supply_regulator returns 0 on success.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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The sparse image writing and boot image reading may have cache unaligned problem.
The u-boot v2017 will print warning at runtime. This patch fixes the
unaligned problem.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The endianness is not set at qspi driver initialization. So if we don't
boot from QSPI, we will get wrong endianness when accessing from AHB address
directly.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The wp-gpios property is used for gpio, if this is set, the WP pin is muxed
to gpio function, can't be used as internal WP checking.
This patch changes to examine the "fsl,wp-controller" for using internal WP checking. And
wp-gpios for using gpio pin.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Change the i2c alias seq number to align with device index. So in lpi2c
driver we don't need to add 4 to get the device index. This codes may not
valid on other platforms.
Signed-off-by: Ye Li <ye.li@nxp.com>
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1. pass androidboot.storage_type to android, 'init' use it to parse
different init.freescale.storage.rc.
2. store new ptable with gpt partition.
3. we use the last LBA as backup gpt table, there is many warning log
when boot, change print to debug
Change-Id: I84070735e9d4c2741b0e240bc1c61b357dabc5b8
Signed-off-by: Sanshan Zhang <sanshan.zhang@nxp.com>
(cherry picked from commit da0ce2787256a323371641b0764266d386d767a5)
Signed-off-by: Ye Li <ye.li@nxp.com>
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Integrate the FSL android fastboot features into community's fastboot.
1. Use USB gadget g_dnl driver
2. Integrate the FSL SD/SATA/NAND flash operations, since the GPT and
EFI partitions are not support by i.MX.
3. Add FDT support to community's android image.
4. Add a new boot command "boota" for android image boot. The boota
implements to load ramdisk and fdt to their loading addresses
specified in boot.img header, while bootm won't do it for android image.
5. Support the authentication of boot.img at the "load_addr" for
both SD and NAND.
6. We use new configuration CONFIG_FSL_FASTBOOT for Freescale's fastboot
with relevant header file "fsl_fastboot.h". While disabling the
configuration, the community fastboot is used.
7. Overwrite the cmdline in boot.img by using bootargs saved in local environment.
8. Add recovery and reboot-bootloader support.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 23d63ff185929fff5e392efc853d69b606ba081a)
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The i.MX6SL EVK needs this driver in android fastboot support. Add
this driver to u-boot.
To use the driver, user must define:
CONFIG_MXC_KPD Enable the driver
CONFIG_MXC_KEYMAPPING Key mapping matrix
CONFIG_MXC_KPD_COLMAX The column size of key mapping matrix
CONFIG_MXC_KPD_ROWMAX The row size of the key mapping matrix
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 5096e572667ff41217deb4ba9b1bd15e93fa6b59)
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Add MT35XU512ABA parameters to NOR flash parameters array. Since the
manufactory ID is changed to 0x2C, add it for micron and using it for
relevant settings.
The MT35XU512ABA only supports 1 bit mode and 8 bits. It can't support
dual and quad. Because the 8 bits is not support by u-boot framework and
driver. We only use 1 bit mode for this flash.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The LCDIF provides video source for MIPI DSI host at DPI-2 interface.
When the LCDIF Framebuffer driver is enabled, it uses the panel
parameters setup by environments to create a panel device and register
it to DSI host driver and then enable the DSI host.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 85659ea5ee975fa2d5fa7215e17a01f7006c39bf)
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Add the mipi dsi panel driver for device HX8363 from kernel. The panel
driver needs work with mipi_dsi_northwest driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 0c6d0f4202bae7f61d38ecff1c9d255261f022f2)
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Add the host driver base from kernel for MIPI DSI controller on i.MX7ULP.
The controller provides a DPI-2 interface for LCDIF video stream, and a APB interface
for packet transmission.
The driver provides APIs to register a MIPI panel device and its driver. The panel
driver can use the write packet function provided by the host driver to send control
packets to panel device via APB interface.
MIPI DSI has its PHY and dedicated PLL. The driver will setup them when enabling the DSI
host.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit e02115dd1c5d36ec06eabcb5a0b8e09aaf0f29a0)
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The i.MX7ulp EVK board uses GPIO to detect ID for USB OTG0,
but when using DM USB driver, it is hard coded to use OTG ID pin.
Add a board override function that when extcon property is provided,
the function can check the GPIO to get ID.
Signed-off-by: Ye Li <ye.li@nxp.com>
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In mx7ulp pinctrl driver, we should create two info instances for
iomuxc0 and iomuxc1 respective, otherwise they will share the same
info instance, and cause problem in get base address... etc.
Signed-off-by: Ye Li <ye.li@nxp.com>
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when using SHARE_MUX_CONF_REG, wrong mask is used for writing config value.
which causes mux value is cleared.
Signed-off-by: Ye Li <ye.li@nxp.com>
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On i.MX7ULP, the fuse words (except bank 0 and 1) only supports to write once,
because they use ECC mode. Multiple writes may damage the ECC value and cause a
wrong fuse value decoded when reading.
This patch adds a checking before the fuse word programming, only can write
when the word value is 0.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit e8447d649a631ec98120d84fab124ca29fbe39f0)
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On mx7ulp EVK board, we use MX25R6435F NOR flash, add its parameters
and IDs to flash parameter array. Otherwise, the flash probe will fails.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The mx7ulp has small TX/RX FIFO (64Bytes) and AHB buffer size (128Bytes)
than other i.MX. Change some parameters for it.
Also found when the DDR_EN bit is set, sometime the page programming will fail
during large data programming. The 64 bytes data is not programmed into flash.
But when DDR_EN is clear, there is no such issue. Suspect this is a IC issue.
We have disable the DDR_EN for mx7ulp.
Signed-off-by: Ye Li <ye.li@nxp.com>
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When doing port reset, the PR bit of PORTSC1 will be automatically
cleared by our IP, but standard EHCI needs explicit clear by software. The
EHCI-HCD driver follow the EHCI specification, so after 50ms wait, it
clear the PR bit by writting to the PORTSC1 register with value loaded before
setting PR.
This sequence is ok for our IP when the delay time is exact. But when the timer
is slower, some bits like PE, PSPD have been set by controller automatically
after the PR is automatically cleared. So the writing to the PORTSC1 will overwrite
these bits set by controller. And eventually the driver gets wrong status.
We implement the powerup_fixup operation which delays 50ms and will check
the PR until it is cleared by controller. And will update the reg value which is written
to PORTSC register by EHCI-HCD driver. This is much safer than depending on the delay
time to be accurate and aligining with controller's behaiver.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 8dfdf83abaff44efb487f801cd1757a729d427c5)
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The ULP has two USB controllers. These two controllers have similar NC
registers layout as i.MX7D. But OTG0 uses UTMI PHY simliar as i.MX6, not
the integrated PHY on i.MX7D. The OTG1 needs off-chip HSIC PHY or ULPI PHY
to work.
This patch only supports OTG0 with UTMI PHY.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 1ac22cabb96a14ac4ca58df60ae2025fb5e94db6)
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Add compatible property for i.MX7ULP.
Add a weak init_usdhc_clk function, i.MX7ULP use this to init the clock.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
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Add i.MX7ULP support.
The buadrate calculation on i.MX7ULP is different,so add a new setbrg
function for i.MX7ULP.
Add a enum lpuart_devtype for runtime check for different platforms.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Shaohui Xie <Shaohui.Xie@nxp.com>
Cc: Alison Wang <b18965@freescale.com>
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Drop CONFIG_LPUART_32B_REG.
Move the register structure to a common file include/fsl_lpuart.h
Define lpuart_serial_platdata structure which includes the reg base and flags.
For 32Bit register access, use lpuart_read32/lpuart_write32 which handles
big/little endian.
For 8Bit register access, still use the orignal code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Shaohui Xie <Shaohui.Xie@nxp.com>
Cc: Alison Wang <b18965@freescale.com>
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Add lpi2c driver for i.MX7ULP.
Need to enable the two options to use this driver:
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
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Add i.MX7ULP pinctrl driver.
Select CONFIG_PINCTRL_IMX7ULP to use this driver.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by : Stefano Babic <sbabic@denx.de>
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This driver implements the HW WATCHDOG functions. Which needs
to set CONFIG_HW_WATCHDOG to use them. This is disabled by default for
mx7ulp.
Use watchdog for reset cpu. Implement this in the driver.
Need to define CONFIG_ULP_WATCHDOG to build it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
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Update the mxc_ocotp driver to support i.MX7ULP.
The read/write sequence has some changes due to
PDN and OUT_STATUS registers added and TIME register is
removed. Also update the bank size and number.
Add is_mx7ulp macro in sys_proto.h
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
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Add the imx_rgpio2p driver for Rapid GPIO2P controllers on i.MX7ULP.
Have added all ports on RGPIO2P_0 and RGPIO2P_1.
The configurations CONFIG_IMX_RGPIO2P and CONFIG_DM_GPIO must be set
to y to enable the drivers.
To use the GPIO function, the IBE and OBE needs to set in IOMUXC.
We did not set the bits in driver, but leave them to IOMUXC settings
of the GPIO pins. User should use IMX_GPIO_NR to generate the GPIO number
for gpio APIs access.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
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Add fuse checking for EPDC module. Once the fused is programmed, the
EPDC module is disabled, can't to access it.
Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit ea7429b70c1eb2cf475028ee8df2ac9ed18b3c82)
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After porting to v2017.03. we start to use community's QSPI driver,
not the one we maintained before in v2014-v2016.
The new QSPI driver only supports i.MX6SX. This patch adds support
for i.MX6UL and i.MX7D
Signed-off-by: Ye Li <ye.li@nxp.com>
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Specify the registered eth index by dev_id.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit df42b7b0c5e6847f32419075eb25f274ed039d6f)
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Avoid transfer parameter dev_id value with "-1" to .fec_get_hwaddr(),
it should transfer fec->dev_id to get mac address from fuse.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit 7e4a55b068311d46d16e86e697d36f34a59bf47a)
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The MIB RAM and FIFO receive start register does not exist on
i.MX6ULL. Accessing these register will cause enet not work well or
cause system report fault.
Reported-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 5fb09cab9bb3cc4cef02239299d02cec666396ab)
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Add the fuse checking in drivers, when the module is disabled in fuse,
the driver will not work.
Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C,
USB-EHCI, GIS, LCDIF.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 1704e116f9b39aeb99201919a18bc2b1e19a980e)
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Enable pcie support in uboot on imx6sx sd boards
- enable_pcie_clock should be call before ssp_en is set,
since that ssp_en control the phy_ref clk gate, turn on
it after the source of the pcie clks are stable.
- add debug info
- add rx_eq of gpr12 on imx6sx
- there are random link down issue on imx6sx. It's
pcie ep reset issue.
solution:reset ep, then retry link can fix it.
(cherry picked from commit ec78595a24b5ff1020baa97b6d6e79a3a3326307)
Signed-off-by: Richard Zhu <r65037@freescale.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 81fd30250110d72992758f08b66c07306126892b)
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On i.MX6SX, 6UL and 7D, there are two enet controllers each has a
MDIO port. Some boards share the MDIO port for the two enets. So
introduce a configuration CONFIG_FEC_MXC_MDIO_BASE to indicate
the MDIO port for sharing.
In Kconfig, user needs enable CONFIG_FEC_MXC_SHARE_MDIO first to enter
the CONFIG_FEC_MXC_MDIO_BASE.
Without defining this configuration, the enet will uses own MDIO port.
Also add this configurationfor FEC DM driver, since the ENET PHY currently
does not support FDT.
Modify the dev_id for DM driver, the first fec will set dev_id with 0, while
second fec sets the dev_id with 1. So the MII bus name won't be duplicated.
Then we can add two FEC devices from DTB.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 088afc073c480bd02208145bfb04259ccdf391c1)
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Add gis module, current gis is support vadc input.
Add power down function to lcdif driver.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit a007b00dd8ef9f773dfdebef0b1deb0990281793)
(cherry picked from commit a31dcdafb0963381e7213c59f79a340ef27ec2e2)
(cherry picked from commit 02dfe2e4af5f51d39a51542fb0e81f93faf505bc)
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Add pxp module.
Support csc between YUV444 and RGB888 and scaling.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 4c6e1f9ed1b2f5c98a34502b44b6414593fdd290)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 92295fafcdbaa3a3fe0a63ede15f896dfc9ce0b0)
(cherry picked from commit 096a63e81a8c78b3f8bbc65a9d418aa032d62231)
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Add csi module.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 854ae26758ec8132ef749b98645dd2f43b84e5e2)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 5f133bd9420109951fd03bd5168801327e929c3b)
(cherry picked from commit 16960e59fa3334162d2e2212ee4bc1e7f0c420a3)
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Add vadc module.
Both PAL and NTSC mode can work.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 03c31ae30c1e81c99f6824221e4801433445e04a)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit b5d776ffc1519c16091736445b3217ffb7fcd7db)
(cherry picked from commit 2377eb9fd299b76888f11faf76383b68e77bcc8a)
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The string display on second line repeats the last word of
first line and does not show full.
This is the bug introduced by the fixing to MLK-10542.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit ac430cee8c42f0acad9e126631d772b99f1166ea)
(cherry picked from commit ff62c5b275a9b5e47d570d3eb10622799bf12070)
(cherry picked from commit bd265a064c8f797e542955352d170e7f20f7b0d1)
(cherry picked from commit aaa55881de3e9aa8232c819a2c8a3abb285b682f)
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The caculation of left space for version string is not correct, should
use VIDEO_COLS not VIDEO_LINE_LEN / 2, otherwise we will get larger space
than actual have and cause string to overlay logo picture.
Also current version string display only supports two lines words at max.
This also causes overlay when the LCD pixel colume size is not enough.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit ed53487d36a886fb4557088804a4b5232b168889)
(cherry picked from commit 253936bb920c5bb8e7d26e0425d155fb2576ab77)
(cherry picked from commit a12ec4c29b4cbdf03ae68a5ecb739253f79b59fc)
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