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* Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2015-11-05-6/+5
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| * video: Drop DEV_EXT_VIDEO flagBin Meng2015-11-05-1/+0
| | | | | | | | | | | | DEV_EXT_VIDEO does not have any actual meaning, hence drop it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * video: Drop DEV_FLAGS_SYSTEM flagBin Meng2015-11-05-5/+5
| | | | | | | | | | | | DEV_FLAGS_SYSTEM does not have any actual meaning, hence drop it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge git://git.denx.de/u-boot-samsungTom Rini2015-11-05-7/+862
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| * | s5p sdhci: call pinmux for card's gpio pins before use themPrzemyslaw Marczak2015-11-02-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SD card detection depends on checking one pin state. But the pin was configured after card was detected, which is wrong. This commit fixes this, by moving call to pinmux before use the pin. Tested-on: Odroid U3 and Odroid X2. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | sandbox: add ADC driverPrzemyslaw Marczak2015-11-02-0/+184
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds implementation of Sandbox ADC device emulation. The device provides: - single and multi-channel conversion - 4 channels with predefined conversion output data - 16-bit resolution Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | dm: adc: add Exynos54xx compatible ADC driverPrzemyslaw Marczak2015-11-02-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds driver for Exynos54xx ADC subsystem. The driver is implemented using driver model, amd provides ADC uclass's methods for ADC single channel operations: - adc_start_channel() - adc_channel_data() - adc_stop() The basic parameters of ADC conversion, are: - sample rate: 600KSPS - output the data as average of 8 time conversion ADC features: - sample rate: 600KSPS - resolution: 12-bit - channels: 10 (analog multiplexer) Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | dm: adc: add simple ADC uclass implementationPrzemyslaw Marczak2015-11-02-0/+432
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds: - new uclass id: UCLASS_ADC - new uclass driver: drivers/adc/adc-uclass.c The new uclass's API allows for ADC operation on: * single-channel with channel selection by a number * multti-channel with channel selection by bit mask ADC uclass's functions: * single-channel: - adc_start_channel() - start channel conversion - adc_channel_data() - get conversion data - adc_channel_single_shot() - start/get conversion data * multi-channel: - adc_start_channels() - start selected channels conversion - adc_channels_data() - get conversion data - adc_channels_single_shot() - start/get conversion data for channels selected by bit mask * general: - adc_stop() - stop the conversion - adc_vdd_value() - positive reference Voltage value with polarity [uV] - adc_vss_value() - negative reference Voltage value with polarity [uV] - adc_data_mask() - conversion data bit mask The device tree can provide below constraints/properties: - vdd-polarity-negative: if true: Vdd = vdd-microvolts * (-1) - vss-polarity-negative: if true: Vss = vss-microvolts * (-1) - vdd-supply: phandle to Vdd regulator's node - vss-supply: phandle to Vss regulator's node And optional, checked only if the above corresponding, doesn't exist: - vdd-microvolts: positive reference Voltage [uV] - vss-microvolts: negative reference Voltage [uV] Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | dm: regulator: add function device_get_supply_regulator()Przemyslaw Marczak2015-11-02-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices are supplied by configurable regulator's output. But there was no function for getting it. This commit adds function, that allows for getting the supply device by it's phandle. The returned regulator device can be used with regulator uclass's API. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | dm: pmic: add s2mps11 PMIC I/O driverPrzemyslaw Marczak2015-11-02-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver allows I/O operations on the Samsung S2MPS11 PMIC, which provides lots of LDO/BUCK outputs. To enable it, update defconfig with: - CONFIG_PMIC_S2MPS11 and additional, if were not defined: - CONFIG_CMD_PMIC - CONFIG_ERRNO_STR The binding info: doc/device-tree-bindings/pmic/s2mps11.txt Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | Merge git://git.denx.de/u-boot-usbTom Rini2015-11-05-18/+22
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| * | | usb: udc: Fix warnings on 64-bit buildsMichal Simek2015-11-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cast u32 bit value to 64bit before recasting to 64bit pointer to avoid pointer from integer cast size mismatch warnings. Warning log: +../drivers/usb/gadget/udc/udc-core.c: In function ‘usb_gadget_unmap_request’: +../drivers/usb/gadget/udc/udc-core.c:68:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | usb: lthor: Specify correct parameter for sizeof typeMichal Simek2015-11-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes this warning: CC drivers/usb/gadget/f_thor.o drivers/usb/gadget/f_thor.c: In function ‘thor_tx_data’: drivers/usb/gadget/f_thor.c:572:2: warning: format ‘%d’ expects argument of type ‘int’, but argument 4 has type ‘long unsigned int’ [-Wformat=] debug("%s: dev->in_req->length:%d to_cpy:%d\n", __func__, ^ Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | usb: dwc3: Fix warnings on 64-bit buildsMichal Simek2015-11-03-15/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Change aritmentics to use 64bit types to be compatible with 64bit builds. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | dfu: dfu_sf: Pass duplicate devstr to parse_devVignesh R2015-11-03-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | parse_dev() alters the string pointed by devstr parameter. Due to this subsequent parsing of sf entities will fail, as string pointed by devstr is no longer valid sf dev arguments. Fix this by passing pointer to the copy of the string to parse_dev instead of pointer to the actual devstr. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | | ohci: Add missing cache-flush for hcca areaHans de Goede2015-11-03-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to cache-flush the hcca area after the initial memset, otherwise on the first hc_interrupt we might see an old $random value as done_head and try to interpret that as the address for a completed td (followed by chaos). Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | | Merge git://git.denx.de/u-boot-socfpgaTom Rini2015-11-05-13/+21
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| * | | spi: cadence_qspi: Ensure check for max frequency in placeChin Liang See2015-11-05-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure the intended SCLK frequency not exceeding the maximum frequency. If that happen, SCLK will set to maximum frequency. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * | | spi: cadence_qspi: Fix fdt read of spi-max-frequencyChin Liang See2015-11-05-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the fdt read for spi-max-frequency as it's contained in the child node. Current state of code is always returning default value. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * | | spi: cadence_qspi: Ensure spi_calibration is run when sclk changeChin Liang See2015-11-05-9/+14
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-11-04-1/+35
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| * | | rtc: Add MCP79411 support to DS1307 rtc driverAndy Fleming2015-11-04-1/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code is from Adrian Cox, and is patterned after similar support in Linux (drivers/rtc/rtc-ds1307.c:1121-1135). This chip is used on the Cyrus board from Varisys. Signed-off-by: Andy Fleming <afleming@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | arm: zynq: Move serial driver to driver modelSimon Glass2015-11-04-98/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update this driver to use driver model and change all users. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | arm: zynq: serial: Drop non-device-tree serial driver portionsSimon Glass2015-11-04-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we use device tree in SPL also, we can drop this code. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | arm: zynq: Support the debug UARTSimon Glass2015-11-04-16/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the debug UART to assist with early debugging. Enable it for Zybo as an example. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | dm: serial: Deal with stdout-path with an aliasSimon Glass2015-11-04-5/+25
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes stdout-path contains a UART alias along with speed, etc. For example: stdout-path = "serial0:115200n8"; Add support for decoding this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | mmc: atmel: Add atmel sdhci supportWenyou Yang2015-11-03-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SDHCI is introduced by sama5d2, named as Secure Digital Multimedia Card Controller(SDMMC). It supports the embedded MultiMedia Card (e.MMC) Specification V4.41, the SD Memory Card Specification V3.0, and the SDIO V3.0 specification. It is compliant with the SD Host Controller Standard V3.0 specification. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | mmc: sdhci: Fix the SD clock stop sequenceWenyou Yang2015-11-03-2/+18
|/ / | | | | | | | | | | | | | | | | | | | | | | According to the SDHC specification, stopping the SD Clock is by setting the SD Clock Enable bit in the Clock Control register at 0, instead of setting all bits at 0. Before stopping the SD clock, we need to make sure all SD transactions to complete, so add checking the CMD and DAT bits in the Presen State register, before stopping the SD clock. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
* | mmc: fsl_esdhc: enable EVDD automatic control for SD/MMC Legacy Adapter CardYangbo Lu2015-11-02-0/+3
| | | | | | | | | | | | | | | | | | When detecting SDHC Adapter Card Type 2(SD/MMC Legacy Adapter Card), enable EVDD automatic control via SDHC_VS. This could support SD card IO voltage switching for UHS-1 speed mode. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | mmc: fsl_esdhc: enable dat[4:7] for eMMC4.5 Adapter CardYangbo Lu2015-11-02-0/+3
| | | | | | | | | | | | | | | | If adapter card type identification is supported for platform, we would enable dat[4:7] for eMMC4.5 Adapter Card. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Powerpc: eSDHC: expand a fix to T4160Shaohui Xie2015-11-02-1/+2
| | | | | | | | | | | | | | | | commit b8e5b07225 "Powerpc: eSDHC: Fix mmc read write err in uboot of T4240QDS board", T4160 also needs this fix. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | lcd: atmel: Add 32bpp support for HLCDCMarek Vasut2015-11-01-0/+4
| | | | | | | | | | | | | | | | Add 32bpp framebuffer support for the Atmel HLCDC driver. This is needed for output bpp higher than 16bpp. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | mmc: atmel: Zap global 'initialized' variableMarek Vasut2015-11-01-4/+4
| | | | | | | | | | | | | | | | | | Global variables are bad. Get rid of this particular one, so we can correctly instantiate multiple atmel mci interfaces, without having them interfere with one another. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | mmc: atmel: Implement proper private dataMarek Vasut2015-11-01-15/+25
| | | | | | | | | | | | | | | | | | | | | | | | Instead of passing just the register area as a private data, introduce a proper struct atmel_mci_priv structure instead. This will become useful in the subsequent patch, where we eliminate the global variable from this driver. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> [fix free()] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | mmc: atmel: Fix clock configurationMarek Vasut2015-11-01-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | After silencing the prints which were generated when reconfiguring the clock of the SD/MMC bus, surprisingly, the driver stopped working such that every attempt to use the SD/MMC bus caused the CPU to get totally stuck hard. It turns out that the prints generated a short delay, which was necessary for the CPU to reconfigure the clock without getting stuck. Thus, this patch adds a short delay after the clock configuration instead. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | mmc: atmel: Silence debug outputMarek Vasut2015-11-01-6/+6
|/ | | | | | | | | | | | | This driver generates clearly debugging prints when changing clock speed, so silence those. Furthermore, the driver generates further prints in case a command fails to complete. The later case woud be useful, but for eMMC, command 8 can fail and it's not an error but a part of the specification. Thus, make this debug() as well. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> [fix checkpatch warnings] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-10-30-141/+402
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| * drivers/ddr/fsl_ddr: Make SR_IE configurableJoakim Tjernlund2015-10-30-1/+1
| | | | | | | | | | | | | | | | | | SR_IE(Self-refresh interrupt enable) is needed for Hardware Based Self-Refresh. Make it configurable and let board code handle the rest. Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardbYangbo Lu2015-10-29-6/+6
| | | | | | | | | | | | | | | | This patch adds esdhc support for ls1043ardb. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043a: Add Fman supportShaohui Xie2015-10-29-2/+128
| | | | | | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl_lsch3: Change arch to fsl-layerscapeMingkai Hu2015-10-29-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net/fm: Add QSGMII PCS initShaohui Xie2015-10-29-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | QSGMII PCS needed to be programmed same as SGMII PCS, and there are four ports in QSGMII PCS, port 0, 1, 2, 3, all the four ports shared port 0's MDIO controller, so when programming port 0, we continue to program other three ports. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net: Move some header files to include/Shaohui Xie2015-10-29-6/+6
| | | | | | | | | | | | | | | | | | | | The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net: fm: bug fix when CONFIG_PHYLIB not definedShaohui Xie2015-10-29-1/+7
| | | | | | | | | | | | | | | | codes related to phylib operations should be wrapped by CONFIG_PHYLIB. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net/fm: Make the return value logic consistent with conventionHou Zhiqiang2015-10-29-24/+36
| | | | | | | | | | | | | | | | | | | | In convention, the '0' is a normal return value indicating there isn't an error. While some functions of FMan IM driver treat '0' as an error return value. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net/fm: Add support for 64-bit platformsHou Zhiqiang2015-10-29-33/+60
| | | | | | | | | | | | | | | | | | | | | | | | The FMan IM driver is developed for 32-bit platfroms and isn't friendly to 64-bit platforms, so do the minimal refactor: 1. Refine the MURAM management and access. 2. Correct the initialization and operations for QDs and BDs. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net/fm: Fix the endian issue to support both endianness platformsHou Zhiqiang2015-10-29-38/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Frame Manager(FMan) is a big-endian peripheral, so the registers, internal MURAM and BDs, which are allocated in main memory and used to communication between core and FMan, should be accessed in big-endian. The big-endian platforms can access them directly as the code implemented so far, while for the little-endian platforms it need to swap the byte-order. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver: net: ldpaa_eth: Set MAC address during interface openPrabhakar Kushwaha2015-10-29-12/+3
| | | | | | | | | | | | | | | | | | | | Currently ldpaa ethernet driver rely on DPL file to statically configure mac address for the DPNIs. It is not a correct approach. Add support setting MAC address from env variable or Random MAC address. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * crypto/fsl: SEC driver cleanup for 64 bit and endiannessAneesh Bansal2015-10-29-20/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SEC driver code has been cleaned up to work for 64 bit physical addresses and systems where endianess of SEC block is different from the Core. Changes: 1. Descriptor created on Core is modified as per SEC block endianness before the job is submitted. 2. The read/write of physical addresses to Job Rings will be depend on endianness of SEC block as 32 bit low and high part of the 64 bit address will vary. 3. The 32 bit low and high part of the 64 bit address in descriptor will vary depending on endianness of SEC. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2015-10-29-33/+85
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