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| * ehci: mx7: fix otg id detectionPeng Fan2016-06-25-2/+5
| | | | | | | | | | | | | | | | | | | | The USBNC_PHYCFG2_ACAENB bit should be cleared to enable the OTG ID detection, not set it. When the bit is set, the ACA Resistance Detection is enabled, which disables the OTG ID detection, because the internal pull up is off. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * ehci: mx7: fix usbnc_regsPeng Fan2016-06-25-1/+2
| | | | | | | | | | | | | | | | There is a 4 bytes hole between phy_cfg2 and phy_status, fix the usbnc_regs structure to include the hole. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * usb: fsl: Fix NULL terminating issue for usb controller name stringRajesh Bhagat2016-06-25-1/+2
| | | | | | | | | | | | | | Fixes NULL terminating issue for usb controller name string by using sizeof operator. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-07-01-315/+530
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| * | pinctrl: uniphier: add Ethernet pin-mux settingsMasahiro Yamada2016-07-02-0/+94
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: avoid building unneeded pin-mux tables for SPLMasahiro Yamada2016-07-02-171/+192
| | | | | | | | | | | | | | | | | | | | | SPL does not use all of the devices, so we can save some memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: support pin configuration for dedicated pinsMasahiro Yamada2016-07-02-154/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration (pin biasing, drive strength control), but not pin-muxing. Allow to fill the mux value table with -1 for those pins; pins with mux value -1 will be skipped in the pin-mux set function. The mux value type should be changed from "unsigned" to "int" in order to accommodate -1 as a special case. [ Linux commit: 363c90e743b50a432a91a211dd8b078d9df446e9 ] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: split pinctrl driver for PH1-LD11 and PH1-LD20Masahiro Yamada2016-07-02-8/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PH1-LD11 and PH1-LD20 have much pin controlling in common, so I added a single driver shared between them in the initial commit. However, the Ethernet pin-mux settings I am going to add are different with each other, and they may diverge more as the progress of development. Split it into two dedicated drivers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: allow to have pinctrl node under syscon nodeMasahiro Yamada2016-07-02-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the UniPhier pinctrl driver itself is a syscon, but it turned out much more reasonable to make it a child node of a syscon because our syscon node consists of a bunch of system configuration registers, not only pinctrl, but also phy, and misc registers. It is difficult to split the node. This commit allows to migrate to the new DT structure. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: remove unneeded pin group nand_cs1Masahiro Yamada2016-06-30-3/+0
| | | | | | | | | | | | | | | | | | | | | This SoC does not support NAND CS1. This place-holder is no longer necessary. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: fix NAND pin-mux setting for PH1-LD11/LD20Masahiro Yamada2016-06-30-2/+2
| | | | | | | | | | | | | | | | | | My mistake in the initial support patch. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: remove wrong pin-mux functions for ProXstream2Masahiro Yamada2016-06-30-2/+0
| | | | | | | | | | | | | | | | | | These are pin group names, not function names. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | mmc: increase MMC SDHCI read status timeoutSteve Rae2016-07-01-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise, ocassionally see errors like this: Flashing sparse image at offset 2078720 Flashing Sparse Image sdhci_send_command: Timeout for status update! mmc fail to send stop cmd write_sparse_image: Write failed, block #2181088 [0] This does not affect the actual writing speed, which is controlled by the default value: CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT It only increases the retries when reading: SDHCI_INT_STATUS to avoid the timeout error. Signed-off-by: Steve Rae <steve.rae@raedomain.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | driver: qspi: correct QSPI disable CS reset valuePraneeth Bajjuri2016-07-01-1/+1
|/ / | | | | | | | | | | | | | | | | | | | | Correcting QSPI disable/unselect CS reset value. CTRL_CORE_CONTROL_IO_2: QSPI_MEMMAPPED_CS[10:8] This is not causing any issue, but its better to untouch the reserved bits. Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Ravi Babu <ravibabu@ti.com>
* | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-06-28-16/+56
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| * | armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCsPrabhakar Kushwaha2016-06-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs. like LS2080A, LS1043A, LS1012A. So append "A" to SoC names. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | mmc: fsl: introduce wp_enablePeng Fan2016-06-28-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introudce wp_enable. To check WPSPL, wp_enable needs to be set to 1 in board code. Take i.MX6UL for example, for some boards, they do not use WP singal, so they does not configure USDHC1_WP_SELECT_INPUT, and its default value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and SION bit set. So USDHC controller can always get wp signal and WPSPL shows write protect and blocks driver continuing. This is not what we want to see, so add wp_enable, and if set to 0, just omit the WPSPL checking and this does not effect normal working of usdhc controller. If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | fsl_esdhc: Update clock enable bits for USDHCYe Li2016-06-28-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USDHC moves the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN, HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec register. The driver uses RSTA to replace the clock gate off operation. But this is not a good solution because: 1. when using RSTA, we should wait this bit to clear by itself. This is not implemeneted in the code. 2. After RSTA is set, it is recommended that the Host Driver reset the external card and reinitialize it. So in this patch, we change to use the vendorspec registers for these bits operation. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | mmc: fsl: reset to normal boot mode when eMMC fast bootPeng Fan2016-06-28-9/+29
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting in eMMC fast boot, MMC host does not exit from boot mode after bootrom loading image. So the first command 'CMD0' sent in uboot will pull down the CMD line to low and cause errors. This patch cleans the MMC boot register in "mmc_init" to put the MMC host back to normal mode. Also clear DLL_CTRL delay line settings at USDHC initialization to eliminate the pre-settings from boot rom. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | fastboot: sparse: resync common/image-sparse.c (part 2)Steve Rae2016-06-27-12/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - update fastboot_okay() and fastboot_fail() This file originally came from upstream code. While retaining the storage abstraction feature, this is the second set of the changes required to resync with the cmd_flash_mmc_sparse_img() in the file aboot.c from https://us.codeaurora.org/cgit/quic/la/kernel/lk/plain/app/aboot/aboot.c?h=LE.BR.1.2.1 Signed-off-by: Steve Rae <srae@broadcom.com>
* | fastboot: sparse: remove session-id logicSteve Rae2016-06-27-14/+2
| | | | | | | | | | | | | | This "session-id" alogrithm is not required, and currently corrupts the stored image whenever more the one "session" is required. Signed-off-by: Steve Rae <srae@broadcom.com>
* | mmc: dw_mmc: fix the wrong AND operationJaehoon Chung2016-06-27-2/+2
| | | | | | | | | | | | | | | | | | | | These condition checking are wrong. Original Author's intention might be "&" instead of "&&". It can know whether receive or transmit data request with BIT[4]/BIT[5] of RINTSTS register. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | clk: sandbox: don't check clk ID against 0Stephen Warren2016-06-24-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | clk->id is unsigned, so it can't be < 0. Remove the check for that. FWIW, this issue was introduced when the clock API converted e.g. clk_get_rate()'s clock ID parameter from an int to an unsigned long (with a struct clk), without removing this check. Fixes: 135aa9500264 ("clk: convert API to match reset/mailbox style") Reported-by: Coverity Scan Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | mtd: nand: Drop a blank line in nand_wait()Andre Renaud2016-06-24-1/+0
|/ | | | | | | This empty line should not be there. Remove it. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* net: phy: marvell: Do not reset 88e1310 after autonegNathan Rossi2016-06-21-4/+1
| | | | | | | | | | | | | | | | | Commit a058052c "net: phy: do not read configuration register on reset", changes the behaviour of the phy_reset function such that the state of the BMCR register is not preserved during reset. Change the config function for the m88e1310 so that it does not do a reset after configuring auto-negotiation. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Stefan Roese <sr@denx.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Stefan Roese <sr@denx.de>
* net: phy: micrel: add support for KSZ886x switches in MIIM modeAlexey Firago2016-06-21-0/+26
| | | | | | | | | | | | | | | | | | | | | | | This patch adds a phy driver for the Micrel KSZ886x switches. Similarly to the KSZ8895, SoC MAC is directly connected to the switch MAC on the switch CPU port, so the link to the switch is always up. KSZ886x switches can be used in the following configuration modes: - Unmanaged mode with config stored in external EEPROM - Managed mode over SPI - Managed mode over I2C - Managed mode over mdio/mdc (aka MIIM or SMI) This patch supports only unmanaged and MIIM modes. Based on Micrel KSZ886x driver from Linux kernel and Micrel KSZ8895 driver from U-Boot. Verified with the KSZ8863MLL. Signed-off-by: Alexey Firago <alexey_firago@mentor.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: rtl8169: fix switching between adaptersStephen Warren2016-06-21-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | The rtl8169 driver uses a global variable to store the register address of the adapter being operated upon. This is updated to point at the correct adapter when sending or receiving a packet, or shutting down the adapter, but not when initializing the adapter. Consequently, switching between different adapters within the same U-Boot runtime does not work correctly since the driver programs the wrong registers during rtl8169_eth_start() -> rtl8169_common_start() -> rtl8169_hw_start(). Note that since rtl8169_eth_stop() does set the global variable, the second consecutive attempt to use the "new" adapter did work even before this patch, because each time network usage is shut down, the network core calls stop, which sets the variable so that the next start does actually initialize the hardware, and the adapter works. Equally, rtl8169_eth_probe() calls rtl_init() which sets the global, so if using only a single device, or if picking the "right" device (based on probe order) when multiple devices are present, ioaddr will already be set correctly from the get-go, so the issue does not occur. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge git://git.denx.de/u-boot-nand-flashTom Rini2016-06-20-180/+333
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| * mtd: nand: Patch remaining places where nand_to_mtd() should be usedBoris Brezillon2016-06-19-5/+5
| | | | | | | | | | | | | | Some drivers are still directly accessing the chip->mtd field. Patch them to use nand_to_mtd() instead. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * nand: nand torture: follow sync with linux v4.6Max Krummenacher2016-06-19-1/+1
| | | | | | | | | | | | follow parameter name change (nand to mtd) to fix compiler error. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
| * spl: nand: sunxi: add support for NAND config auto-detectionBoris Brezillon2016-06-19-58/+204
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NAND chips are supposed to expose their capabilities through advanced mechanisms like READID, ONFI or JEDEC parameter tables. While those methods are appropriate for the bootloader itself, it's way to complicated and takes too much space to fit in the SPL. Replace those mechanisms by a dumb 'trial and error' mechanism. With this new approach we can get rid of the fixed config list that was used in the sunxi NAND SPL driver. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * spl: nand: sunxi: split 'load page' and 'read page' logicBoris Brezillon2016-06-19-71/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split the 'load page' and 'read page' logic in 2 different functions so we can later load the page and test different ECC configs without the penalty of reloading the same page in the NAND cache. We also move common setup to a dedicated function (nand_apply_config()) to avoid rewriting the same values in NFC registers each time we read a page. These new functions are passed a pointer to an nfc_config struct to limit the number of parameters. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * spl: nand: sunxi: rework status polling loopBoris Brezillon2016-06-19-16/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | check_value_xxx() helpers are using a 1ms delay between each test, which can be quite long for some operations (like a page read on an SLC NAND). Since we don't have anything to do but to poll this register, reduce the delay between each test to 1us. While we're at it, rename the max_number_of_retries parameters and the MAX_RETRIES macro into timeout_us and DEFAULT_TIMEOUT_US to reflect that we're actually waiting a given amount of time and not only a number of retries. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * spl: nand: sunxi: stop guessing the redundant u-boot offsetBoris Brezillon2016-06-19-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | Use CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND value instead of trying to guess where the redundant u-boot image is based on simple (and most of the time erroneous) heuristics. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com> # Conflicts: # drivers/mtd/nand/sunxi_nand_spl.c
| * spl: nand: support redundant u-boot imageBoris Brezillon2016-06-19-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On modern NAND it's more than recommended to have a backup copy of the u-boot binary to recover from corruption: bitflips are quite common on MLC NANDs, and the read-disturbance will corrupt your u-boot partitition more quickly than what you would see on an SLC NAND. Add an extra Kconfig option to specify the offset of the redundant u-boot image. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com> [scottwood: added ifdef to fix build break] Signed-off-by: Scott Wood <oss@buserror.net>
| * spl: nand: rework SYS_NAND_U_BOOT_OFFS Kconfig option dependencyBoris Brezillon2016-06-19-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | The SYS_NAND_U_BOOT_OFFS is quite generic, but the Kconfig entry is forced to explicitly depend on platforms that are not already defining it in their include/configs/<board>.h header. Add the SYS_NAND_U_BOOT_LOCATIONS option, make the SYS_NAND_U_BOOT_OFFS depends on it, remove the dependency on NAND_SUNXI and make it dependent on SPL selection. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * spl: nand: sunxi: remove support for so-called 'syndrome' modeBoris Brezillon2016-06-19-42/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sunxi SPL NAND controller driver supports use 'BootROM'-like configs, that is, configs where the ECC bytes and real data are interleaved in the page instead of putting ECC bytes in the OOB area. Doing that has several drawbacks: - since you're interleaving data and ECC bytes you can't use the whole page otherwise you might override the bad block marker with non-FF bytes. - to solve the bad block marker problem, the ROM code supports partially using the page, but this introduces a huge penalty both in term of read speed and NAND memory usage. While this is fine for rather small binaries(like the SPL one which is at maximum 24KB large), it becomes non-negligible for the bootloader image (several hundred of KB). - auto-detection of the page size is not reliable (this is in my opinion the biggest problem). If you get the page size wrong, you'll end up reading data at a different offset than what was specified by the caller and the reading may succeed (if valid data were written at this address). For all those reasons I think it's wiser to completely remove support for 'syndrome' configs. If we ever need to support it again, then I'd recommend specifying all the config parameters through Kconfig options. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* | mmc: add MMC_VERSION_5_1Stefan Wahren2016-06-20-0/+3
| | | | | | | | Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
* | clk: convert API to match reset/mailbox styleStephen Warren2016-06-19-388/+462
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | reset: implement a reset testStephen Warren2016-06-19-0/+173
| | | | | | | | | | | | | | | | | | This adds a sandbox reset implementation (provider), a test client device, instantiates them both from Sandbox's DT, and adds a DM test that excercises everything. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Add a reset driver framework/uclassStephen Warren2016-06-19-0/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A reset controller is a hardware module that controls reset signals that affect other hardware modules or chips. This patch defines a standard API that connects reset clients (i.e. the drivers for devices affected by reset signals) to drivers for reset controllers/providers. Initially, DT is the only supported method for connecting the two. The DT binding specification (reset.txt) was taken from Linux kernel v4.5's Documentation/devicetree/bindings/reset/reset.txt. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | mailbox: add Tegra186 HSP driverStephen Warren2016-06-19-0/+171
| | | | | | | | | | | | | | | | | | | | Tegra186's HSP module implements doorbells, mailboxes, semaphores, and shared interrupts. This patch provides a driver for HSP, and hooks it into the mailbox API. Currently, only doorbells are supported. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* | mailbox: rename headersStephen Warren2016-06-19-4/+4
| | | | | | | | | | | | | | | | Rename mailbox*.h to match the naming convention requested during review of the new reset subsystem. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | gpio: pca953x: Fix register reading past 8th GPIOmario.six@gdsys.cc2016-06-19-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | A bug in the pca953x driver prevents correct reading of GPIO input values beyond the 8th GPIO; all values are reported as zero. Setting of GPIO output values is not affected. This patch fixes the reading behavior. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Peng Fan <van.freenix@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | dm: add manual relocation for devicesAngelo Dureghello2016-06-19-0/+15
| | | | | | | | | | | | | | | | Some architectures as m68k still need to use CONFIG_NEEDS_MANUAL_RELOC, and are not still using the device tree. Signed-off-by: Angelo Dureghello <angelo@sysam.it> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-06-18-39/+299
|\ \ | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
| * | usb: ehci: only shutdown opened controllerPeng Fan2016-06-18-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the usb controller is not running, no need to shutdown it, otherwise `usb stop` complains about: "EHCI failed to shut down host controller". To i.MX7D SDB, there are two usb ports, one Host, one OTG. If we only plug one udisk to the Host port and then `usb start`, the OTG controller for OTG port does not run actually. Then, if `usb stop`, the OTG controller for OTG port will also be shutdown, but it is not running. This patch adds a check to only shutdown the running controller. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: "Stefan Brüns" <stefan.bruens@rwth-aachen.de> Cc: Stephen Warren <swarren@nvidia.com>
| * | usb: xhci: fsl: Add workaround for USB erratum A008751Sriram Dash2016-06-13-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is doing the following: 1. Implementing the errata for LS2080. 2. Adding fixup for fdt for LS2080. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * | fsl: usb: make errata function common for PPC and ARMSriram Dash2016-06-13-2/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following things: 1. Makes the errata checking code common for PPC and ARM 2. Moves all these static inline functions into a dedicated C file Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * | usb: xhci: fsl: code cleanup for device tree fixup for fsl usb controllersSriram Dash2016-06-13-38/+56
| | | | | | | | | | | | | | | | | | | | | | | | Performs code cleanup for device tree fixup for fsl usb controllers by making functions to handle these similar errata checking code. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
generated by cgit v1.1 at 2024-11-19 11:51:48 +0000