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* power: regulator: add pwm regulatorKever Yang2016-10-01-0/+170
| | | | | | | | add driver support for pwm regulator. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-09-30-54/+277
|\ | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/dra7xx_evm.h
| * drivers: usb: xhci-fsl: Implement Erratum A-010151 for FSL USB3 controllerSriram Dash2016-09-27-0/+39
| | | | | | | | | | | | | | | | | | | | | | Currently the controller by default enables the Receive Detect feature in P3 mode in USB 3.0 PHY. However, USB 3.0 PHY does not reliably support receive detection in P3 mode. Enabling the USB3 controller to configure USB in P2 mode whenever the Receive Detect feature is required. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * usb: fsl: Renaming fdt_fixup_erratum and fdt_fixup_usb_erratumSriram Dash2016-09-27-22/+23
| | | | | | | | | | | | | | | | The functions fdt_fixup_erratum and fdt_fixup_usb_erratum are fsl/nxp specific. So, make them explicit by renaming them fsl_fdt_fixup_erratum and fsl_fdt_fixup_usb_erratum Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
| * usb: fsl: Rename fdt_fixup_dr_usbSriram Dash2016-09-27-1/+1
| | | | | | | | | | | | | | | | The function fdt_fixup_dr_usb is specific to fsl/nxp. So, make the function name explicit and rename fdt_fixup_dr_usb into fsl_fdt_fixup_dr_usb. Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
| * usb: host: ehci-vf: Migrate Vybrid USB to driver modelSanchayan Maity2016-09-27-7/+201
| | | | | | | | | | | | Add driver model support for Vybrid USB driver. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
| * drivers: usb: xhci-fsl: Change burst beat and outstanding pipelined ↵Sriram Dash2016-09-27-0/+10
| | | | | | | | | | | | | | | | | | | | | | transfers requests This is required for better performance, and performs below tuning: 1. Enable burst length set, and define it as 4/8/16. 2. Set burst request limit to 16 requests. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
| * net: asix: Fix ASIX 88772B with driver modelAlban Bedel2016-09-27-24/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 147271209a9d ("net: asix: fix operation without eeprom") added a special handling for ASIX 88772B that enable another type of header. This break the driver in DM mode as the extra handling needed in the receive path is missing. However this new header mode is not required and only seems to increase the code complexity, so this patch revert this part of commit 147271209a9d. This also reverts commit 41d1258aceb45b45f9e68f67a9c40f0afbc09dc9 ("net: asix: Fix AX88772B when used with DriverModel") of late. Fixes: 147271209a9d ("net: asix: fix operation without eeprom") Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
* | mpc85xx: powerpc: usb: Update the list of Socs afftected by erratum A006261Sriram Dash2016-09-28-9/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apply the erratum A006261 for the following Socs: P2041 rev 2.0, P2040 rev 2.0, P5040 rev 2.0, 2.1 Do not apply erratum A006261 for the following Socs: T4160, T4080, T1040, T1042, T1020, T1022, T2080, T2081 Erratum A006261 is applicable for the following Socs: P1010(1.0, 2.0), P2041(1.0, 1.1, 2.0, 2.1), P2040(1.0, 1.1, 2.0, 2.1), P3041(1.0, 1.1, 2.0, 2.1), P5010(1.0, 2.0), P5020(1.0, 2.0), P5021(1.0, 2.0), T4240(1.0, 2.0), P5040(1.0,2.0,2.1). Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-09-27-382/+488
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| * | ARM: tegra: fix USB ULPI PHY reset signal inversion confusionStephen Warren2016-09-27-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB ULPI PHY reset signals are typically active low. Consequently, they should be marked as GPIO_ACTIVE_LOW in device tree, and indeed they are in the Linux kernel DTs, and in DT properties that U-Boot doesn't yet use. However, in DT properties that U-Boot does use, the value has been set to 0 (== GPIO_ACTIVE_HIGH) to work around a bug in U-Boot. This change fixes the DT to correctly represent the HW, and fixes the Tegra USB driver to cope with the fact that dm_gpio_set_value() internally handles any inversions implied by the DT value GPIO_ACTIVE_LOW. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | i2c: tegra: only use new clock/reset APIsStephen Warren2016-09-27-57/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the standard clock/reset APIs are available for all Tegra SoCs, convert the I2C driver to use them exclusively, and remove any references to the custom Tegra-specific APIs. Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | mmc: tegra: only use new clock/reset APIsStephen Warren2016-09-27-40/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the standard clock/reset APIs are available for all Tegra SoCs, convert the MMC driver to use them exclusively, and remove any references to the custom Tegra-specific APIs. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | clock: implement a driver for the Tegra CARStephen Warren2016-09-27-0/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a clock uclass driver for the Tegra CAR. This allows clients to use standard clock APIs on Tegra. This device is intended to be instantiated by the core Tegra CAR driver, rather than being instantiated directly from DT. The implementation uses the existing custom Tegra- specific clock APIs to avoid coupling the series with significant refactoring of the existing Tegra clock/clock code. The driver currently only supports peripheral clocks, and avoids support for other clocks such as PLLs and external clocks. This should be sufficient to convert over all Tegra peripheral drivers, and avoids a complex implementation which calls different Tegra-specific clock APIs based on the type of clock being manipulated. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | reset: implement a driver for the Tegra CARStephen Warren2016-09-27-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a reset uclass driver for the Tegra CAR. This allows clients to use standard reset APIs on Tegra. This device is intended to be instantiated by the core Tegra CAR driver, rather than being instantiated directly from DT. The implementation uses the existing custom Tegra- specific reset APIs to avoid coupling the series with significant refactoring of the existing Tegra clock/reset code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | misc: implement Tegra CAR core driverStephen Warren2016-09-27-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra CAR (Clock And Reset) module provides control of most clocks and reset signals within the Tegra SoC. This change implements a driver for this module. However, since the module implements multiple kinds of services (clocks, resets, perhaps more), all this driver does is bind various sub-devices, which in turn provide the real services. This driver is essentially an "MFD" (Multi-Function Device) in Linux kernel speak. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | mmc: tegra: Add DM_MMC support to Tegra MMC driverTom Warren2016-09-27-208/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the Tegra MMC driver to DM_MMC. Support for non-DM is removed to avoid ifdefs in the code. DM_MMC is now enabled for all Tegra builds. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Warren <twarren@nvidia.com> (swarren, fixed some NULL pointer dereferences, removed extraneous changes, rebased on various other changes, removed non-DM support etc.) Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | mmc: tegra: priv struct and naming cleanupStephen Warren2016-09-27-138/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | struct mmc_host is a Tegra-specific structure, but the name implies it's something defined by core MMC code, which is confusing. Rename it to struct tegra_mmc_priv to make its purpose more obvious. The new name is also more appropriate for a DM driver private data structure, which will be relevant later in this series. Nothing needs access to this type except the MMC driver itself. Move the definition into the driver C file. Make sure all Tegra MMC functions are named tegra_mmc_*. Even though they're all static, it's useful to have good naming so that symbol tables are easy to interpret. A few functions aren't renamed by this patch since they'll be deleted by a subsequent patch in this series. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | mmc: tegra: don't use periph_id in pad_init_mmc()Stephen Warren2016-09-27-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MMC driver will soon be converted to use standard clock/reset APIs, and so the periph_id field in the MMC device priv struct will disappear. Rework the implementation of pad_init_mmc() to rely on this; using the device register address is a much more direct test anyway. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | mmc: tegra: move pad_init_mmc() into MMC driverStephen Warren2016-09-27-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pad_init_mmc() is performing an SoC-specific operation, using registers within the MMC controller. There's no reason to implement this code outside the MMC driver, so move it inside the driver. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | mmc: tegra: use correct alias for SDHCI/MMC nodesStephen Warren2016-09-27-5/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra MMC driver currently honors "sdhci" entries in /aliases. The MMC core however uses "mmc" entries in /aliases. This difference will be relevant once the Tegra MMC driver is converted to DM, and the MMC core handles alias lookups. To avoid issues during that conversion, fix the Tegra MMC driver and all Tegra DTs to use the same alias name as the MMC core does. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-09-27-16/+4691
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| * | ahci: Make ahci_port_base() non-static to enable overwriteStefan Roese2016-09-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To allow a board- / platform-specific ahci_port_base() function, this patch removes "static inline" and adds __weak to this function. This will be used by the upcoming Armada 7K/8K SATA / AHCI support, which unfortunately needs a different port base address calculation. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
| * | usb: xhci-mvebu: Add Armada 8K to compatiblity listStefan Roese2016-09-27-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To enable this driver on Armada 7K/8K this patch adds the compatibility property to the list. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
| * | drivers/phy: Add Marvell SerDes / PHY drivers used on Armada 7K/8KStefan Roese2016-09-27-2/+1904
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This version is based on the Marvell U-Boot version with this patch applied as latest patch: Git ID 7f408573: "fix: comphy: cp110: add comphy initialization for usb device mode" from 2016-07-05. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
| * | drivers/phy: Add Marvell SerDes / PHY drivers used on Armada 3kStefan Roese2016-09-27-0/+2092
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This version is based on the Marvell U-Boot version with this patch applied as latest patch: Git ID 7f408573: "fix: comphy: cp110: add comphy initialization for usb device mode" from 2016-07-05. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
| * | usb: ehci: ehci-marvell.c: Add Armada 3700 support (ARMv8)Stefan Roese2016-09-27-7/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds DM based support for the Armada 3700 EHCI controller. The address windows don't need to get configured in this case. The difference here is detected via DT compatible property at runtime. With this support and the DM xHCI driver, both XHCI and eHCI can be used simultaniously on the MVEBU boards now. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com> Acked-by: Marek Vasut <marex@denx.de>
| * | usb: xhci: Add Marvell MVEBU xHCI supportStefan Roese2016-09-27-0/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds DM based support for the xHCI USB 3.0 controller integrated in the Armada 3700 SoC. It may be extended to be used by other MVEBU SoCs as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com> Acked-by: Marek Vasut <marex@denx.de>
| * | net: mvneta: Add support for Armada 3700 SoCStefan Roese2016-09-27-1/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the Armada 3700 SoC to the Marvell mvneta network driver. Not like A380, in Armada3700, there are two layers of decode windows for GBE: First layer is: GbE Address window that resides inside the GBE unit, Second layer is: Fabric address window which is located in the NIC400 (South Fabric). To simplify the address decode configuration for Armada3700, we bypass the first layer of GBE decode window by setting the first window to 4GB. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: mvneta: Make driver 64bit safeStefan Roese2016-09-27-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mvneta driver is also used on the ARMv8 64bit Armada 3700 SoC. This patch fixes the compilation warnings seen on this 64bit platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | spi: Add driver for Marvell Armada 3700 SoCStefan Roese2016-09-27-0/+303
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPI IP core in the Marvell Armada 3700 is similar to the one in the other Armada SoCs. But the differences are big enough that it makes sense to introduce a new driver instead of cluttering the old kirkwood driver with #ifdef's. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | serial: Add serial_mvebu_a3700 for Armada 3700 SoCStefan Roese2016-09-27-0/+191
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Armada 3700's UART is a simple serial port. It has a 32 bytes Tx FIFO and a 64 bytes Rx FIFO integrated. This patch adds support for this UART including the DEBUG UART functions for very early debug output. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
| * | net: mvneta: Round up top tx buffer boundaries for dcache opsStefan Roese2016-09-27-1/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | check_cache_range() warns that the top boundaries are not properly aligned when flushing or invalidating the buffers and make these operations fail. This gets rid of the warnings: CACHE: Misaligned operation at range ... Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | dfu: Migrate to KconfigTom Rini2016-09-27-0/+28
| | | | | | | | | | | | | | | | | | | | | | Introduce a hidden USB_FUNCTION_DFU Kconfig option and select it for CMD_DFU (as we must have the DFU command enabled to do anything DFU). Make all of the entries in drivers/dfu/Kconfig depend on CMD_DFU and add options for all of the back end choices that DFU can make use of. Cc: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com>
* | usb:gadget: Disallow DFU in SPL for nowTom Rini2016-09-27-0/+2
|/ | | | | | | | | | Previously, DFU was not built in for SPL and often disabled via the board config.h file, in the SPL build. By moving DFU to Kconfig we now need to move this logic to the Makefile to continue to allow boards to fit within their SPL size limit (until gcc 6 is more widespread and unused strings will be discarded). Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-09-26-292/+224
|\ | | | | | | | | | | | | trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * driver: ddr: fsl_mmdc: Pass board parameters through data structureYork Sun2016-09-26-19/+19
| | | | | | | | | | | | | | | | | | Instead of using multiple macros, a data structure is used to pass board-specific parameters to MMDC DDR driver. Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * armv8: ls1046a: Convert CONFIG_LS1046A to Kconfig option ARCH_LS1046AYork Sun2016-09-26-1/+1
| | | | | | | | | | | | | | | | | | Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Mingkai Hu <mingkai.hu@nxp.com> CC: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * ddr: fsl: fix a compile issueShaohui Xie2016-09-14-1/+6
| | | | | | | | | | | | | | | | | | | | When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that temp32 undeclared, this patch fixes it. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012aShengzhou Liu2016-09-14-0/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: Remove debug server supportYork Sun2016-09-14-251/+0
| | | | | | | | | | | | Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Revise workaround A008511 for A009803York Sun2016-09-14-36/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR controller 5.2.1 has this erratum A008511 partially fixed. The workaround needs to be adjusted to take advantage of Vref training. This patch enables the training and force output enable to be off. Erratum A009803 requires the controller to be idel before enabling address parity. It was combined with workaround for A008511. With new A008511 flow, this flow needs to be changed to enabling data init (D_INIT) after the address parity is enabled. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
| * driver/ddr/fsl: Add more debug registersYork Sun2016-09-14-3/+3
| | | | | | | | | | | | | | 32 more debug registers are added for newer DDR controllers. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
| * net: fm: fix spi flash probe for using driver modelQianyu Gong2016-09-14-0/+10
| | | | | | | | | | | | | | | | | | | | | | The current code would always use the speed and mode set by CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. But if using SPI driver model it should get the values from DT. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | kconfig: introduce kconfig for UBIHeiko Schocher2016-09-26-0/+100
| | | | | | | | | | | | | | | | | | move the UBI config options into Kconfig. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andrew F. Davis <afd@ti.com> Reviewed by: Evgeni Dobrev <evgeni at studio-punkt.com>
* | i2c: mvtwsi.c: Add support for Marvell Armada 7K/8KStefan Roese2016-09-26-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By adding the "marvell,mv78230-i2c" compatible property, we can enable this I2C driver to support these new ARM64 chips as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Heiko Schocher <hs@denx.de>
* | i2c: mv_i2c.c: Validate read length in I2C commandjinghua2016-09-26-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The I2C bus will get stuck when reading 0 byte. So we add validation of the read length in i2c_read(). This issue only occurs on read operation. Signed-off-by: jinghua <jinghua@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Heiko Schocher <hs@denx.de>
* | i2c: mv_i2c.c: Enable runtime speed selection (standard vs fast mode)Stefan Roese2016-09-26-7/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds runtime speed configuration to the mv_i2c driver. Currently standard (max 100kHz) and fast mode (max 400kHz) are supported. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Heiko Schocher <hs@denx.de>
* | i2c: mv_i2c.c: Add DM supportStefan Roese2016-09-26-48/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Heiko Schocher <hs@denx.de>
* | i2c: mv_i2c.c: Prepare driver for DM conversionStefan Roese2016-09-26-126/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To prepare for the DM conversion, we add a layer of compatibility functions to be used by both the legacy and the DM functions. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Heiko Schocher <hs@denx.de>
generated by cgit v1.1 at 2024-11-02 07:32:46 +0000