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* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-09-24-2/+10
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| * mtd: nand: mxs check maximum ecc that platfrom supportsPeng Fan2015-09-20-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | Check maximum ecc strength for each platfrom to avoid the calculated ecc exceed the limitation. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Han Xu <b45815@freescale.com> Tested-By: Tim Harvey <tharvey at gateworks.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: wdog: correct wcr register settingsPeng Fan2015-09-20-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | We should not simple use "writew(WCR_WDE, &wdog->wcr)" to set wcr, since this will override bits set before reset_cpu. Use clrsetbits_le16 instead of writew to fix this issue. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Sebastian Siewior <bigeasy@linutronix.de> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2015-09-24-0/+1142
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| * | ARM: uniphier: rename CONFIG_MACH_* to CONFIG_ARCH_UNIPHIER_*Masahiro Yamada2015-09-25-6/+6
| | | | | | | | | | | | | | | | | | | | | I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify they belong to UniPhier SoC family. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: add UniPhier PH1-LD6b pinctrl driverMasahiro Yamada2015-09-25-0/+140
| | | | | | | | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD6b SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: add UniPhier ProXstream2 pinctrl driverMasahiro Yamada2015-09-25-0/+147
| | | | | | | | | | | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier ProXstream2 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: add UniPhier PH1-Pro5 pinctrl driverMasahiro Yamada2015-09-25-0/+151
| | | | | | | | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier PH1-Pro5 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: add UniPhier PH1-sLD8 pinctrl driverMasahiro Yamada2015-09-25-0/+148
| | | | | | | | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier PH1-sLD8 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: add UniPhier PH1-Pro4 pinctrl driverMasahiro Yamada2015-09-25-0/+137
| | | | | | | | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier PH1-Pro4 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: add UniPhier PH1-LD4 pinctrl driverMasahiro Yamada2015-09-25-0/+141
| | | | | | | | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD4 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: add UniPhier pinctrl core supportMasahiro Yamada2015-09-23-0/+278
| | | | | | | | | | | | | | | | | | | | | The core support for the pinctrl drivers for all the UniPhier SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-09-22-234/+1998
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| * | drivers/net/vsc9953: Add GPL-2.0+ SPDX-License-IdentifierCodrin Ciubotariu2015-09-21-1/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Add commands for VLAN ingress filteringCodrin Ciubotariu2015-09-21-0/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The command: ethsw [port <port_no>] ingress filtering { [help] | show | enable | disable } - enable/disable VLAN ingress filtering on port can be used to enable/disable/show VLAN ingress filtering on a port. This command has also been added to the ethsw generic parser from common/cmd_ethsw.c Signed-off-by: Johnson Leung <johnson.leung@freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Add command for shared/private VLAN learningCodrin Ciubotariu2015-09-21-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The command: ethsw vlan fdb { [help] | show | shared | private } - make VLAN learning shared or private" configures the FDB to share the FDB entries learned on multiple VLANs or to keep them separated. By default, the FBD uses private VLAN learning. This command has also been added to the ethsw generic parser from common/cmd_ethsw.c Signed-off-by: Johnson Leung <johnson.leung@freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Add VLAN commands for VSC9953Codrin Ciubotariu2015-09-21-0/+478
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new added commands can be used to configure VLANs for a port on both ingress and egress. The new commands are: ethsw [port <port_no>] pvid { [help] | show | <pvid> } - set/show PVID (ingress and egress VLAN tagging) for a port; ethsw [port <port_no>] vlan { [help] | show | add <vid> | del <vid> } - add a VLAN to a port (VLAN members); ethsw [port <port_no>] untagged { [help] | show | all | none | pvid } - set egress tagging mod for a port" ethsw [port <port_no>] egress tag { [help] | show | pvid | classified } - Configure VID source for egress tag. Tag's VID could be the frame's classified VID or the PVID of the port These commands have also been added to the ethsw generic parser from common/cmd_ethsw.c Signed-off-by: Johnson Leung <johnson.leung@freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Add commands to manipulate the FDB for VSC9953Codrin Ciubotariu2015-09-21-0/+472
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new command: ethsw [port <port_no>] [vlan <vid>] fdb { [help] | show | flush | { add | del } <mac> } Can be used to add and delete FDB entries. Also, the command can be used to show entries from the FDB tables. When used with [port <port_no>] and [vlan <vid>], only the matching the FDB entries can be seen or flushed. The command has also been added to the generic ethsw parser from cmd_ethsw.c. Signed-off-by: Johnson Leung <johnson.leung@freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Add commands to enable/disable HW learningCodrin Ciubotariu2015-09-21-0/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The command: ethsw [port <port_no>] learning { [help] | show | auto | disable } can be used to enable/disable HW learning on a port. This patch also adds this command to the generic ethsw parser from cmd_ethsw. Signed-off-by: Johnson Leung <johnson.leung@freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Add command to show/clear port countersCodrin Ciubotariu2015-09-21-0/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new added command: ethsw [port <port_no>] statistics { [help] | [clear] } will print counters like the number of Rx/Tx frames, number of Rx/Tx bytes, number of Rx/Tx unicast frames, etc. This patch also adds this commnd in the genereric ethsw parser from cmd_ethsw.c Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Use the generic Ethernet Switch parserCodrin Ciubotariu2015-09-21-184/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch replaces the parser used by VSC9953 L2 Switch driver with the generic one. Also, the config macro that enables the VSC9953 commands has been replaced in all the platforms that use this driver with the config macro that corresponds to the generic parser. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Add default configuration for VSC9953 L2 SwitchCodrin Ciubotariu2015-09-21-0/+253
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At startup, the default configuration should be: - enable HW learning on all ports (HW default); - all ports are VLAN aware; - all ports are members of VLAN 1; - all ports have Port-based VLAN 1; - on all ports, the switch is allowed to remove maximum one VLAN tag, - on egress, the switch should add a VLAN tag if the frame is classified to a different VLAN than the port's Port-based VLAN; Signed-off-by: Johnson Leung <johnson.leung@freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Fix bug when enabling a portCodrin Ciubotariu2015-09-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a port is enabled at init time, the initializing function touches more bits than necessary to enable a port (also touches reserved bits and default bit values). This patch fixes this issue by changing the value of the define used to enable the port and assures that no other bits are changes by replacing out_le32() with setbits_le32(). Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Cleanup patchCodrin Ciubotariu2015-09-21-71/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch groups some macros defined for registers and replaces some magic numbers from vsc9953 with macros. Also, "port" and "port_nr" words are replaced with "port_no", puts each variable declaration on a line and removes unnecessary tabs. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers/net/vsc9953: Remove 'CONFIG_' from macros' nameCodrin Ciubotariu2015-09-21-19/+19
| |/ | | | | | | | | | | Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | pinctrl: move dm_scan_fdt_node() out of pinctrl uclassMasahiro Yamada2015-09-19-6/+17
|/ | | | | | | | | | | | | | | | | | | | | Commit c5acf4a2b3c6 ("pinctrl: Add the concept of peripheral IDs") added some additional change that was not mentioned in the git-log. That commit added dm_scan_fdt_node() in the pinctrl uclass binding. It should be handled by the simple-bus driver or the low-level driver, not by the pinctrl framework. I guess Simon's motivation was to bind GPIO banks located under the Rockchip pinctrl device. It is true some chips have sub-devices under their pinctrl devices, but it is basically SoC-specific matter. This commit partly reverts commit c5acf4a2b3c6 to keep the only pinctrl-generic features in the uclass. The dm_scan_fdt_node() should be called from the rk3288_pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* net: designware: Add support to PCI designware devicesBin Meng2015-09-16-0/+42
| | | | | | | | The Designware ethernet controller is also seen on PCI bus, e.g. on Intel Quark SoC. Add this support in the DM version driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Add an inline API to test if a device is on a PCI busBin Meng2015-09-16-2/+2
| | | | | | | | Introduce device_is_on_pci_bus() which can be utilized by driver to test if a device is on a PCI bus. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-fdtTom Rini2015-09-16-1/+4
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| * fdt: add new fdt address parsing functionsStephen Warren2015-09-15-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fdtdec_get_addr_size() hard-codes the number of cells used to represent an address or size in DT. This is incorrect in many cases depending on the DT binding for a particular node or property (e.g. it is incorrect for the "reg" property). In most cases, DT parsing code must use the properties #address-cells and #size-cells to parse addres properties. This change splits up the implementation of fdtdec_get_addr_size() so that the core logic can be used for both hard-coded and non-hard-coded cases. Various wrapper functions are implemented that support cases where hard-coded cell counts should or should not be used, and where the client does and doesn't know the parent node ID that contains the properties #address-cells and #size-cells. dev_get_addr() is updated to use the new functions. Core functionality in fdtdec_get_addr_size_fixed() is widely tested via fdtdec_get_addr_size(). I tested fdtdec_get_addr_size_auto_noparent() and dev_get_addr() by manually modifying the Tegra I2C driver to invoke them. Much of the core implementation of fdtdec_get_addr_size_fixed(), fdtdec_get_addr_size_auto_parent(), and fdtdec_get_addr_size_auto_noparent() comes from Thierry Reding's previous commit "fdt: Fix fdtdec_get_addr_size() for 64-bit". Based-on-work-by: Thierry Reding <treding@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Simon Glass <sjg@chromium.org> Cc: Michal Suchanek <hramrach@gmail.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Dropped #define DEBUG at the top of fdtdec.c: Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove unused ST-Ericsson u8500 archStefan Roese2015-09-15-803/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This arch does not seem to be supported / used at all in the current U-Boot mainline source tree any more. So lets remove the core u8500 code and code that was only referenced by this platform. Please note that this patch also removes these config options: - CONFIG_PL011_SERIAL_RLCR - CONFIG_PL011_SERIAL_FLUSH_ON_INIT As they only seem to be referenced by u8500 based boards. Without any such board in the current code, these config option don't make sense any more. Lets remove them as well. If someone still wants to use this platform, then please send patches to re-enable support by adding at least one board that references this code. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: John Rigby <john.rigby@linaro.org> Cc: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Tom Rini <trini@konsulko.com> Cc: Heiko Schocher <hs@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | mtd: nand: fsmc: Fixes and cleanup for fsmc_nand_switch_ecc()Stefan Roese2015-09-15-6/+15
|/ | | | | | | | | | | | | | | | | | | This patch addresses some comments raised by Scott in the last versions. Here the changes in detail: - Removed __maybe_unused as its not needed - Added check for strength == 4 and error out for the unsupported ECC strength values - Don't set .caclulate, .correct, and .bytes for NAND_ECC_SOFT_BCH as this will be done in nand_scan_tail() - Set .caclulate back to fsmc_read_hwecc() in the HW case - Added comment that this function will only be called on SPEAr platforms, not supporting the BCH8 HW ECC (FSMC_VER8) Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Cc: Tom Rini <trini@konsulko.com> Acked-by: Scott Wood <scottwood@freescale.com>
* Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2015-09-13-10/+36
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| * serial: serial-sh: SCIFA interface for R-Car Gen2 SoCsVladimir Barinov2015-08-31-9/+34
| | | | | | | | | | | | | | | | | | Add SCIFA console interface for R-Car Gen2 SoCs. SCIFA has different registers offsets and sizes then SCI. Hence it needs to put it's macro definitions separately. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * gpio: sh-pfc: fix gpio input readVladimir Barinov2015-08-31-1/+2
| | | | | | | | | | | | | | | | Fix gpio_read: gpio input (INDT) and gpio output (OUTDT) registers have different offset. gpio_read must be performed from INDT. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | pcie_imx: Use 'ms' for millisecondsFabio Estevam2015-09-13-3/+3
| | | | | | | | | | | | | | milliseconds should be written as 'ms' instead of 'mS'. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Marek Vasut <marex@denx.de>
* | thermal: imx_thermal: Do not print on errorFabio Estevam2015-09-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is not very useful to have the message below on every boot (especially when we are using early silicon): U-Boot 2015.10-rc2-23945-g37cf215 (Sep 08 2015 - 14:12:14 -0300) CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0 - invalid sensor device , so turn the error message into debug level. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | imx: imx7d: add imx-common cpu support for imx7dAdrian Alonso2015-09-13-1/+1
| | | | | | | | | | | | | | | | | | Add imx-common cpu support for imx7d SoC - Update reset_cause for imx7d - Enable watchdog driver built for imx7d Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | thermal: imx: add imx7d soc thermal supportAdrian Alonso2015-09-13-6/+84
| | | | | | | | | | | | Add imx7 SoC thermal driver support Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | thermal: imx_thermal: rework driver to be reusedAdrian Alonso2015-09-13-8/+12
| | | | | | | | | | | | | | | | Rework imx_thermal driver to be used across i.MX processor that support thermal sensor Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | usb: ci_udc: fix emissions of ZLPsStephen Warren2015-09-12-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 6a132416359e "ci_udc: Update the ci_udc driver to support bulk transfers" caused the value of "len" to change without updating subsquent users of that variable in ci_ep_submit_next_request(). This caused the code that detects when to emit ZLPs (Zero Length Packets) never to trigger, which in turn caused host timeouts when a ZLP was required, which in turn broke tests/dfu/, even despite the assertion in that commit's description that "These changes are tested for both the DFU and lthor." Fix this by modifying the added dtd iteration code not to modify "len", but rather to keep state in a separate variable. Rename the variables while we're at it so they describe their purpose better. Fixes: 6a132416359e ("ci_udc: Update the ci_udc driver to support bulk transfers") Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | usb: gadget: ci_udc: implement usb_ep_ops dequeue callbackPeng Fan2015-09-12-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement endpoint dequeue callback function. Without this function, uboot will hang when executing fastboot comamnd. See following flow: "fastboot_tx_write_str->fastboot_tx_write->usb_ep_dequeue->ep->ops->dequeue" without implement ci_udc dequeue function, ep->ops->dequeue is NULL, then uboot will hang. Tested on mx6qsabresd board with fastboot enabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Cc: "Łukasz Majewski" <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | gpio: lpc32xx: fix issues with port3 gpioSylvain Lemieux2015-09-11-6/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current simplify lpc32xx gpio driver implementation assume a maximum of 32 GPIO per port; there are a total of 22 GPI, 24 GPO and 6 GPIO to managed on port 3. Update the driver to fix the following: 1) When requesting GPI_xx and GPO_xx on port 3 (xx is the same number) the second call to "gpio_request" will return -EBUSY. 2) The status of GPO_xx pin report the status of the corresponding GPI_xx pin when using the "gpio status" command. 3) The gpio driver may setup the direction register for the wrong gpio when calling "gpio_direction_input" (GPI_xx) or "gpio_direction_output" (GPO_xx) on port 3; the call to the direction is require to use the "gpio status" command. The following change were done in the driver: 1) port3 GPI are cache in a separate 32 bits in the array. 2) port3 direction register written only for GPIO pins. 3) port3 GPO & GPIO (as output) are read using "p3_outp_state". 4) LPC32XX_GPI_P3_GRP updated to match the change. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* | bitops: introduce BIT() definitionHeiko Schocher2015-09-11-9/+0
| | | | | | | | | | | | | | | | | | | | | | introduce BIT() definition, used in at91_udc gadget driver. Signed-off-by: Heiko Schocher <hs@denx.de> [remove all other occurrences of BIT(x) definition] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
* | dfu: mmc: buffer file reads tooStephen Warren2015-09-11-12/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When writing to files in a filesystem on MMC, dfu_mmc.c buffers up the entire file content until the end of the transaction, at which point the file is written in one go. This allows writing files larger than the USB transfer size (CONFIG_SYS_DFU_DATA_BUF_SIZE); the maximum written file size is CONFIG_SYS_DFU_MAX_FILE_SIZE (the size of the temporary buffer). The current file reading code does not do any buffering, and so limits the maximum read file size to the USB transfer size. Enhance the code to do the same kind of buffering as the write path, so the same file size limits apply. Remove the size checking code from dfu_read() since all read paths now support larger files than the USB transfer buffer. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com>
* | dfu: don't keep freeing/reallocatingStephen Warren2015-09-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DFU currently allocates buffer memory at the start of each data transfer operation and frees it at the end. Especially since memalign() is used to allocate the buffer, and various other allocations happen during the transfer, this can expose the code to heap fragmentation, which prevents the allocation from succeeding on subsequent transfers. Fix the code to allocate the buffer once when DFU mode is initialized, and free the buffer once when DFU mode is exited, to reduce the exposure to heap fragmentation. The failure mode is: // Internally to memalign(), this allocates a lot more than s to guarantee // that alignment can occur, then returns chunks of memory at the start/ // end of the allocated buffer to the heap. p = memalign(a, s); // Various other malloc()s occur here, some of which allocate the RAM // immediately before/after "p". // // DFU transfer is complete, so buffer is released. free(p); // By chance, no other malloc()/free() here, in DFU at least. // // A new DFU transfer starts, so the buffer is allocated again. // In theory this should succeed since we just free()d a buffer of the // same size. However, this fails because memalign() internally attempts // to allocate much more than "s", yet free(p) above only free()d a // little more than "s". p = memalign(a, s); Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com>
* | usb: gadget: don't leak configs when unbindingStephen Warren2015-09-11-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By the time g_dnl_unbind() is run, cdev->config has been set to NULL, so the free() there does nothing, and the config struct is leaked. Equally, struct usb_gadget contains a linked list of config structs, so the code should iterate over them all and free each one, rather than freeing one particular config struct. composite_unbind() already iterates over the list of config structs, and unlinks each from the linked list. Fix this loop to free() each struct as it's unlinked and otherwise forgotten. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com>
* | Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h headerSimon Glass2015-09-11-0/+20
| | | | | | | | | | | | | | Now that we have a new header file for cache-aligned allocation, we should move the stack-based allocation macro there also. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Move malloc_cache_aligned() to its own headerSimon Glass2015-09-11-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present malloc.h is included everywhere since it recently was added to common.h in this commit: 4519668 mtd/nand/ubi: assortment of alignment fixes This seems wasteful and unnecessary. We have been trying to trim down common.h and put separate functions into separate header files and that change goes in the opposite direction. Move malloc_cache_aligned() to a new header so that this can be avoided. The header would perhaps be better named as alignmem.h but it needs to be included after common.h and people might be confused by this. With the name memalign.h it fits nicely after malloc() in most cases. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
* | mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600Stefan Roese2015-09-11-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can be used by boards equipped with a NAND chip that requires 4-bit ECC strength. The SPEAr600 HW ECC only supports 1-bit ECC strength. To enable SW BCH4, you need to specify this in your config header: #define CONFIG_NAND_ECC_BCH #define CONFIG_BCH And use the command "nandecc bch4" to select this ECC scheme upon runtime. Tested on SPEAr600 x600 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
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