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* | | | dm: serial: Put common code into separate functionsSimon Glass2014-10-22-15/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid duplicating the code which deals with getc() and putc(). It is fairly simple, but may expand later. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | dm: exynos: cros_ec: Move cros_ec_spi to driver modelSimon Glass2014-10-22-9/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust this driver to use driver model and move smdk5420 boards over to use it. Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | dm: sandbox: cros_ec: Move sandbox cros_ec to driver moduleSimon Glass2014-10-22-5/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust the sandbox cros_ec emulation driver to work with driver model, and switch over to driver model for sandbox cros_ec. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | | dm: cros_ec: Add support for driver modelSimon Glass2014-10-22-14/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for driver model if enabled. This involves minimal changes to the code, mostly just plumbing around the edges. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | | dm: tegra: spi: Convert to driver modelSimon Glass2014-10-22-534/+392
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This converts the Tegra SPI drivers to use driver model. This is tested on: - Tegra20 - trimslice - Tegra30 - beaver - Tegra124 - dalmore (not tested on Tegra124) Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | dm: sf: sandbox: Convert SPI flash driver to driver modelSimon Glass2014-10-22-47/+291
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert sandbox's spi flash emulation driver to use driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | | dm: Convert spi_flash_probe() and 'sf probe' to use driver modelSimon Glass2014-10-22-2/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want the SPI flash probing feature to operate as a standard driver. Add a driver for the basic probing feature used by most boards. This will be activated by device_probe() as with any other driver. The 'sf probe' command currently keeps track of the SPI slave that it last used. This doesn't work with driver model, since some other driver or system may have probed the device and have access to it too. On the other hand, if we try to probe a device twice the second probe is a nop with driver model. Fix this by searching for the matching device, removing it, and then probing it again. This should work as expected regardless of other device activity. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | | dm: sf: Add a uclass for SPI flashSimon Glass2014-10-22-1/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver model uclass for SPI flash which supports the common operations (read, write, erase). Since we must keep support for the non-dm interface, some modification of the spi_flash header is required. CONFIG_DM_SPI_FLASH is used to enable driver model for SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | | spi: Use error return value in sf_opsSimon Glass2014-10-22-33/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust spi_flash_probe_slave() to return an error value instead of a pointer so we get the correct error return. Have the caller allocate memory for spi_flash to simplify error handling, and also so that driver model can use its existing allocated memory. Add a spi.h include in the sf_params file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | | sf: Tidy up public and private header filesSimon Glass2014-10-22-7/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since spi_flash.h is supposed to be the public API for SPI flash, move private things to sf_internal.h. Also tidy up a few comment nits. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | | dm: exynos: Convert SPI to driver modelSimon Glass2014-10-22-333/+180
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the exynos SPI driver over to driver model. This removes quite a bit of boilerplate from the driver, although it adds some for driver model. A few device tree additions are needed to make the SPI flash available. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | | dm: spi: Add soft_spi implementationSimon Glass2014-10-22-0/+253
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new implementation of soft_spi that uses device tree to specify the GPIOs. This will replace soft_spi_legacy for boards which use driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | | dm: spi: Remove SPI_INIT featureSimon Glass2014-10-22-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This feature provides for init of a single SPI port for the soft SPI feature. It is not really compatible with driver model since it assumes a single SPI port. Also, inserting SPI init into the driver by means of a #define is not very nice. This feature is not used by any active boards, so let's remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | | dm: spi: Rename soft_spi.c to soft_spi_legacy.cSimon Glass2014-10-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reserve the 'normal' name for use by driver model, and rename the old driver so that it is clear that it is for 'legacy' drivers only. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | | dm: sandbox: spi: Move to driver modelSimon Glass2014-10-22-126/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust the sandbox SPI driver to support driver model and move sandbox over to driver model for SPI. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | | dm: Add spi.h header to a few filesSimon Glass2014-10-22-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some files are using SPI functions but not explitly including the SPI header file. Fix this, since driver model needs it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | | dm: sandbox: Add a SPI emulation uclassSimon Glass2014-10-22-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot includes a SPI emulation driver already but it is not explicit, and is hidden in the SPI flash code. Conceptually with sandbox's SPI implementation we have a layer which creates SPI bus transitions and a layer which interprets them, currently only for SPI flash. The latter is actually an emulation, and it should be possible to add more than one emulation - not just SPI flash. Add a SPI emulation uclass so that other emulations can be plugged in to support different types of emulated devices on difference buses/chip selects. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | | dm: spi: Add a uclass for SPISimon Glass2014-10-22-0/+394
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a uclass which provides access to SPI buses and includes operations required by SPI. For a time driver model will need to co-exist with the legacy SPI interface so some parts of the header file are changed depending on which is in use. The exports are adjusted also since some functions are not available with driver model. Boards must define CONFIG_DM_SPI to use driver model for SPI. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> (Discussed some follow-up comments which will address in future add-ons)
* | | | dm: core: Allow parents to pass data to children during probeSimon Glass2014-10-22-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Buses sometimes want to pass data to their children when they are probed. For example, a SPI bus may want to tell the slave device about the chip select it is connected to. Add a new function to permit the parent data to be supplied to the child. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | | dm: core: Add functions for iterating through device childrenSimon Glass2014-10-22-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Buses need to iterate through their children in some situations. Add a few functions to make this easy. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | | dm: exynos: Move serial to driver modelSimon Glass2014-10-22-183/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the Exynos serial driver to work with driver model and switch over all relevant boards to use it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | dm: exynos: gpio: Convert to driver modelSimon Glass2014-10-22-136/+288
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the exynos GPIO driver to driver model. This implements the generic GPIO interface but not the extra Exynos-specific functions. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | dm: exynos: Make sure that GPIOs are requestedSimon Glass2014-10-22-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With driver model GPIOs must be requested before use. Make sure this is done correctly. (Note that the soft SPI part of universal is omitted, since this driver is about to be replaced with a driver-model-aware version) Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | dm: exynos: Tidy up GPIO definesSimon Glass2014-10-22-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The defines at the top of the GPIO driver use single-character names for parameters which are not very descriptive. Improve these to use descriptive parameter names. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | dm: exynos: Tidy up GPIO headersSimon Glass2014-10-22-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The wrong header is being included, thus requiring the code to re-declare the generic GPIO interface in each GPIO header. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | dm: simplify the loop in lists_driver_lookup_name()Masahiro Yamada2014-10-22-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | if (strncmp(name, entry->name, len)) continue; /* Full match */ if (len == strlen(entry->name)) return entry; is equivalent to: if (!strcmp(name, entry->name)) return entry; The latter is simpler. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* | | | dm: do not check the existence of uclass operationMasahiro Yamada2014-10-22-4/+0
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function uclass_add() checks uc_drv->ops as follows: if (uc_drv->ops) { dm_warn("No ops for uclass id %d\n", id); return -EINVAL; } It seems odd because it warns "No ops" when uc_drv->ops has non-NULL pointer. (Looks opposite.) Anyway, most of UCLASS_DRIVER entries have no .ops member. This check makes no sense. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-10-20-0/+2051
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| * | | crypto/fsl: Add command for encapsulating/decapsulating blobsRuchika Gupta2014-10-16-1/+279
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's SEC block has built-in Blob Protocol which provides a method for protecting user-defined data across system power cycles. SEC block protects data in a data structure called a Blob, which provides both confidentiality and integrity protection. Encapsulating data as a blob Each time that the Blob Protocol is used to protect data, a different randomly generated key is used to encrypt the data. This random key is itself encrypted using a key which is derived from SoC's non volatile secret key and a 16 bit Key identifier. The resulting encrypted key along with encrypted data is called a blob. The non volatile secure key is available for use only during secure boot. During decapsulation, the reverse process is performed to get back the original data. Commands added -------------- blob enc - encapsulating data as a cryptgraphic blob blob dec - decapsulating cryptgraphic blob to get the data Commands Syntax --------------- blob enc src dst len km Encapsulate and create blob of data $len bytes long at address $src and store the result at address $dst. $km is the 16 byte key modifier is also required for generation/use as key for cryptographic operation. Key modifier should be 16 byte long. blob dec src dst len km Decapsulate the blob of data at address $src and store result of $len byte at addr $dst. $km is the 16 byte key modifier is also required for generation/use as key for cryptographic operation. Key modifier should be 16 byte long. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | fsl_sec: Add hardware accelerated SHA256 and SHA1Ruchika Gupta2014-10-16-0/+1773
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | video: ipu_disp: remove pixclk fixupJeroen Hofstee2014-10-16-25/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ipu display insists on having a lower_margin smaller then 2. If this is not the case it will attempt to force it and adjust the pixclk accordingly. This multiplies pixclk in Hz with the width and height, since this is typically a * 10^7 * b * 10^2 * c * 10^2 this will overflow the uint_32 and make things even worse. Since this is a bootloader and the adjustment is neglectible, just force it to two and warn about it. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | | video: ipu: fix debug and commentJeroen Hofstee2014-10-16-5/+4
|/ / | | | | | | | | | | | | | | - fix debug pixel clk display and add unit - fix some comments Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | sunxi: axp152: dcdc3 scale is 50mV / step not 25mV / stepHans de Goede2014-10-13-1/+1
| | | | | | | | | | | | | | | | | | | | Currently uboot wrongly uses 25mV / step for dcdc3, this is a copy and paste error introduced when adding the axp152_mvolt_to_target during review of the axp152.c driver. This results in u-boot setting Vddr to 2.3V instead of 1.5V. This commit fixes this. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-10-10-22/+971
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| * Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-10-11-289/+654
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| * | macb: simplify gmac initialisationAndreas Bießmann2014-10-10-17/+8
| | | | | | | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Bo Shen <voice.shen@atmel.com>
| * | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-10-10-3/+220
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| | * | samsung: Enable device tree for s5p_goniSimon Glass2014-10-08-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change this board to add a device tree. This also adds a pinmux header file although it is not used as yet. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | cros_ec: exynos: Use the correct tps65090 driver in each caseSimon Glass2014-10-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos 5250 boards (snow, spring) use the I2C driver but Exynos 5420 boards cannot due to a hardware design decision. Select the correct driver to use in each case. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | cros_ec: power: Add a tunnelled version of the tps65090 driverSimon Glass2014-10-08-0/+219
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately on Pit the AP has no direct access to the tps65090 but must talk through the EC (over SPI) to the EC's I2C bus. When driver model supports PMICs this will be relatively easy. In the meantime the best approach is to duplicate the driver. It will be refactored once driver model support is expanded. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD2014-10-08-2/+743
| |\ \ \ | | |/ / | |/| | | | | | | | | | | | | | | | | | The single file conflict below is actually trivial. Conflicts: board/boundary/nitrogen6x/nitrogen6x.c
| | * | usb: ehci-mx6: Rename the USB register base addressYe.Li2014-09-29-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mx6sl/mx6sx has 2 OTG and 1 host. So they have name "USBO2H_USB_BASE_ADDR" in imx-regs.h. The driver hard codes the USB base address name to "USBOH3", which causes the driver failed to build for mx6sl/mx6sx. This patch uniform the address name to "USB_BASE_ADDR" for all mx6 series. Signed-off-by: Ye.Li <B37916@freescale.com>
| | * | usb: ehci: mxs: Add board-specific callbacksMarek Vasut2014-09-29-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add board-specific callbacks for enabling/disabling port power into the MXS EHCI controller driver. This is in-line with the names of callbacks on other systems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| | * | Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-09-22-181/+1390
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| | * | | mtd: nand: add Freescale vf610_nfc driverStefan Agner2014-09-16-0/+725
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds initial support for Freescale NFC (NAND Flash Controller) found in ARM Vybrid SoC's, Power Architecture MPC5125 and others. The driver is called vf610_nfc since this is the first supported and tested hardware platform supported by the driver. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
* | | | | serial-uclass: Fix compilation errorHans de Goede2014-10-10-1/+1
| |_|_|/ |/| | | | | | | | | | | Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2014-10-10-2/+10
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| * | | | mtd: denali: support NAND_CMD_RNDOUT commandMasahiro Yamada2014-10-09-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function nand_flash_detect_ext_param_page() requires NAND_CMD_RNDOUT command supported. It is necessary to detect some types of ONFi-compliant devices. Without it, the error message "unsupported command received 0x5" is shown. Let's support this command on the Denali NAND controller driver. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Chin Liang See <clsee@altera.com>
| * | | | mtd: denali: fix NAND_CMD_PARAM commandMasahiro Yamada2014-10-09-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NAND_CMD_PARAM (0xEC) command is not working on the Denali NAND controller driver. Unlike NAND_CMD_READID (0x90), when the NAND_CMD_PARAM command is followed by an address cycle, the target device goes busy. (R/B# is deasserted) Wait until the parameter data are ready. In addition, unnecessary clear_interrupts() should be removed. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Chin Liang See <clsee@altera.com>
* | | | | ahci: Don't start command DMA engine before buffers are setRoger Quadros2014-10-10-1/+0
|/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DMA/FIS buffers are set in ahci_port_start() which is called after ahci_host_init(). So don't start the DMA engine here (i.e. don't set FIS_RX) This fixes the following error at kernel boot on OMAP platforms (e.g. DRA7x) WARNING: CPU: 0 PID: 0 at drivers/bus/omap_l3_noc.c:147 l3_interrupt_handler+0x260/0x358() 44000000.ocp:L3 Custom Error: MASTER SATA TARGET GPMC (Idle): Data Access in User mode during Functional access Signed-off-by: Roger Quadros <rogerq@ti.com>
generated by cgit v1.1 at 2024-11-19 11:45:32 +0000