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* usb: dwc3: remove pm related operations from dwc3 driverKishon Vijay Abraham I2015-04-14-223/+5
| | | | | | | | Removed all pm related operations including pm_runtime APIs, suspend/resume hooks as support for these are not present in u-boot. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* usb: dwc3: fix dwc3 header filesKishon Vijay Abraham I2015-04-14-14/+3
| | | | | | | | | Changed the header files included in core.h and io.h to the u-boot header files so that these files can be included in other dwc3 source files and be compiled in uboot. Also added otg.h which has the defines for dr_mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* usb: dwc3: remove trace_* APIs from dwc3 driverKishon Vijay Abraham I2015-04-14-80/+29
| | | | | | | | Removed most of the trace_* APIs from dwc3 driver since tracepoints are not supported in u-boot. Replaced some of the trace_* API with dev_dbg/dev/vdbg. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Review-by: Lukasz Majewski <l.majewski@samsung.com>
* usb: dwc3: Modify the file headers to u-boot formatKishon Vijay Abraham I2015-04-14-58/+45
| | | | | | | | | Modified the file header to the format that is used in u-boot. Also included in the header, the commit in linux kernel from which each of these files are added. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* usb: dwc3: remove un-used files from dwc3 folderKishon Vijay Abraham I2015-04-14-2741/+0
| | | | | | | | removed un-used/un-supported files from dwc3. These files can be added later as and when the support is added. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* usb: dwc3: add dwc3 folder from linux kernel to u-bootKishon Vijay Abraham I2015-04-14-0/+9679
| | | | | | | | | Added dwc3 folder from linux kernel 3.19-rc1 (97bf6af1f9) to u-boot. This will be adapted to work with u-boot in the following patches. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* usb: gadget: udc: make udc-core compile in u-boot buildKishon Vijay Abraham I2015-04-14-309/+26
| | | | | | | | | | Make udc-core compile in u-boot by removing all linux specific stuff and having only the bare minimal udc-core required for usb gadget drivers. Also modified the file header to a format that is generally being used in u-boot. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* usb: gadget: udc: add udc-core from linux kernel to u-bootKishon Vijay Abraham I2015-04-14-0/+641
| | | | | | | | | | | | | | Added udc-core.c from linux kernel 3.19-rc1 (97bf6af1f9) to u-boot. This will be adapted to work with u-boot in the following patches. Adding support for udc will help to seamlessly port dwc3 driver from linux kernel to u-boot (since dwc3 uses udc-core) and it'll also help to add support for multiple gadget controllers to be functional at the same time. All other gadget drivers can also be adapted to use udc-core. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* usb: dwc2: retry NAK'd interrupt transfersStephen Warren2015-04-14-6/+19
| | | | | | | | | | | | | | | | | IIUC, interrupt transfers are NAK'd by devices until they wish to trigger an interrupt, and e.g. EHCI controllers retry these in HW until they are ACK'd. However, DWC2 doesn't seem to retry, so we need to do this in SW. In practice, I've seen DWC2_HCINT_FRMOVRUN happen too. I'm not quite sure what this error implies; perhaps it's related to how near the end of a USB frame we're at when the interrupt transfer is initiated? Anyway, retrying this temporary error seems to be necessary too. With all these commits applied, both my USB keyboards (one LS Lenovo and one FS Dell) work correctly when there is no USB hub between the SoC and the keyboard; We still need split transactions to be implemented for hubs to work. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* usb: dwc2: implement interrupt transfersStephen Warren2015-04-14-3/+2
| | | | | | | | | | | | | | | | | | | | | | As best I can tell, there's no difference between bulk and interrupt transfers in terms of how the HW should be programmed, at least given that we're executing one transaction at a time rather than scheduling them into frames for maximum throughput. This patch ends up sharing the toggle bit state between bulk and interrupt transfers on a particular EP. However I believe this is fine; AFAIK a given EP either uses bulk or interrupt transfers and doesn't mix them. This patch doesn't do anything with the "interval" parameter for interrupt transfers, but then most other USB controller drivers in U-Boot don't either. It turns out that one of my keyboards is happy to work using control transfers but the other only gives non-zero "HID reports" via interrupt transfers. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* usb: dwc2: correctly program hcchar for LS devicesStephen Warren2015-04-14-9/+12
| | | | | | | | A bit must be set in HCCHAR when communicating with low-speed devices. I have no idea why there's no corresponding bit to distinguish between full-speed and high-speed devices, but no matter; they all work now! Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* usb: dwc2: detect device speed correctlyStephen Warren2015-04-14-1/+8
| | | | | | | This doesn't make my LS keyboard work any better, but it does at least report the correct speed in "usb tree". Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* usb: dwc2: use phys_to_bus/bus_to_physStephen Warren2015-04-14-1/+3
| | | | | | | Use of these APIs is required on the Raspberry Pi. With this change, USB on RPi1 should be more reliable, and USB on the RPi2 will start working. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* Create API to map between CPU physical and bus addressesStephen Warren2015-04-14-0/+8
| | | | | | | | | | | | | On some SoCs, DMA-capable peripherals see a different address space to the CPU's physical address space. Create an API to allow platform-agnostic drivers to convert between the two address spaces when programming DMA operations. This API will exist on all platforms, but will have a dummy implementation when this feature is not required. Other platforms will enable CONFIG_PHYS_TO_BUS and provide the required implementation. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* usb: dwc2: fix bulk transfersStephen Warren2015-04-14-9/+13
| | | | | | | | | | | | | | | | When I created wait_for_chhltd(), I noticed that some instances of the code it replaced expected the ACK bit to be set and others didn't. I assumed this was an accidental inconsistency in the code, so wrote wait_for_chhltd() to always expect ACK to be set. This code appeared to work correctly for both enumeration of USB keyboards and operation of USB Ethernet devices. However, this change broke USB Mass Storage (at least my USB SD card reader). This change reverts to exactly the original behaviour. I'm not sure why the ACK bit isn't always set (perhaps a quirk in the USB HW or DWC2 controller), but the code works this way! Fixes: 5be4ca7d6ac8 ("usb: dwc2: unify waiting for transfer completion") Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* usb: dwc2: remove restriction on buffer lengthStephen Warren2015-04-14-9/+3
| | | | | | | | | | Each USB transfer is split up into chunks that are held in an aligned buffer. This imposes a limit on the size of each chunk, but no limit on the total size of transferred data. Fix the logic in chunk_msg() not to reject large transfers, but simply take the size of the aligned buffer into account when calculating the chunk size. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* usb: dwc2: fix aligned buffer usageStephen Warren2015-04-14-6/+8
| | | | | | | | | | | | | | | The original aligned_buffer usage: a) Uselessly copied data into the aligned buffer even for IN transactions. Fix this my making the copy conditional. b) Always programmed the HW to transfer to/from the start of the aligned buffer. This worked fine for OUT transactions since the memcpy copied the OUT data to this location too. However, for large IN transactions, since the copy from the aligned buffer to the "client" buffer was deferred until after all chunks were transferred. it resulted in each chunk's transfer over-writing the data for the first transfer. Fix this by copying IN data as soon as it's received. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* usb: dwc2: simplify wait_for_chhltdStephen Warren2015-04-14-4/+2
| | | | | | | toggle is never NULL. Simplify the code by removing handling of when it is NULL. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* usb: dwc2: remove control_data_toggle[]Stephen Warren2015-04-14-8/+4
| | | | | | | | The control data toggle resets to DATA1 at the start of the data phase of every setup transaction. We don't need a global variable to store the value; we can just store it on the stack. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* usb: dwc2: usb chunk_msg() for control transfers tooStephen Warren2015-04-14-95/+19
| | | | | | This removes duplicated code. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* usb: dwc2: refactor submit_bulk_msg to be commonStephen Warren2015-04-14-16/+39
| | | | | | | | Move the body of submit_bulk_msg() into new function chunk_msg(). This can be shared with submit_control_msg() to reduce code duplication, and allow control messages larger than maxpacket. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* usb: dwc2: unify waiting for transfer completionStephen Warren2015-04-14-107/+60
| | | | | | Lift common code out of submit_bulk_msg() and submit_control_msg(). Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* usb: 64-bit architectures support for xHCISergey Temerkhanov2015-04-14-32/+41
| | | | | | | | | This commit allows xHCI to use both 64 and 32 bit memory physical addresses depending on architecture it's being built for. Also it makes use of readq()/writeq() on 64-bit systems Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
* usb: mass-storage: Build warning fixes for 64-bitThierry Reding2015-04-14-1/+1
| | | | | | | | | | | Fix a printf format mismatch warning seen on 64-bit builds. Cc: Łukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* usb: ehci-tegra: Build warning fixes for 64-bitThierry Reding2015-04-14-4/+4
| | | | | | | | | Cast pointers to unsigned long instead of a sized 32-bit type to avoid pointer to integer cast size mismatch warnings. Cc: Tom Warren <twarren@nvidia.com> Cc: Marek Vasut <marex@denx.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
* ehci-hcd: fix warnings on 64-bit buildsRob Herring2015-04-14-41/+41
| | | | | | | | Change addresses to unsigned long to be compatible with 64-bit builds. Regardless of fixing warnings, the device is still only 32-bit capable. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Marek Vasut <marex@denx.de>
* usb: ci_udc: fix warnings on 64-bit buildsRob Herring2015-04-14-21/+21
| | | | | | | | | | Change addresses to unsigned long to be compatible with 64-bit builds. Regardless of fixing warnings, the device is still only 32-bit capable. Signed-off-by: Rob Herring <robh@kernel.org> Cc: "Łukasz Majewski" <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* usb: eth: asix: Build warning fixes for 64-bitThierry Reding2015-04-14-1/+1
| | | | | | | Fix a type mismatch in a printf format string. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
* dtt: add ds620 supportAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+66
| | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* lpc32xx: add LPC32xx SSP support (SPI mode)Albert ARIBAUD \(3ADEV\)2015-04-10-0/+145
| | | | | Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* lpc32xx: add GPIO supportAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+301
| | | | | | This driver only supports Driver Model, not legacy model. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* lpc32xx: i2c: add LPC32xx I2C interface supportAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+250
| | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* lpc32xx: mtd: nand: add MLC NAND controllerAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+765
| | | | | | | | | | The controller's Reed-Solomon ECC hardware is used except of course for raw reads and writes. It covers in- and out-of-band data together. The SPL framework is supported. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* lpc32xx: add Ethernet supportAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+638
| | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* ahci: Fix a wrong parameter passTang Yuantian2015-04-07-1/+1
| | | | | | | | | | | | In stead of user_buffer_size, transfer_size should be used to pass to ahci_device_data_io(). transfer_size is the length that we want the low level function to transfer each time. If we use user_buffer_size which is the totally data length as parameter, low level function will actually create many SGs to transfer as many data as possible each time. That will produce many redundant data transfer. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* video: parade: configure SLP and RST GPIOs if specified in DTAjay Kumar2015-04-06-0/+11
| | | | | | | | | | Add support to configure EDP_RST GPIO and EDP_SLP GPIO, if provided in parade DT node. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* video: exynos_fb: configure backlight GPIOs if specified in DTAjay Kumar2015-04-06-0/+21
| | | | | | | | | | Add support to configure PWM_OUT(PWM output) GPIO and BL_EN(backlight enable) GPIO, if provided in FIMD DT node. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* serial-arc: switch to DMAlexey Brodkin2015-04-03-32/+70
| | | | | | | | Now when all infrastructure in ARC is ready for it let's switch ARC UART to driver model. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org>
* serial/serial_arc: set registers address during compilationAlexey Brodkin2015-04-03-2/+1
| | | | | | | | | | Being global variable with 0 value it falls into .bss area which we may only use after relocation to RAM. And right afetr relocation we zero .bss - effectively cleaing register address set for early console. Now with pre-set value "regs" variable is no longer in .bss and this way safely survives relocation. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-03-31-0/+6
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| * ARM: at91: atmel_nand: Support flash based BBTDavid Dueck2015-04-01-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for on-flash bad block table. This makes U-Boot handle an existing BBT correctly. Signed-off-by: David Dueck <davidcdueck@googlemail.com> Reviewed-by: Boris BREZILLON <boris.brezillon@free-electrons.com> CC: Boris BREZILLON <boris.brezillon@free-electrons.com> CC: Josh Wu <josh.wu@atmel.com> CC: Andreas Bießmann <andreas.devel@googlemail.com> CC: Scott Wood <scottwood@freescale.com> Acked-by: Josh Wu <josh.wu@atmel.com>
* | Merge git://git.denx.de/u-boot-nand-flashTom Rini2015-03-31-318/+120
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| * | mtd: vf610_nfc: specify transfer size before each transferStefan Agner2015-03-30-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Testing showed, that commands like STATUS made the buffer dirty when executed with NFC_SECSZ set to the page size. It looks like the controller transfers bogus data when this register is configured. When setting it to 0, the buffer does not get altered while the status command still seems to work flawless. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * | mtd: vf610_nfc: mark page as dirty on block eraseStefan Agner2015-03-30-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver tries to re-use the page buffer by storing the page number of the current page in the buffer. The page is only read if the requested page number is not currently in the buffer. When a block is erased, the page number is marked as invalid if the erased page equals the one currently in the cache. However, since a erase block consists of multiple pages, also other page numbers could be affected. The commands to reproduce this issue (on a written page): > nand dump 0x800 > nand erase 0x0 0x20000 > nand dump 0x800 The second nand dump command returns the data from the buffer, while in fact the page is erased (0xff). Avoid the hassle to calculate whether the page is affected or not, but set the page buffer unconditionally to invalid instead. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * | nand: yaffs: Remove the "nand write.yaffs" commandPeter Tyser2015-03-30-65/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This command is only enabled by one board, complicates the NAND code, and doesn't appear to have been functioning properly for several years. If there are no bad blocks in the NAND region being written nand_write_skip_bad() will take the shortcut of calling nand_write() which bypasses the special yaffs handling. This causes invalid YAFFS data to be written. See http://lists.denx.de/pipermail/u-boot/2011-September/102830.html for an example and a potential workaround. U-Boot still retains the ability to mount and access YAFFS partitions via CONFIG_YAFFS2. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * | nand: Remove CONFIG_MTD_NAND_VERIFY_WRITEPeter Tyser2015-03-30-248/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_MTD_NAND_VERIFY_WRITE has been removed from Linux for some time and a more generic method of NAND verification now exists in U-Boot. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
| * | dfu: nand: Verify writesPeter Tyser2015-03-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously NAND writes were not verified and could fail silently. Add a verification step after all writes to NAND. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
| * | nand: Add verification functionsPeter Tyser2015-03-30-1/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add nand_verify() and nand_verify_page_oob(). nand_verify() verifies NAND contents against an arbitrarily sized buffer using ECC while nand_verify_page_oob() verifies a NAND page's contents and OOB. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
| * | mtd: nand: mxs: fix PIO_WORDs in mxs_nand_write_buf()Luca Ellero2015-03-30-1/+1
| | | | | | | | | | | | | | | | | | There is only one pio_word in this DMA transaction so data field must be 1. Signed-off-by: Luca Ellero <luca.ellero@brickedbrain.com>
| * | mtd: nand: mxs: fix PIO_WORDs in mxs_nand_read_buf()Luca Ellero2015-03-30-1/+1
| |/ | | | | | | | | | | There is only one pio_word in this DMA transaction so data field must be 1. Signed-off-by: Luca Ellero <luca.ellero@brickedbrain.com>
generated by cgit v1.1 at 2024-09-18 11:05:19 +0000