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* mmc: SEND_OP_COND considers card capabilities (voltage)Raffaele Recalcati2011-04-13-3/+18
| | | | | | | | | | | The first SEND_OP_COND (CMD1) command added is used to ask card capabilities. After it an AND operation is done between card capabilities and host capabilities (at the moment only for the voltage field). Finally the correct value is sent to the MMC, waiting that the card exits from busy state. Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: checking status after commands with R1b responseRaffaele Recalcati2011-04-13-3/+59
| | | | | | | | | | It is recommended to check card status after these kind of commands. This is done using CMD13 (SEND_STATUS) JEDEC command until the card is ready. In case of error the card status field is displayed. Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: remove duplicated header fileMinkyu Kang2011-04-13-1/+0
| | | | | Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: add generic mmc spi driverThomas Chou2011-04-13-20/+354
| | | | | | | | | | | | | This patch supports mmc/sd card with spi interface. It is based on the generic mmc framework. It works with SDHC and supports multi blocks read/write. The crc checksum on data packet is enabled with the def, There is a subcomamnd "mmc_spi" to setup spi bus and cs at run time. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: constify & localize dataMike Frysinger2011-04-13-2/+2
| | | | | | | These local vars need not be writable nor exported. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* drivers/mmc/fsl_esdhc.c: reordered testsFrans Meulenbroeks2011-04-13-3/+3
| | | | | | | | | | | | As DATA_ERROR includes the value IRQSTAT_DTOE, a timeout error would yield the first error return instead of TIMEOUT. By swapping the test TIMEOUTs are reported as such An alternate solution would be to remove the IRQSTAT_DTOE from the DATA_ERROR define but as that one might be less desired I've opted for the simplest solution Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* add CONFIG_SPI_IDLE_VAL for cf_spi.c to allow use of spi_mmcWolfgang Wegner2011-04-13-3/+11
| | | | | | | | | | This patch adds CONFIG_SPI_IDLE_VAL to cf_spi.c The default setting is 0x0 to behave same as current version, in case CONFIG_SPI_MMC is set, the value is set to 0xFFFF (all ones). In either case, the value can be overwritten by board configuration. Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de> Signed-off-by: Andy Fleming <afleming@freescale.com>
* MMC: Max blocks value adjustableMatt Waddel2011-04-13-10/+9
| | | | | | | | | | The maximum blocks value was hardcoded to 65535 due to a 16 bit register length. The value can change for different platforms. This patch makes the default the current value of 65535, but it is configurable for other platforms. Signed-off-by: Matt Waddel <matt.waddel@linaro.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* SD1.00 wide-bus fixAlagu Sankar2011-04-13-3/+3
| | | | | | Fixed a bug wherein SD version 1.0 cards were not configured for 4-bit mode Signed-off-by: Alagu Sankar <alagusankar@embwise.com>
* ftwdt010_wdt: move header to include/faraday and enhanceMacpaul Lin2011-04-12-108/+7
| | | | | | | | | | | | | 1. Move header to include/faraday 2. Fix include path in ftwdt010_wdt.c 3. Fix function prototype and declaration to - ftwdt010_wdt_settimeout - ftwdt010_wdt_reset - ftwdt010_wdt_disable 4. Add "#if definde (CONFIG_HW_WATCHDOG)" let user have flexibilty to choose which better to his product. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
* Fix misc spelling errors found by lintianLoïc Minier2011-04-12-1/+1
| | | | Signed-off-by: Loïc Minier <loic.minier@linaro.org>
* ftwdt010_wdt: support faraday ftwdt010 watchdogMacpaul Lin2011-04-11-0/+206
| | | | | | | | Faraday ftwdt010 watchdog is an architecture independant watchdog. It is usually used in SoC chip design. Signed-off-by: Macpaul Lin <macpaul@andestech.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Net: Add Intel E1000 82574L PCIe card supportRoy Zang2011-04-11-8/+31
| | | | | | | | | Add Intel E1000 82574L PCIe card support. Test on MPC8544DS and MPC8572 board. Add the missing contact information for future support. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* ea20: fix undefined PHY_* errorsBen Gardiner2011-04-11-3/+3
| | | | | | | | | | | This patch fixes ea20 after 8ef583a0351590a91394499eb5ca2ab8a703d959 where the u-boot custom PHY_ macros were replaced with those of linux/mii.h MII_ definitions except in the RMII support for davinci_emac. Probably also due to the merge path of changes in 2010.12. Signed-off-by: Ben Gardiner<bengardiner@nanometrics.ca> CC: Mike Frysinger <vapier@gentoo.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* sf: unify read functionsMike Frysinger2011-04-11-157/+22
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* sf: unify erase functionsMike Frysinger2011-04-11-335/+83
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* sf: unify status polling for ready bitMike Frysinger2011-04-11-283/+81
| | | | | | | | All of the spi flash drivers implement the status register polling for detecting the device ready state, so unify them all in a new helper function -- spi_flash_wait_ready. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* sf: unify read/write helpersMike Frysinger2011-04-11-48/+19
| | | | | | | These functions largely do the same exact thing, so unify them all into one basic function. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-04-10-5/+40
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| * fsl_esdhc: Deal with watermark level register related changesPriyanka Jain2011-04-10-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add P1021 specific QE and UEC supportHaiying Wang2011-04-05-1/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal. Also added relevant QE support defines unique to P1021. The P1021 QE is shared on P1012, P1016, and P1025. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2011-04-10-6/+9
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| * | Blackfin: bfin_sdh: add support for multiblock operationsSonic Zhang2011-04-08-4/+5
| | | | | | | | | | | | | | | | | | | | | Don't forget to count full data size for the multiblock operation request. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: bfin_sdh: set all timer bits before transferCliff Cai2011-04-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The timer register is 32bits, not 16bit, so 0xFFFF won't fill it. Write out -1 to make sure to fill the whole thing. Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: BF50x: new processor portMike Frysinger2011-04-08-1/+3
| |/ | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | mtd, cfi: introduce void flash_protect_default(void)Heiko Schocher2011-04-07-36/+41
| | | | | | | | | | | | | | | | collect code which protects default sectors in a function, called flash_protect_default. So boardspecific code can call it too. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | cfi_flash: use AMD fixups for AMIC (e.g. A29L160A series) tooMario Schuknecht2011-04-07-1/+2
|/ | | | | | Signed-off-by: Mario Schuknecht <m.schuknecht@dresearch.de> Signed-off-by: Steffen Sledz <sledz@dresearch.de> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-04-05-2/+54
|\ | | | | | | | | | | | | Conflicts: drivers/usb/host/ehci-pci.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * tsec: add AR8021 PHY supportLi Yang2011-04-04-0/+23
| | | | | | | | Signed-off-by: Li Yang <leoli@freescale.com>
| * echi: add ULI1575 PCI IDZhao Chenhui2011-04-04-0/+1
| | | | | | | | | | | | | | | | Add ULI1575 EHCI controller to the list of the supported devices. Signed-off-by: Zhao Chenhui <b35336@freescale.com> Acked-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/8xxx: Fix LAW init to respect pre-initialized entriesKumar Gala2011-04-04-0/+20
| | | | | | | | | | | | | | | | | | | | If some pre-boot or earlier stage bootloader (NAND SPL) has setup LAW entries consider them good and mark them used. In the NAND SPL case we skip re-initializing based on the law_table since the SPL phase already did that. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_pci: Add support for FSL PCIe controllers v2.xPrabhakar Kushwaha2011-04-04-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FSL PCIe controller v2.1: - New MSI inbound window - Same Inbound windows address as PCIe controller v1.x Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window FSL PCIe controller v2.2 and v2.3: - Different addresses for PCIe inbound window 3,2,1 - Exposed PCIe inbound window 0 - New PCIe interrupt status register Added new Interrupt Status register to struct ccsr_pci & updated pit_t array size to reflect the 4 inbound windows. To maintain backward compatiblilty, on V2.2 or greater controllers we start with inbound window 1 and leave inbound 0 with its default value (which maps to CCSRBAR). Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ehci-pci: Add PCI EHCI controllerTrübenbach, Ralf2011-04-02-1/+2
| | | | | | | | | | | | | | | | | | | | This patch adds support for the PI7C9X442SL PCIe EHCI host controller from Pericom. Tested at P4080DS eval board from Freescale. Signed-off-by: Ralf Trübenbach <ralf.truebenbach@men.de> Cc: Remy Bohmer <linux@bohmer.net>
* | usb: musb: blackfin: check anomaly workarounds at runtime tooMike Frysinger2011-04-02-3/+26
| | | | | | | | | | | | | | | | The anomaly workarounds we need for older silicon might break things if used on newer versions where the anomalies don't exist. So check the silicon rev at runtime too. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | usb: musb: blackfin: make clkin configurableMike Frysinger2011-04-02-1/+6
|/ | | | | | Not everyone has a 24MHz clkin to the USB, so let board porters override. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* atmel_nand: don't require CONFIG_SYS_NAND_ENABLE_PINmichael2011-04-01-0/+2
| | | | | | | | | | | | If NCE is hooked up to NCS3, we don't need to (and can't) explicitly set the state of the NCE pin. Instead, the controller asserts it automatically as part of a command/data access. Only "CE don't care"-type NAND chips can be used in this manner. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Reinhard Meyer <u-boot@emk-elektronik.de>
* NAND: add support for reading ONFI page tableFlorian Fainelli2011-04-01-49/+144
| | | | | | | | | | | | This patch adds support for reading an ONFI page parameter from a NAND device supporting it. If this is the case, struct nand_chip onfi_version member contains the supported ONFI version, 0 otherwise. This allows NAND drivers past nand_scan_ident to set the best timings for the NAND chip. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: add more watchdog resetsScott Wood2011-04-01-0/+8
| | | | | | | Poke the watchdog in a variety of looping constructs, which could take a long time to complete. Signed-off-by: Scott Wood <scottwood@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-03-31-0/+7
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| * powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCsPrabhakar Kushwaha2011-03-29-0/+7
| | | | | | | | | | | | | | | | | | | | The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | cfi_flash: fix bug with flash banks with different sector numbersMartin Krause2011-03-28-0/+5
|/ | | | | | | | | | | | | | | The function find_sector() does not take into account if the flash bank has changed since the last call. This could lead to illegal accesses inside and beyond the flash_info_t info strcture. For example if the current flash bank has less sectors than the last used flash bank. This patch adds two cheks. One that insures, that the current sector does not exceed the allowed maximum (which is always a good idea). And one that checks if the current access is to the same flash bank as the last access. If not, the search loop will start with sector 0. Signed-off-by: Martin Krause <martin.krause@tqs.de> Signed-off-by: Stefan Roese <sr@denx.de>
* Coding Style cleanup: remove trailing empty linesWolfgang Denk2011-03-27-4/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* S5P: mmc: Resolved interrupt error during mmc_initChander Kashyap2011-03-27-1/+1
| | | | | | | | | | | | Blocksize was hardcoded to 512 bytes. But the blocksize varies depeding on various mmc subsystem commands (between 8 and 512). This hardcoding was resulting in interrupt error during data transfer. It is now calculated based upon the request sent by mmc subsystem. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* net: ftmac100: update get_timer() usagesPo-Yu Chuang2011-03-21-3/+3
| | | | | | | | Use get_timer() the same way as drivers/net/ftgmac100.c Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com> Reviewed-by: Macpaul Lin <macpaul@gmail.com> Tested-by: Macpaul Lin <macpaul@gmail.com>
* net: ftmac100: remove unnecessary volatilesPo-Yu Chuang2011-03-21-6/+6
| | | | | | Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com> Reviewed-by: Macpaul Lin <macpaul@gmail.com> Tested-by: Macpaul Lin <macpaul@gmail.com>
* net: sh_eth: add support for SH7757's ETHERYoshihiro Shimoda2011-03-16-4/+86
| | | | | | | SH7757 has ETHER and GETHER. This patch supports EHTER only. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* fsl_esdhc: Correcting esdhc timeout counter calculationPriyanka Jain2011-03-07-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | - Timeout counter value is set as DTOCV bits in SYSCTL register For counter value set as timeout, Timeout period = (2^(timeout + 13)) SD Clock cycles - As per 4.6.2.2 section of SD Card specification v2.00, host should cofigure timeout period value to minimum 0.25 sec. - Number of SD Clock cycles for 0.25sec should be minimum (SD Clock/sec * 0.25 sec) SD Clock cycles = (mmc->tran_speed * 1/4) SD Clock cycles - Calculating timeout based on (2^(timeout + 13)) >= mmc->tran_speed * 1/4 Taking log2 both the sides and rounding up to next power of 2 => timeout + 13 = log2(mmc->tran_speed/4) + 1 Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Mingkai Hu <Mingkai.Hu@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_law: Fix LAW printing functionKumar Gala2011-02-22-1/+1
| | | | | | | | | | | | | We had an extra '0x' in the output of the LAWAR header that would cause output like: LAWBAR11: 0x00000000 LAWAR0x11: 0x80f0001d intead of: LAWBAR11: 0x00000000 LAWAR11: 0x80f0001d Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mvmfp: add MFP configuration support for PANTHEONLei Wen2011-02-21-0/+2
| | | | | | | This patch adds the Multiple Function Pin configuration support for Marvell PANTHEON SoCs Signed-off-by: Lei Wen <leiwen@marvell.com>
* serial: add pantheon soc supportLei Wen2011-02-21-0/+2
| | | | Signed-off-by: Lei Wen <leiwen@marvell.com>
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